NJRC NJU6637CH

Preliminary
NJU6637
Preliminary
16-CHARACTER 3-LINE DOT MATRIX LCD
CONTROLLER DRIVER
■ GENERAL DESCRIPTION
The NJU6637 is a 1Chip Dot Matrix LCD controller
driver for up to 16-character 3-line display.
It contains microprocessor Interface circuits, Instruction
decoder controller, character generator ROM/RAM and
common and segment drivers.
The bleeder resistance generates for LCD Bias voltage
Internally.
The CR oscillator Incorporates C and R, therefore no
external components for oscillation are required.
The microprocessor Interface circuits which operate
1MHz frequency, can be connected directly to serial I/F
microprocessor.
The character generator consists of 10,200 bits ROM
and 8 x 5 bits RAM. The standard version ROM is
coded with 255 characters including capital and small
letter fonts.
The 24-common and 80-segment drive up to
16-character 3-line LCD panel which divided two
common electrode blocks.
The rectangle outlook is very applicable to COG.
■ PACKAGE OUTLINE
NJU6637CH
■ FEATURES
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16-character 3-line Dot Matrix LCD Controller Driver
Serial Direct Interface with Microprocessor
Display Data RAM
:48 x 8 bits : Maximum 16-character 3line Display
Character Generator ROM
:10,200 bits ; 255 characters for 5 x 8 dots
Character Generator RAM
:8 x 5 bits ; 1 Patterns( 5 x 8 dots)
Microprocessor direst accessing to Display Data RAM and Character Generator RAM
High Voltage LCD Driver
:24-common / 80-segment
Duty Ratio
:1/24 Duty
Maximum Display Characters :48 Characters
Common Driver Order Assignment by mask option
Version
COM1 to COM24 (PAD Name)
NJU6637A COM1 to COM24
NJU6637B COM24 to COM1
Useful Instruction Set
Clear Display, Returns Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink, Cursor Shift,
Character Shift.
Power On Reset / Hardware Reset Function
Oscillation Circuit on chip
Bleeder Resistance on chip
Low Power Consumption
Operating Voltage --- +3V
Package Outline --- Bumped Chip
C-MOS Technology
Ver.1.1
Preliminary
NJU6637
■ PAD LOCATION
DUMMY33
COM9
COM16
SEG1
SEG8
DUMMY34
DUMMY35
NJU6637A Mode A (SEL=”L”)
DUMMY36
DUMMY32
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG9
DUMMY31
DUMMY30
x
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
VDD
VDD
VDD
VSS
VSS
VSS
V5
V5
V5
OSC2
OSC1
DUMMY10
y
SEG80
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY3
DUMMY2
1
DUMMY50
Bump Size : 90 x 45um
Bump Height : 17.5um
Bump Material :Au
DUMMY53
COM1
COM8
COM17
COM24
DUMMY52
DUMMY51
Chip Size : 5.48 x 1.68mm
Chip Size : X=0um, Y=0um
Chip Thickness : 625um+30um
DUMMY1
Preliminary
DUMMY33
COM9
COM16
SEG80
SEG73
DUMMY34
DUMMY35
NJU6637A Mode B (SEL=”H”)
NJU6637
DUMMY36
DUMMY32
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG72
DUMMY31
DUMMY30
x
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
VDD
VDD
VDD
VSS
VSS
VSS
V5
V5
V5
OSC2
OSC1
DUMMY10
y
SEG1
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY3
DUMMY2
1
DUMMY50
DUMMY1
DUMMY53
COM1
COM8
COM17
COM24
DUMMY52
DUMMY51
Preliminary
DUMMY33
COM16
COM9
SEG1
SEG8
DUMMY34
DUMMY35
NJU6637B Mode A (SEL=”L”)
NJU6637
DUMMY36
DUMMY32
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG9
DUMMY31
DUMMY30
x
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
VDD
VDD
VDD
VSS
VSS
VSS
V5
V5
V5
OSC2
OSC1
DUMMY10
y
SEG80
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY3
DUMMY2
1
DUMMY50
DUMMY1
DUMMY53
COM24
COM17
COM8
COM1
DUMMY52
DUMMY51
Preliminary
DUMMY33
COM16
COM9
SEG80
SEG73
DUMMY34
DUMMY35
NJU6637B Mode B (SEL=”H”)
NJU6637
DUMMY36
DUMMY32
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG72
DUMMY31
DUMMY30
x
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
VDD
VDD
VDD
VSS
VSS
VSS
V5
V5
V5
OSC2
OSC1
DUMMY10
y
SEG1
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY3
DUMMY2
1
DUMMY50
DUMMY1
DUMMY53
COM24
COM17
COM8
COM1
DUMMY52
DUMMY51
Preliminary
Alignment Mark size
63
10.8
14.4 12.6 14.410.8
DUMMY1
DUMMY32
10.8
y
14.4
x
12.6
63
14.4
10.8
63
DUMMY36
DUMMY50
10.8
14.4 12.6 14.410.8
10.8
14.4
y
x
39.6
14.4
10.8
90
NJU6637
Preliminary
NJU6637
■ PAD COORDINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PAD Name
SEL=H
SEL=L
DMY1
DMY2
DMY3
DMY4
DMY5
DMY6
DMY7
DMY8
DMY9
DMY10
OSC1
OSC2
V5
V5
V5
VSS
VSS
VSS
VDD
VDD
VDD
TEST
SEL
RESET
RS
SCL
SI
CS
DMY11
DMY12
DMY13
DMY14
DMY15
DMY16
DMY17
DMY18
DMY19
DMY20
DMY21
DMY22
DMY23
DMY24
DMY25
DMY26
DMY27
DMY28
DMY29
DMY30
DMY31
DMY32
DMY1
DMY2
DMY3
DMY4
DMY5
DMY6
DMY7
DMY8
DMY9
DMY10
OSC1
OSC2
V5
V5
V5
VSS
VSS
VSS
VDD
VDD
VDD
TEST
SEL
RESET
RS
SCL
SI
CS
DMY11
DMY12
DMY13
DMY14
DMY15
DMY16
DMY17
DMY18
DMY19
DMY20
DMY21
DMY22
DMY23
DMY24
DMY25
DMY26
DMY27
DMY28
DMY29
DMY30
DMY31
DMY32
Chip Size(5.48mm x 1.68mm)
X= µm
Y= µm
PAD No.
-2599
-2520
-2460
-2400
-2340
-2280
-2220
-2160
-2100
-2040
-1860
-1620
-1440
-1380
-1320
-1080
-1020
-960
-900
-840
-780
-540
-300
-60
180
420
660
1140
1320
1380
1440
1500
1560
1620
1680
1740
1800
1860
1920
1980
2040
2100
2160
2220
2280
2340
2400
2460
2520
2599
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
-690
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PAD Name
SEL=H
SEL=L
DMY33
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
DMY34
DMY35
DMY36
DMY37
DMY38
DMY39
DMY40
DMY41
DMY42
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
DMY33
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
DMY34
DMY35
DMY36
DMY37
DMY38
DMY39
DMY40
DMY41
DMY42
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
X= µm
Y= µm
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2599
2520
2460
2400
2340
2280
2220
2160
2100
2040
1980
1920
1860
1800
1740
1680
1620
1560
1500
1440
1380
1320
1260
1200
1140
1080
1020
960
900
840
780
-540
-480
-420
-360
-300
-240
-180
-120
-60
0
60
120
180
240
300
360
420
480
540
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
Preliminary
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
PAD Name
SEL=H
SEL=L
SEG48
SEG33
SEG34
SEG47
SEG35
SEG46
SEG36
SEG45
SEG44
SEG37
SEG43
SEG38
SEG42
SEG39
SEG41
SEG40
SEG40
SEG41
SEG39
SEG42
SEG38
SEG43
SEG37
SEG44
SEG36
SEG45
SEG35
SEG46
SEG34
SEG47
SEG33
SEG48
SEG32
SEG49
SEG31
SEG50
SEG30
SEG51
SEG29
SEG52
SEG28
SEG53
SEG27
SEG54
SEG26
SEG55
SEG25
SEG56
SEG24
SEG57
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
DMY43
DMY44
PAD No.
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
DMY43
DMY44
X= µm
Y= µm
PAD No.
720
660
600
540
480
420
360
300
240
180
120
60
0
-60
-120
-180
-240
-300
-360
-420
-480
-540
-600
-660
-720
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
-780
-840
-900
-960
-1020
-1080
-1140
-1200
-1260
-1320
-1380
-1440
-1500
-1560
-1620
-1680
-1740
-1800
-1860
-1920
-1980
-2040
-2100
-2160
-2220
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
698
NJU6637
PAD Name
SEL=H
SEL=L
DMY45
DMY46
DMY47
DMY48
DMY49
DMY50
DMY51
DMY52
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DMY53
DMY45
DMY46
DMY47
DMY48
DMY49
DMY50
DMY51
DMY52
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DMY53
X= µm
Y= µm
-2280
-2340
-2400
-2460
-2520
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
-2599
698
698
698
698
698
698
540
480
420
360
300
240
180
120
60
0
-60
-120
-180
-240
-300
-360
-420
-480
-540
Preliminary
NJU6637
■ BLOCK DIAGRAM
OSC1
RESET
Address
Counter
Timing
Gen.
Segment
Driver
SEL
Character
Generator
ROM(CGROM)
10,200bits
Latch
Character
Generator
RAM(CGRAM)
8 x 5bits
Cursor Blink Cont.
SI
Data
Reg.(DR)
CS
I/O Buffer
SCL
Common
Driver
RS
80bit
Display Data RAM (DDRAM)
48 x 8bits
24bit
Shift Reg.
Power on
Reset
Instruction
Decoder(ID)
Instruction Reg.(IR)
OSC2
CR
OSC
VSS
Parallel to Serial Convertor
VDD
V1
V2
V3
V4
V5
V5
80bit
Shift Reg.
COM1 to
COM24
SEG1 to
SEG80
Preliminary
NJU6637
■ TERMINAL DESCRIPTION
PAD No.
SYMBOL
I/O
19-21
16-18
13-15
11
VDD
VSS
V5
OSC1
–
12
OSC2
O
25
RS
I
Oscillation Frequency Adjustment Terminals. Normally Open.
(Oscillation C and R are Incorporated, Osc Freq.=145kHZ)
Oscillation Frequency Adjustment Terminals. Normally Open.
This terminal also operates as the clock frequency monitor.
Resister selection signal Input
"1":Data Register
Shift clock input
–
I
FUNCTION
Power Source : VDD = +3V,
GND : VSS = 0V
LCD driving Power Source
"0":Instruction Resister
26
SCL
I
28
27
23
CS
SI
SEL
I
I
I
52-59
159-174
60-67
77-148
24
COM1 – COM24
O
Chip select signal input
Data input terminal
Segment driver location order select terminal
"0": Mode A
"1": Mode B
LCD Common driving signal Terminals
SEG1 – SEG80
O
LCD segment driving signal Terminals
RESET
I
22
TEST
I
1-9
22-51
68-76
149-158
175
DUMMY1 –
DUMMY53
–
Reset Terminal
When the “L” level Input over than 1.2ms to this terminal,
the system will be reset.(fOSC=145kHz)
Maker Test Terminal
This terminal should be connected to Vss or open.
Dummy Terminal
These terminals are electrically open.
Preliminary
NJU6637
■ FUNCTIONAL DESCRIPTION
(1)Description for each blocks
(1-1)Register
The NJU6637 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores Instruction codes such as “Clear Display” and “Return Home”, and address
data for Display Data RAM (DD RAM) and Character Generator RAM (CG RAM).
The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the
DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred from the Register automatically to the
DD RAM or CG RAM by Internal operation.
These two registers are selected by the selection signal RS.
(1-2)Address counter (AC)
The address Counter (AC) addresses the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is
transferred from Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is
also determined by this instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC)
increments (or decrements) “1” automatically.
(1-3)Display Data RAM (DD RAM)
The display data RAM (DD RAM) consisting of 48 x 8 bits stores up to 48-character display data
represented in 8-bit code.
The DD RAM address data set in the address Counter (AC) is represented in hexadecimal.
AC
←Higher order bit
AC5
AC4
AC6
AC3
Hexadecimal
Lower order bit→
AC2
AC1
AC0
(Example) DD RAM address “ 08 ”
0
0
0
1
0
0
0
0
Hexadecimal
8
16-character 2-line Display
st
1 line
nd
2 line
rd
3 line
1
00
10
20
2
01
11
21
3
02
12
22
4
03
13
23
5
04
14
24
6
05
15
25
7
06
16
26
8
07
17
27
9
08
18
28
10
09
19
29
11
0A
1A
2A
12
0B
1B
2B
13
0C
1C
2C
14
0D
1D
2D
15
0E
1E
2E
16
0F
1F
2F
←Display position
←DD RAMaddress(Hex.)
The relation between DD RAM address and display position on the LCD shown below.
[ Left Shift Display ]
(00) ←
(10) ←
(20) ←
01
11
21
02
12
22
03
13
23
04
14
24
05
15
25
06
16
26
07
17
27
08
18
28
09
19
29
0A
1A
2A
0B
1B
2B
0C
1C
2C
0D
1D
2D
0E
1E
2E
0F
1F
2F
00
10
20
04
14
24
05
15
25
06
16
26
07
17
27
08
18
28
09
19
29
0A
1A
2A
0B
1B
2B
0C
1C
2C
0D
1D
2D
0E
1E
2E
[ Right Sift Display ]
0F
1F
2F
00
10
20
01
11
21
02
12
22
03
13
23
→ (0F)
→ (1F)
→ (2F)
Preliminary
NJU6637
(1-4)Character Generator ROM(CG ROM)
The Character Generator ROM (CG ROM) generates 5 x 8 dots character pattern represented in 8-bit
character codes.
The storage capacity is up to 255 kinds of 5 x 8 dots character pattern. The correspondence between
character code and standard character pattern is shown in Table 2.
User-defined character pattern ( Custom Font ) are also available by mask option.
Table 2. CG ROM Character Pattern ( ROM version –02 )
Lower 4 bit (Hexadecimal)
Upper 4 bit (Hexadecimal)
Preliminary
NJU6637
(1-5)Character Generator RAM
The character generator RAM (CG RAM) stores any kinds of character pattern in 5 x 8 dots written by
the user program to display user’s original character pattern. The CG RAM stores 1 kinds of character
in 5 x 8 dots mode.
To display user’s original character pattern stored in the CG RAM, the address data (00)H should be
written to the DD RAM as shown in Table 2.
Table 3. shows the correspondence among the character pattern, CG RAM address and data.
Table 3. Correspondence of CG RAM address, DD RAM character code
Character Code
(DD RAM data)
7654
3210
←
→
Upper bit
Lower bit
0000
0000
CG RAM address
7654
←
3
Upper bit
0 1 0 0
210
→
Lower bit
0
and CG RAM character pattern (5 x 8 dots)
Character pattern
(CG RAM data)
43210
←
→
Upperbit
000
001
010
011
100
101
110
111
Lowerbit
11110
10001
10001
11110
10100
10010
10001
00000
Character
Pattern
Example
← Cursor Position
Notes: 1. Character code bits 0 and 1 correspond to the CG RAM address 3 and 4.
2. CG RAM address 0, 1 and 2 designate a character pattern line position.
The 8th line is the cursor position and the display is performed by logical OR with cursor.
Therefore, in case of the cursor display, the data of 8th line should be “0”.
If there is “1” in the 8th line, the bit “1” is always displayed on the cursor position regardless of
cursor existence.
3. Character pattern row position corresponding to the CG RAM data bits 0 to 4 are all shown above.
4. ”1” for CG RAM data corresponds to display On and “0” to display Off.
(1-6)Timing Generator
The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal
circuit operation.
RAM read timing for the display and internal operation timing for MPU access are separately generated,
so that they may not interfere with each other.
Therefore, when the data write to the DD RAM for example, there will be undesirable Influence, such as
flickering, in areas other than the display area.
(1-7) LCD Driver
LCD driver consists of 24-common driver and 80-segment driver.
The 80 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift
performed completely. This latched data controls display driver to output LCD driving waveform.
(1-8) Common Driver Assignment
The scanning order can be assigned by mask option as shown as follows:
PAD No.
Pin name
Ver. A
Ver. B
174
COM1
COM1
COM24
167
COM8
COM8
COM17
COM Outputs Terminals
166
159
COM17
COM24
COM17
COM24
COM8
COM1
59
COM16
COM16
COM9
52
COM9
COM9
COM16
Preliminary
NJU6637
(1-9) Cursor Blinking Control Circuit
This circuits controls cursor On/Off and cursor position character blinks. The cursor or blinks
appears in the digit position at the DD RAM address set in the address counter(AC).
When the address counter is (08)H, a cursor position is shown as follows:
AC6
0
AC
st
1 line
nd
2 line
rd
3 line
1
00
10
20
2
01
11
21
3
02
12
22
4
03
13
23
AC5
0
5
04
14
24
AC4
0
6
05
15
25
7
06
16
26
AC3
1
8
07
17
27
AC2
0
9
08
18
28
AC1
0
10
09
19
29
11
0A
1A
2A
AC0
0
12
0B
1B
2B
13
0C
1C
2C
14
0D
1D
2D
15
0E
1E
2E
16
0F
1F
2F
← Display Position
← DD RAM Address
(Hexadecimal)
Cursor Position
Note) The cursor or blinks appears when the address counter (AC) selects the CG RAM.
But the displayed cursor and blink are meaningless.
If the AC stores the CG RAM address data, the cursor and blink are displayed in the meaningless position.
(2)Power on Initialization by internal circuits
(2-1) Initialization By internal Reset circuits
The NJU6637 is initialized automatically by the internal power on initialization circuits when the power is
turned on. In the internal power on initialization, following instructions are executed.
During the internal power on initialization is kept 4ms after VDD = 2.4V. (fosc=145KHz)
Initialization flow is shown below:
Display On/Off
Control
D=0
C=0
B=0
:Display Off
:Cursor Off
:Cursor Blink Off
Entry Mode Set
I/D=1
S=0
:Increment by 1
:No Shift
Clear Display
Note) If the condition of power supply rise time described in the Electrical Characteristics is not satisfied, the
internal Power on initialization Circuits will not operate and initialization will not be performed.
In this case, the initialization by MPU software is required.
(2-2) Initialization By Hardware
The NJU6637 incorporates RESET terminal to initialize the all system. When the “L” level input over
than 1.2ms to the RESET terminal, the reset sequence is executed. In this time, the initialization during
4ms after RESET terminal goes to “H”.
•
Operation timing
Over 1.2ms
External Reset
Signal
Initialization set time
4ms
Preliminary
NJU6637
(3)Instructions
The NJU6637 incorporates two resisters, which are Instruction Register (IR) and a Data Register (DR).
These two registers store control information temporarily to allow interface between NJU6637 and MPU or
peripheral ICs operating different cycles. The operation of NJU6637 is determined by this control signal
from MPU. The control information includes register selection signals (RS) and data bus signals (DB0 to
DB7). Table 5. Shows each instruction and its operating time.
Note) The execution time mentioned in Table 5. is based on fcp or fOSC=145kHz.
If the oscillation frequency is changed, the execution time is also changed.
INSTRUCTION
Table 5. Table of Instruction
CODE
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Maker Test
0
0
0
0
0
0
0
0
0
Clear Display
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
∗
0
0
0
0
0
0
1
I/D
S
0
0
0
0
0
1
D
C
B
0
0
0
0
1
∗
∗
0
1
Return Home
Entry Mode Set
Display ON/OFF
Control
Cursor or Display
Shift
S/C R/L
Set RAM Address
Write Data to
CG or DD RAM
Explanation of
Abbreviation
*:Don't care
1
RAM address
Write Data(DD RAM)
∗
∗
∗
DESCRIPTION
All “0” code is using for maker
testing.
Display clear and sets DD RAM
address 0 in AC.
Sets DD RAM address 00H In AC
and returns display being shifted to
original position.
DD
RAM
contents
remain
unchanged.
Sets cursor move direction and
species shift of display are
performed In data write.
I/D=1:Increment,
I/D=D:Decrement,
S=1:Accopanies display shift.
Sets of display On/Off(D), cursor
On/Off(C) and blink of cursor
position character(B)
Move cursor and shifts display
without
changing
DD
RAM
contents.
S/C=1 : Display shift
S/C=0 : Cursor shift
R/L=1 : Shift to right
R/L=0 : Shift to the left
Sets RAM address.
After this
instruction, the data is transferred
to RAM.
Writes data into CG or DD RAM.
(CG RAM)
DD RAM : Display data RAM, CG RAM : Character generator RAM
ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address
AC : Address counter used for both DD and CG RAM
EXEC TIME
(fOSC=145kHz)*
–
2ms
0µs
0µs
0µs
0µs
0µs
55µs
Preliminary
NJU6637
(3-1)Description of instruction
a) Maker Test
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
All “0” code is using device testing mode ( only for maker ).
b) Clear Display
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
1
Clear display instruction is executed when the code “1” is written into DB0.
when this instruction is executed, the space code (20)H is written into every DD RAM address, the
DD RAM address 0 is set into the address counter and entry mode is set an increment. If the
st
cursor or blink are displayed, they are returned to the left end of the 1 line on the LCD.
The S of entry mode and CG RAM data does not change.
Note: The character pattern for character code (20)H must be blank code in the user-defined
character pattern( Custom font ).
c) Return Home
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
∗
∗=Don’t Care
Return home instruction is executed when the code “1” is written Into DB1. When this Instruction
is executed, the DD RAM address 0 is set to address counter. Display is returned to the original
position if shifted, the cursor or blink is returned to the left end of the LCD. If the cursor or blink are
on the display, the DD RAM contents are not changed.
d) Entry Mode Set
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
1
DB1
I/D
DB0
S
Entry mode set instruction which sets cursor moving direction and display shift On/Off, is executed
when the code “1” is written into DB2 and the codes of (I/D) and (S) are written into DB1 (I/D) and
DB0 (S) as shown below.
(I/D) sets the address increment or decrement, and the (S) sets the entire display shift in the DD
RAM writing.
I/D
1
0
S
1
0
FUNCTION
Address increment : The address of the DD RAM increment ( +1) when
the write, and the cursor or blink moves to the right.
Address decrement : The address of the DD or CG RAM decrement
( -1) when the write, and the cursor or blink move to the left.
FUNCTION
Entire display shift.
The shift direction is determined by I/D: shift to the left at I/D=1 and shift
to the right at the I/D=0. The shift is operated with only the character, so
that it looks as if the cursor stands still and the display moves. The
display does not shift when reading from the DD RAM and writing into
CG RAM.
The display does not shifting
Preliminary
NJU6637
e) Display ON/OFF Control
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
D
DB1
C
DB0
B
Display On/Off control instruction which controls the display On/Off, the cursor On/Off and the
cursor position character blink, is executed when the code “1” is written into DB3 and the codes of
(D), (C) and (B) are written into DB2(D), DB1(C) and DB0(B) as shown below.
D
1
0
FUNCTION
Display On.
Display Off. In this mode, the display data remains in the DD RAM so
that it is retrieved immediately on the display when the D change to 1.
C
1
0
FUNCTION
Cursor On. The cursor is displayed by 5 dots on the 8th line.
Cursor Off. Even if the display data write, the I/D etc does not change.
B
1
FUNCTION
The cursor position character is blinking. Blinking rate is 600ms at
fOSC=145kHz. The blink is displayed alternatively with all on (it means
all black) and characters display. The cursor and the blink can be
displayed simultaneously.
The character does not blink.
0
!"""!
"!!!"
"!!!"
"!!!"
"""""
"!!!"
"!!!"
"""""
!"""!
"!!!"
"!!!"
"!!!"
"""""
"!!!"
"!!!"
!!!!!
Character Font 5 x 7dots
(1) Cursor display example
"""""
"""""
"""""
"""""
"""""
"""""
"""""
"""""
Alternating display
(2) Blink display example
f) Cursor Display Shift
Code
RS
0
DB7
0
DB6
0
DB5
0
DB4
1
DB3
S/C
DB2
R/L
DB1
∗
DB0
∗
∗=Don’t Care
The Cursor/Display shift instruction shifts the cursor position or display the right or left without
writing reading display data. This function is used to correct or search the display. The cursor
moves to the 2nd line when it passes the 16th digit of the 1st line. Notice that the every 1st to 3rd
line displays shift at the same time. When the displayed data are shifted repeatedly, each line
moves only horizontally.
The 2nd and 3rd line display does not shift into the 1st and 2nd line.
The contents of address counter (AC) is not changed by operation of display shift only.
This instruction is executed when the code “1” is written into DB4 and the codes of (S/C) and (R/L)
are written into DB3 (S/C) and DB2(R/L) as shown below.
S/C
R/L
FUNCTION
0
0
Shifts the cursor position to the left ((AC) is decrement by 1)
0
1
Shifts the cursor position to the right ((AC) is incremented by 1)
1
0
Shifts the entire display to the left and the cursor follows it.
1
1
Shifts the entire display to the right and the cursor follows it.
Preliminary
NJU6637
g) Set RAM Address
Code
RS
0
DB7
1
DB6
DB5
DB4
A
A
A
←Higher order bit
DB3
A
DB2
DB1
DB0
A
A
A
Lower order bit→
The RAM address set instruction is executed when the code "1" is written into DB7 and the
address is written into DB6 to DB0 as shown above.
The address data (DB6 to DB0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed RAM.
The RAM includes DD RAM and CG RAM, and these RAMs are shared by address as shown
below.
DD RAM address
DD RAM 1-Line
: (00)H – (0F)H
DD RAM 2-Line
: (10)H – (1F)H
DD RAM 2-Line
: (20)H – (2F)H
CG RAM 1character
:
(40)H – (47)H
h) Write Data to CG or DD RAM
•
Write data to DD RAM
Code
•
RS
1
DB7
DB6
DB5
D
D
D
←Higher order bit
DB4
D
DB3
D
DB2
DB1
DB0
D
D
D
Lower order bit→
DB7
DB6
DB5
∗
∗
∗
←Higher order bit
DB4
D
DB3
D
DB2
DB1
DB0
D
D
D
Lower order bit→
Write data to CG RAM
Code
RS
1
∗=Don’t Care
Write Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS)
and code “0” is written into (R/W).
By the execution of this instruction, the binary 5-bit data “DDDDD” are written into the CG RAM,
and the binary 8-bit data “DDDDDDDD” are written into the DD RAM. The selection of the CG
RAM or DD RAM is determined by the previous instruction.
After this instruction execution, the address increment(+1) or decrement(-1) is performed
automatically according to the entry mode set. And the display shift is also executed according to
the previous entry mode set.
Preliminary
NJU6637
(3-2) Initialization by instruction
If the power supply conditions for the correct operation of the internal reset circuits are not method, the
NJU6637 must be initialized by the instruction.
Initialized.
No display appears.
Power On
Wait more than 4 ms
after VDD rises to 2.4V
Display Off
Display Clear
Entry Mode Set
RS
DB7 DB6 DB5
DB4 DB3
DB2 DB1
DB0
0
0
0
0
0
RS
DB7 DB6 DB5
DB4 DB3
DB2 DB1
DB0
0
0
0
0
1
RS
DB7 DB6 DB5
DB4 DB3
DB2 DB1
DB0
0
0
0
1
0
Write data to the CG or DD RAM
and set the instruction.
0
0
0
0
0
0
1
0
0
0
0
1
Example for set address
increment and cursor right shift
when the data write to the DD
RAM.
Preliminary
NJU6637
(4) Bleeder Resistance
Each LCD driving voltage ( V1, V2, V3, V4 ) is generated by the high impedance bleeder resistance
buffered by voltage follower OP-AMP to get a enough display characteristics with low operating current.
The bleeder resistance is set 1/6.3 bias suitable for 1/24 duty ratio and 5MΩ resistance in total.
The capacitor connected between V5 and VDD is needed for stabilizing V5. The determination of the
each capacitance of C1, C2 and C3 generating for LCD operating voltage, is required to operate with
the LCD panel actually. The capacitance for the typical application is shown below :
Power
Supply
LCD Driving Voltage vs. Duty Ratio
Duty Ratio
1/24
Bias
V5
1/6.3
VDD-VLCD
∗ The VLCD is maximum swing of LCD waveform.
NJU6637
VDD
952kΩ
V1
952kΩ
V2
2192kΩ
V3
952kΩ
V4
952kΩ
V5
V5
LCD Driving Voltage example
VLCD
Preliminary
NJU6637
(5) Relation between oscillation frequency and LCD frame frequency.
As the NJU6637 incorporate oscillation capacitor and resistor for CR oscillation, 145kHz oscillation is
available without any external components.
The LCD frame frequency example mentioned below is based on 145kHz oscillation.(1clock =6.875µs)
•
1/24 duty
96 clock
1
2
3
4
••••••
24
1
2
3
4
••••••
24
1
2
3
VLCD
V1
V2
V4
VSS
1 frame
1 frame
1 frame = 6.875 (µs) x 96 x 24 = 15.84 (ms)
Frame frequency = 1 / 15.84 (ms) = 63.1 (Hz)
(6) Interface with MPU
Serial interface circuit is activated when the chip select terminal (CS) goes to "L" level. The data
input is MSB first like as the order of DB7, DB6 ---- DB0.
The input data is entered into the shift register synchronized at the rise edge of the serial clock SCL.
The shift register converted to parallel data at the CS rise edge input.
In case of entering over than 8-bit data, valid data is last 8-bit data.
The time chart for the serial interface is shown below.
Note : The level ("L" or "H") of RS terminals should be set before CS terminal goes to "L" level.
RS
CS
SCL
SI
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Preliminary
NJU6637
■ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Input Voltage
Operating Temperature
Storage Temperature
(Ta=25°C)
SYMBOL
VDD
VLCD
VIN
Topr
Tstg
RATINGS
UNIT
-0.3 – +7.0
VDD-7.0 – VDD+0.3
-0.3 – VDD+0.3
V
V
V
°C
°C
-30 – +80
-55 – +125
NOTE
V5 Terminal
Note 1.) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed.
Using the LSI within electrical characteristics is strongly recommended for normal operation. Use
beyond the electric characteristics conditions will cause malfunction and poor reliability.
Note 2.) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for
the LSI.
Note 3.) All voltage values are specified as VSS =0V
Note 4.) The relation VDD>V5≥VSS, VSS=0V must be maintained.
■ ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Volt.
Input Voltage 1
Input Voltage 2
Output Voltage
Driver
On-resist.(COM)
Driver
On-resist.(SEG)
Driver
On-resist.(COM)
Driver
On-resist.(SEG)
Input Leakage
Current
SYMBOL
SYMBOL
MIN
VDD
VDD
2.4
All Input / Output Terminals except 0.8 VDD
VIH1
OSC1 Terminals
VSS
VIL1
VIH2
VDD-0.5
OSC1 Terminal
VSS
VIL2
VOH
-IOH=0.205mA, VDD=3V
2.0
IOL=1.6mA, VDD=3V
–
VOL
MAX
3.6
VDD
0.2 VDD
VDD
0.5
–
0.5
UNIT
V
V
V
V
V
V
V
±Id=1µA, Vo= VDD,V5
–
–
20
kΩ
RSEG1
±Id=1µA, Vo= VDD,V5
–
–
30
kΩ
RCOM2
±Id=1µA, Vo= V1,V4
–
–
40
kΩ
RSEG2
±Id=1µA, Vo= V2,V3
–
–
50
kΩ
VIN=0 to VDD
-1
–
1
µA
ILI
Operating Current
IDD2
Oscillation
Frequency
LCD Driving
Voltage
V5 Terminal
Current
TYP
3.0
–
–
–
–
–
–
RCOM1
IDD1
LCD Driving
Voltage
(VDD=2.4 – 3.6V, VSS=0V, Ta=25°C)
V1
V2
V3
V4
VDD=3V fOSC=Internal Osc.
V5=2V,during display
VDD=3V fOSC=Internal Osc.
during access, TCYCE=5us
VDD=3V, Ta=25°C, V5=2V
fOSC
VDD=3V, Ta=25°C
VLCD
VDD=3V, V5 Terminal
I5
VDD=3V, V5=2V
T.B.D.
µA
T.B.D.
µA
NOTE
5
6
7
2.08
1.28
-0.54
-1.34
2.21
1.41
-0.41
-1.21
2.34
1.54
-0.28
-1.08
V
110
145
180
kHz
VDD-3
–
VDD-6
V
200
µA
Note 5.) Apply to the OSC2 Terminals.
Note 6.) Except pull-down resistance current. (All input terminal except OSC terminal)
Note 7.) Except Input / Output current but including the current flow on bleeder resistance.
If the input level is medium, current consumption will increase due to the penetration current. Therefore,
the input level must be fixed to “H” or “L”.
Preliminary
NJU6637
■ Bus timing characteristics
•
(VDD=2.4 – 3.6V, VSS=0V, Ta=25°C)
Serial Interface Sequence
PARAMETER
Serial clock cycle time
“High” level
Serial clock width
Low” level
Serial clock rise and fall Time
Chip select pulse width
Chip select set up time
Chip select hold time
Chip Select rise and fall Time
Address set up time
Address hold time
Serial input data set up time
Serial input data hold time
SYMBOL
tCYCE
tSCH
tSCL
tSCr, tSCf
PW CS
tCSU
tCH
tCSr, tCSf
tAS
tAH
tSISU
tSIH
MIN
1
300
700
–
500
200
200
–
200
200
200
200
MAX
–
–
–
20
–
–
–
20
–
–
–
–
UNIT
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CONDITION
Fig.1
Serial Interface timing
RS
VIH
VIL
tAS
CS
tCYCE
tCSU
tCH
VIH
VIL
tAH
VIH
VIL
PW CS
tSCH
tSCL
SCL
tSISU
tSIH
VIH
VIL
SI
Fig.1
•
External clock input
PARAMETER
External clock operation Frequency
External clock Duty
External clock rise Time
External clock fall Time
SYMBOL
fCP
Duty
tCPr
tCPf
MIN
110
45
–
–
MAX
180
55
0.2
0.2
UNIT
KHz
%
µs
µs
CONDITION
Fig.2
Tfcp
Duty=
OSC1
Tk
Tk+Ti
0.5VDD
Tfcp=1/fcp
Tk
Ti
Fig.2
Preliminary
•
NJU6637
The Input Condition when using the Hardware Reset Circuit
PARAMETER
RESET input
”Low” level width
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
tRSL
fOSC =145kHz
1.2
–
–
ms
TYP
–
–
MAX
5
–
Input timing
VRSL
RESET
VIL
•
Power supply condition when using the internal initialization circuit
PARAMETER
Power supply rise time
Power supply OFF time
SYMBOL
trDD
tOFF
CONDITION
–
–
3V
2.4V
0.2V
0.2V
VDD
trDD
0.1ms<trDD<10ms
MIN
0.1
1
UNIT
ms
ms
*tOFF specifies the power OFF
time in a short period OFF or
cyclical ON/OFF
tOFF
tOFF>1ms
Note.) Since the internal initialization circuits will not operate normally unless the above conditions are met, in
such a case initialize by instruction(Refer to initialization by the instruction).
Preliminary
NJU6637
■ LCD DRIVING WAVE FROM
NJU6637 1/24 Duty driving
1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
2
3
4
••••••
22 23 24 1
2
3
4
••••••
22 23 24
COM1
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
V4
V5
COM3
VDD
V1
V2
V3
V4
V5
SEG1
SEG5
SEG4
SEG3
SEG2
SEG1
SEG2
COM1-SEG1
COM1-SEG2
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
Preliminary
NJU6637
■ APPLICATION CIRCUITS
LCD Panel (16-character 3-line)
BOTTOM VIEW
16-character 3-line Display Example
(The terminal description is “Mode A”.)
COM1
COM24
SEG80
SEG1
COM16
COM9
NJU6637A
Preliminary
NJU6637
LCD Panel (16-character 3-line)
16-character 3-line Display Example
(The terminal description is “Mode B”.)
COM9
TOP VIEW
COM16
SEG80
SEG1
COM24
COM1
NJU6637A
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.