NJU6635 PRELIMINARY 16-CHARACTER 2-LINE DOT MATRIX LCD CONTROLLER DRIVER ■ GENERAL DESCRIPTION The NJU6635 is a 1Chip Dot Matrix LCD controller driver for up to 16-character 2-line display with double height function. It contains microprocessor Interface circuits, Instruction decoder controller, character generator ROM/RAM and common and segment drivers. The bleeder resistance generates for LCD Bias voltage Internally. The CR oscillator Incorporates C and R, therefore no external components for oscillation are required. The microprocessor Interface circuits which operate 2MHz frequency, can be connected directly to 4/8bit microprocessor. The character generator consists of 9,600 bits ROM and 32 x 5 bits RAM. The standard version ROM is coded with 240 characters including capital and small letter fonts. The 16-common and 80-segment drive up to 16-character 2-line LCD panel which divided two common electrode blocks. The rectangle outlook is very applicable to COG. ■ PACKAGE OUTLINE NJU6635CH ■ FEATURES ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 16-character 2-line Dot Matrix LCD Controller Driver 4/8 Bit Microprocessor direct Interface Display Data RAM :32 x 8 bits : Maximum 16-character 2line Display Character Generator ROM :9,600 bits ; 240 characters for 5 x 8 dots Character Generator RAM :32 x 5 bits ; 4 Patterns( 5 x 8 dots) Microprocessor direst accessing to Display Data RAM and Character Generator RAM High Voltage LCD Driver :16-common / 80-segment Duty Ratio :1/16 Duty Maximum Display Characters ; 32 Characters Useful Instruction Set Clear Display, Returns Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink, Cursor Shift, Character Shift, Double Height Function. Power On Reset / Hardware Reset Function Oscillation Circuit on chip Bleeder Resistance on chip Low Power Consumption Operating Voltage --- +5V Package Outline --- Bumped Chip C-MOS Technology 00/01/15 NJU6635 ■ PAD LOCATION 1 CHIP SIZE CHIP CENTER :5.49 x 1.37mm :X=0µm, Y=0µm BUMP SIZE :45 x 83µm BUMP HEIGHT :17.5µm Typ. BUMP MATERIAL :Au NJU6635 ■ PAD COORDINATES PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 PAD Name A mode DMY_1 OSC1 OSC2 VSS VSS VSS VDD VDD VDD V5 V5 V5 V3 V2 RESET RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DMY_2 DMY_3 DMY_4 DMY_5 DMY_6 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 DMY_7 DMY_8 DMY_9 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 B mode DMY_1 OSC1 OSC2 VSS VSS VSS VDD VDD VDD V5 V5 V5 V3 V2 RESET RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DMY_2 DMY_3 DMY_4 DMY_5 DMY_6 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 DMY_7 DMY_8 DMY_9 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 Chip Size(5490µm x 1370µm) X= um Y= um PAD No. -2435 -2282 -2061 -1916 -1856 -1796 -1661 -1601 -1541 -1407 -1347 -1287 -1138 -918 -689 -468 -239 336 561 820 1049 1308 1537 1797 2025 2285 2435 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 2435 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -534 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 PAD Name A mode SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 DMY_10 DMY_11 DMY_12 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 DMY_13 DMY_14 DMY_15 DMY_16 B mode SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DMY_10 DMY_11 DMY_12 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DMY_13 DMY_14 DMY_15 DMY_16 X= um Y= um 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2435 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 -2600 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 541 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 NJU6635 VSS Busy Flag Address counter 7 7 Display Data RAM (DD RAM) 32 x 8 bits 8 8 8 5 5 Character Generator (CG RAM) 32 x 5bits 5 Character Generator (CG RAM) 9,600bits 5 Parallel to serial Converter VDD R1 for LCD Driver V1 R1 V2 V2 R1 V3 V3 R1 V4 R1 VSS V5 Timing Generator Power On RESET 7 16 80 80 80-bit Shift resister Common Driver 4 DB4– DB7 DB0– 4 DB3 8 7 Segment Driver I/O Buffer E Data register (DR) 8 R/W Instruction Decoder (ID) 16-bit Shift register 8 RS 8 80-bit Latch CR OSC OSC2 Cursor Blink Controller OSC1 Instruction register(DR) ■ BLOCK DIAGRAM RESET 16 COM1– COM16 80 SEG – 1 SEG80 NJU6635 ■ TERMINAL DESCRIPTION PAD No. A mode B mode 4–9 4–9 10 – 14 10 – 14 2 2 SYMBOL I/O FUNCTION VDD, VSS V2, V3, V5 OSC1 – – I 3 3 OSC2 O 16 16 RS I 17 17 R/W I 18 26 – 23 18 26 – 23 E DB7 – DB4 I I/O 19 – 22 19 – 22 DB3 – DB0 I/O 32 – 39, 126 – 133 133 – 126, 39 – 32 O 43 – 122 122 – 43 COM1 – COM16 SEG1 – SEG80 Power Source : VDD = +5V, GND : VSS = 0V LCD driving Power Source Oscillation Frequency Adjustment Terminals. Normally Open. (Oscillation C and R are Incorporated, Osc Freq.=540kHZ) Oscillation Frequency Adjustment Terminals. Normally Open. This terminal also operates as the clock frequency monitor. Resister selection signal Input "0":Instruction Resister (Writing) Busy Flag (Reading) "1":Data Register (Writing / Reading) Read/Write selection signal Input "0":Write "1":Read Read/write activation Signal Input 3-state Data Bus(Upper) to transfer the data between MPU and NJU6635. DB7 is also used for the Busy Flag reading. 3-state Data Bus(Lower) to transfer the data between MPU and NJU6635. In serial and 4bit parallel mode, these terminals are not used and should be open. LCD Common driving signal Terminals O LCD segment driving signal Terminals 15 15 I Reset Terminal. When the “L” level Input over than 1.2ms to this terminal, the system will be reset.(fOSC=540kHz) Dummy Terminal These terminals are electrically open. RESET DUMMY1 1, 1, – 27 – 31, 27 – 31, DUMMY 15 40 – 42, 40 – 42, 123 – 125, 123 – 125, 134 – 137 134 – 137 O NJU6635 ■ FUNCTIONAL DESCRIPTION (1)Description for each blocks (1-1)Register The NJU6635 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register (IR) stores Instruction codes such as “Clear Display” and “Return Home”, and address data for Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the Instruction code and address data to the Register (IR), but it can not read out from the Register (IR). The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the DD RAM or CG RAM and read out from the DD RAM or CG RAM. The data in the Register (DR) written by the MPU is transferred from the Register automatically to the DD RAM or CG RAM by Internal operation. After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is transferred automatically to the Register (DR) for the next MPU reading. These two registers are selected by the selection signal RS as shown below: Table 1. Register operation control by RS and R/W signals. RS 0 0 1 1 R/W 0 1 0 1 Table 1. Register Operation Operation Write Read busy flag (DB7) and address counter (DB0 to DB7) Write (DR to DD or CG RAM) Read (DD or CG RAM to DR) (1-2)Busy Flag (BF) When the internal circuits are operating, the busy flag is “1”, and any instruction reading is inhibited. The busy flag (BF) is output from DB7 when RS=”0” and R/W=”1” as shown in table 1. The next instruction should be written after busy flag (BF) goes to “0”. (1-3)Address Counter(AC) The address Counter (AC) addresses the DD RAM and CG RAM. When the address setting instruction is written into the Register (IR), the address information is transferred from Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is also determined by this instruction. After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC) increments (or decrements) “1” automatically. The address data in the Counter (AC) is output from DB6 to DB0 when RS=”0” and R/W=”1” as shown in table 1. (1-4)Display Data RAM (DD RAM) The display data RAM (DD RAM) consisting of 32 x 8 bits stores up to 32-character display data represented in 8-bit code. The DD RAM address data set in the address Counter (AC) is represented in hexadecimal. AC ←Higher order bit AC6 AC5 AC4 Hexadecimal AC3 Lower order bit→ AC2 AC1 AC0 Hexadecimal (Example) DD RAM address “ 08 ” 0 0 0 1 0 0 0 0 8 NJU6635 (1-4-1)16-character 2-line Display The NJU6635 has two kinds of addressing mode as “ Addressing mode 1 ” and “ Addressing mode 2 ” which is determined by the Function Set Instruction (A=0 and 1). “Addressing mode 1” uses sequential address of (00)H through (1F)H for front half 16-character and last half 16-character. “Addressing mode 2 “ does not use sequential address like as (00)H through (1F)H and (40)H through (4F)H for front half 16-character and last half 16-character respectively. Addressing mode 1: A=0 1 2 3 4 5 1st line 00 01 02 03 04 2nd line 10 11 12 13 14 • 6 05 15 7 06 16 8 07 17 9 08 18 10 09 19 11 0A 1A 12 0B 1B 13 14 0C 0D 1C 1D 15 0E 1E 16 0F 1F ←Display Position ←DD RAM Address (Hexadecimal) The relation between DD RAM address and display position on the LCD shown below. [ Left Shift Display ] (00) ← 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 (10) ← 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 00 [ Right Sift Display ] 1F 00 01 02 03 0F 10 11 12 13 04 14 05 15 06 16 07 17 08 18 09 19 0A 1A 0B 1B Addressing mode 2: A=1 1 2 3 4 5 1st line 00 01 02 03 04 2nd line 40 41 42 43 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A 12 0B 4B 13 14 0C 0D 4C 4D 0C 1C 0D 0E 1D 1E → (0F) → (1F) 15 0E 4E ← Display Position ← DD RAM Address (Hexadecimal) • 16 0F 4F The relation between DD RAM address and display position on the LCD shown below. [ Left Shift Display ] (00) ← 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 (40) ← 41 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F [ Right Sift Display ] 0F 00 01 02 03 4F 40 41 42 43 04 44 05 45 06 46 07 47 08 48 09 49 0A 4A 0B 4B 0C 4C 0D 0E 4D 4E → (0F) → (4F) (1-4-2)The relation between DD RAM address and display position on the LCD shown below. (Double Height Sized display Function). Correspondence between DD RAM Address and display position on the LCD panel. In case of double height size Display function, the address of DD RAM which is set as follows the display, operates as 16-character 1-line and the addressing mode is ignored. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ← Display Position 1st line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ← DD RAM Address 2nd line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F (Hexadecimal) When the display shift is performed, the DD RAM address changes as follows. [ Left Shift Display ] (00) ← 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 (00) ← 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 [ Right Sift Display ] 0F 00 01 02 03 0F 00 01 02 03 04 04 05 05 06 06 07 07 08 08 09 09 0A 0A 0B 0B 0C 0C 0D 0E 0D 0E → (0F) → (0F) NJU6635 (1-5)Character Generator ROM(CG ROM) The Character Generator ROM (CG ROM) generates 5 x 8 dots character pattern represented in 8-bit character codes. The storage capacity is up to 240 kinds of 5 x 8 dots character pattern. The correspondence between character code and standard character pattern is shown in Table 2. User-defined character pattern ( Custom Font ) are also available by mask option. Table 2. CG ROM Character Pattern ( ROM version –02 ) Lower 4 bit (Hexadecimal) Upper 4 bit (Hexadecimal) NJU6635 (1-6)Character Generator RAM The character generator RAM (CG RAM) stores any kinds of character pattern in 5 x 8 dots written by the user program to display user’s original character pattern. The CG RAM stores 4 kinds of character in 5 x 8 dots mode. To display user’s original character pattern stored in the CG RAM, the address data (00)H – (03)H should be written to the DD RAM as shown in Table 2. Table 3. shows the correspondence among the character pattern, CG RAM address and data. Table 3. Correspondence of CG RAM address, DD RAM character code and CG RAM character pattern (5 x 8 dots) Character Character Code CG RAM Address Pattern (DD RAM Data) (CG RAM Data) 43210 76543210 43 210 ← → ← → ← → Upper Lower Upper bit Lower bit Upper bit Lower bit bit bit 000 11110 001 10001 010 Character 10001 011 00 Pattern 11110 0000∗∗00 100 Example (1) 10100 101 10010 110 10001 111 00000 ←Cursor Position 000 10001 001 01010 010 Character 11111 0 1 1 0 1 Pattern 0 0 1 0 0 0000∗∗01 100 Example (2) 11111 101 00100 110 00100 111 00000 ← Cursor Position 000 001 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 11 0000∗∗11 100 101 110 111 Notes: 1. Character code bits 0 and 1 correspond to the CG RAM address 3 and 4 ( 2bits : 4 patterns). 2. CG RAM address 0, 1 and 2 designate a character pattern line position. The 8th line is the cursor position and the display is performed by logical OR with cursor. Therefore, in case of the cursor display, the data of 8th line should be “0”. If there is “1” in the 8th line, the bit “1” is always displayed on the cursor position regardless of cursor existence. 3. Character pattern row position corresponding to the CG RAM data bits 0 to 4 are all shown above. The bits 5 to 7 of the CG RAM do not exist. 4. CG RAM character patterns are selected when character code bits 4 to 7 are all “0” and addressed by character code bits 0 and 1. Therefore the address (00)H, (04)H, (08)H and (0C)H, select the same character pattern as shown In table 2 and Table 3. 5. ”1” for CG RAM data corresponds to display On and “0” to display Off. NJU6635 (1-7)Timing Generator The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal circuit operation. RAM read timing for the display and internal operation timing for MPU access are separately generated, so that they may not interfere with each other. Therefore, when the data write to the DD RAM for example, there will be undesirable Influence, such as flickering, in areas other than the display area. (1-8)LCD Driver LCD driver consists of 16-common driver and 80-segment driver. The 80 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift performed completely. This latched data controls display driver to output LCD driving waveform. (1-9)Cursor Blinking Control Circuit This circuits controls cursor On/Off and cursor position character blinks. The cursor or blinks appears in the digit position at the DD RAM address set in the address counter(AC). When the address counter is (08)H, a cursor position is shown as follows: AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC 0 0 0 1 0 0 0 1st line 2nd line 1 00 10 2 01 11 3 02 12 4 03 13 5 04 14 6 05 15 7 06 16 8 07 17 9 08 18 10 09 19 11 0A 1A 12 0B 1B 13 14 0C 0D 1C 1D 15 0E 1E 16 0F 1F ← Display Position ← DD RAM Address (Hexadecimal) Cursor Position Note) The cursor or blinks appears when the address counter (AC) selects the CG RAM. But the displayed cursor and blink are meaningless. If the AC stores the CG RAM address data, the cursor and blink are displayed in the meaningless position. NJU6635 (2)Power on Initialization by internal circuits (2-1) Initialization By internal Reset circuits The NJU6635 is initialized automatically by the internal power on initialization circuits when the power is turned on. In the internal power on initialization, following instructions are executed. During the internal power on initialization, the busy flag (BF) is “1” and this status is kept 10ms after VDD = 4.5V. Initialization flow is shown below: Clear Display DL=1 A=0 M0=0 M1=0 E=0 :8-bit long interface data :Addressing mode 1 :A mode :32-character 1-line :Normal Display mode Display On/Off Control D=0 C=0 B=0 :Display Off :Cursor Off :Cursor Blink Off Entry Mode Set I/D=1 S=0 :Increment by 1 :No Shift Function Set Note) If the condition of power supply rise time described in the Electrical Characteristics is not satisfied, the internal Power on initialization Circuits will not operate and initialization will not be performed. In this case, the initialization by MPU software is required. (2-2) Initialization By Hardware The NJU6635 incorporates RESET terminal to initialize the all system. When the “L” level input over than 1.2ms to the RESET terminal, the reset sequence is executed. In this time, the busy signal output during 10ms after RESET terminal goes to “H”. • RESET operation System clock C Q C Q Counter RESET RST RST RS-F/F Power No RESET • Operation timing Over 1.2ms External Reset Signal Counter Output RS-F/F Output Internal Reset Signal BUSY 10ms System RESET NJU6635 (3) Instructions The NJU6635 incorporates two resisters, which are Instruction Register (IR) and a Data Register (DR). These two registers store control information temporarily to allow interface between NJU6635 and MPU or peripheral ICs operating different cycles. The operation of NJU6635 is determined by this control signal from MPU. The control information includes register selection signals (RS), read/write signals (R/W) and data bus signals (DB0 to DB7). Table 5. Shows each instruction and its operating time. Note) The execution time mentioned in Table 5. is based on fcp or fOSC=540kHz. If the oscillation frequency is changed, the execution time is also changed. Table 5. Table of Instruction INSTRUCTION CODE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Maker Test 0 0 0 0 0 0 0 0 0 0 Clear Display 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 E 0 0 0 0 0 0 0 1 I/D S 0 0 0 0 0 0 1 D C B 0 0 0 0 0 1 S/C R/L ∗ ∗ 0 0 0 0 1 Set CG RAM Address 0 0 0 1 ∗ Set DD RAM Address 0 0 1 Read Busy Flag & Address 0 1 BF Return Home / Font Size Set Entry Mode Set Display Control ON/OFF Cursor or Display Shift Function Set Write Data to CG or DD or MK RAM 1 Read Data from CG or DD or MK RAM 1 Explanation of Abbreviation ∗=Don’t Care 0 1 DL A ∗ M1 M0 CG RAM address DD RAM address AC ∗ ∗ AC Write Data(DD RAM) ∗ ∗ ∗ ∗ ∗ All “0” code is using for maker testing. Display clear and sets DD RAM address 0 in AC. Sets DD RAM address 0 In AC and returns display being shifted to original position. DD RAM contents remain unchanged. Sets cursor move direction and species shift of display are performed In data read/write. I/D=1:Increment, I/D=D:Decrement,S=1:Accopa nies display shift. Sets of display On/Off(D), cursor On/Off(C) and blink of cursor position character(B) Move cursor and shifts display without changing DD RAM contents. S/C=1 : Display shift S/C=0 : Cursor shift R/L=1 : Shift to right R/L=0 : Shift to the left Sets interface data length(DL), Display address mode(A) DL=1 : 8 bits, DL=0 : 4 bits A=0 : Addressing mode 1 A=1 : Addressing mode 2 M1=0 : 32-Character 1-Line M1=1 : 16-Character 2-Line M0=0 : Pin configuration mode A M0=1 : Pin configuration mode B Sets CG RAM address. After this instruction, the data is transferred on CG RAM. Sets DD RAM address. After this instruction, the data is transferred on DD RAM. Read busy flag and AC contents. BF=1 : Internally operating BF=0 : Can accept instruction Writes data into CG or DD RAM. EXEC TIME (fOSC=540kHz)* – 315.9µs 18.5µs 18.6µs 18.6µs 28µs 18.6µs 18.6µs 18.5µs 0µs 18.6µs (CG RAM) Read Data(DD RAM) ∗ DESCRIPTION Reads data from CG or DD RAM (CG RAM) DD RAM : Display data RAM, CG RAM : Character generator RAM ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address AC : Address counter used for both DD and CG RAM 28µs NJU6635 (3-1) Description of instruction a) Maker Test RS R/W DB7 Code 0 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 All “0” code in 4-bit length is using device testing mode ( only for maker ). Therefore, please avoid all “0” input or no meaning Enable signal input at data “0” ( Especially please pay attention to the output condition of Enable signal when the power turns on ). All “0” code in 8-bit length is usable for NOP ( Not Operating instruction ). b) Clear Display RS Code 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 Clear display instruction is executed when the code “1” is written into DB0. In case of normal display mode, when this instruction is executed, the space code (20)H is written into every DD RAM address, the DD RAM address 0 is set into the address counter and entry mode is set an increment. If the cursor or blink are displayed, they are returned to the left end of the LCD. The S of entry mode and CG RAM data does not change. In case of double height mode, when this instruction is executed, the space code (20)H is written into DD RAM address,(00)H to (0F)H. Note: The character pattern for character code (20)H must be blank code in the user-defined character pattern( Custom font ). c) Return Home / Font Size Set RS R/W DB7 DB6 Code 0 0 0 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 E Return home instruction is executed when the code “1” is written Into DB1. When this Instruction is executed, the DD RAM address 0 is set to address counter. Display is returned to the original position if shifted, the cursor or blink is returned to the left end of the LCD. If the cursor or blink are on the display, the DD RAM contents are not changed. The normal display mode is executed when the code “0” is written Into DB0. The double height mode function is set by writing “1” Into DB0. The character of DD RAM address, (00)H to (0F)H, are expanded to double height size ( 5 x 16 dots ) and “Return Home” function is operated. In this time, access from (10)H to (1F)H or (40)H to (4F)H of DD RAM address is not available but the data in RAM are kept. Therefore, when the display mode returns from double height to normal, the kept data in RAM displays again. In case of no display, “clear display” should be operated before transition from normal mode to double height. The cursor size is also expanded to 5 x 2 dots. Double height sized display function and Normal are not operated in the mean time. The font in double height mode is some as normal. E 0 1 FUNCTION Normal Display mode (Font Size : 5 x 8dots) Double height sized Display mode (Font Size : 5 x 16 dots) in case of DD RAM address : (00)H to (0F)H. NJU6635 d) Entry Mode Set RS R/W Code 0 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S Entry mode set instruction which sets cursor moving direction and display shift On/Off, is executed when the code “1” is written into DB2 and the codes of (I/D) and (S) are written into DB1 (I/D) and DB0 (S) as shown below. (I/D) sets the address increment or decrement, and the (S) sets the entire display shift in the DD RAM writing. I/D 0 1 S 1 0 FUNCTION Address increment : The address of the DD RAM increment ( +1) when the read/write, and the cursor or blink moves to the right. Address decrement : The address of the DD or CG RAM decrement ( -1) when the read/write, and the cursor or blink move to the left. FUNCTION Entire display shift. The shift direction is determined by I/D: shift to the left at I/D=1 and shift to the right at the I/D=0. The shift is operated with only the character, so that it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DD RAM and writing/reading into/from CG RAM. The display does not shifting e) Display ON/OFF Control RS R/W DB7 Code 0 0 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B Display On/Off control instruction which controls the display On/Off, the cursor On/Off and the cursor position character blink, is executed when the code “1” is written into DB3 and the codes of (D), (C) and (B) are written into DB2(D), DB1(C) and DB0(B) as shown below. D 1 0 FUNCTION Display On. Display Off. In this mode, the display data remains in the DD RAM so that it is retrieved immediately on the display when the D change to 1. C 1 0 FUNCTION Cursor On. The cursor is displayed by 5 dots on the 8th line. Cursor Off. Even if the display data write, the I/D etc does not change. B 1 FUNCTION The cursor position character is blinking. Blinking rate is 303.4ms at fOSC=540kHz. The blink is displayed alternatively with all on (it means all black) and characters display. The cursor and the blink can be displayed simultaneously. The character does not blink. 0 NJU6635 • Normal display mode !"""! "!!!" "!!!" "!!!" """"" "!!!" "!!!" """"" !"""! "!!!" "!!!" "!!!" """"" "!!!" "!!!" !!!!! Character Font 5 x 7dots (1) Cursor display example • """"" """"" """"" """"" """"" """"" """"" """"" Alternating display (2) Blink display example Double height sized display mode !"""! !"""! "!!!" "!!!" "!!!" "!!!" "!!!" "!!!" """"" "!!!" "!!!" "!!!" "!!!" """"" """"" Alternating display (2) Blink display example Character Font 5 x 14dots (3) Cursor display example f) Cursor Display Shift RS R/W Code 0 0 """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" """"" !"""! !"""! "!!!" "!!!" "!!!" "!!!" "!!!" "!!!" """"" "!!!" "!!!" "!!!" "!!!" !!!!! !!!!! DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 ∗ DB0 ∗ ∗=Don’t Care The Cursor/Display shift instruction shifts the cursor position or display the right or left without writing reading display data. The contents of address counter (AC) is not changed by operation of display shift only. This instruction is executed when the code “1” is written into DB4 and the codes of (S/C) and (R/L) are written into DB3 (S/C) and DB2(R/L) as shown below. S/C 0 0 1 1 R/L 0 1 0 1 FUNCTION Shifts the cursor position to the left ((AC) is decrement by 1) Shifts the cursor position to the right ((AC) is incremented by 1) Shifts the entire display to the left and the cursor follows it. Shifts the entire display to the right and the cursor follows it. NJU6635 g) Function Set RS Code 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 A DB2 ∗ DB1 M1 DB0 M0 ∗=Don’t Care Function set instruction which sets the interface data length, the addressing mode for the DD RAM, 1-line or 2-line display, and Pin configuration mode, is executed when the code ”1” is written into DB5 and the codes of (DL), (A), (M1) and (M0) are written into DB4 (DL), DB3 (A), DB1 (M1), and DB0 (M0) as shown below (character font is fixed 5 x 8 dots). Note) This function set instruction must be performed at the head of the program prior to all other instructions (except Busy flag/Address read). This function set instruction can not be executed afterwards unless the interface data length change. DL 1 0 A 0 1 FUNCTION Set the interface data length to 8 bits (DB7 to DB0) Set the interface data length to 4 bits (DB7 to DB4) A couple of data must be sent or received. FUNCTION Set the Addressing Mode 1 for the DD RAM Set the Addressing Mode 2 for the DD RAM M1 0 1 Set the 32-Character 1-Line Display Set the 16-Character 2-Line Display FUNCTION M0 0 1 FUNCTION Set the Pin configuration mode A for Common and Segment Driver (Refer to cord.) Set the Pin configuration mode B for Common and Segment Driver (Refer to cord.) h) Set CG RAM Address RS R/W DB7 DB6 DB5 DB4 Code 0 0 0 1 A ∗ ← Higher order bit → DB3 DB2 DB1 DB0 A A A A ← Lower order bit → Set CG RAM address instruction is executed when the code “1” is written into DB6 and the address is written into DB4 to DB0 as shown above. The address data mentioned by binary code “AAAAA “ is written into the address counter (AC) together with the CG RAM addressing condition. After this instruction, the data writing/reading is performed into/from the CG RAM. CG RAM : CG RAM address (00)H – (1F)H NJU6635 i) Set DD RAM Address RS R/W DB7 DB6 DB5 DB4 Code 0 0 1 A A A ← Higher order bit → DB3 DB2 DB1 DB0 A A A A ← Lower order bit → Set DD RAM address instruction is executed when the code “1” is written into DB7 and the address is written into DB6 to DB0 as shown above. The address data mentioned by binary code “AAAAAAA “ is written into the address counter (AC) together with the DD RAM addressing condition. After this instruction, the data writing/reading is performed into/from the DD RAM. The DD RAM address is indicated as follows, which is available for DD RAM address only. Normal mode condition DD RAM 1-Line DD RAM 2-Line (Addressing mode 1) DD RAM 2-Line (Addressing mode 2) : : : DD RAM address (00)H – (0F)H (10)H – (1F)H (40)H – (4F)H : DD RAM address (00)H – (0F)H Double height size display condition DD RAM 1-Line j) Read Busy Flag & Address RS R/W DB7 DB6 DB5 DB4 Code 0 1 BF A A A ← Higher order bit → DB3 DB2 DB1 DB0 A A A A ← Lower order bit → This instruction reads out the internal status of the NJU6635. When this instruction is executed, the busy flag (BF) which indicates the internal operation, is read out from DB7 and the address of CG RAM or DD RAM is read out from DB6 to DB0 (an address for CG RAM or DD RAM is determined by the previous instruction). (BF)=1 indicates that internal operation is in progress. The next instruction is inhibited when (BF)=1. Check the (BF) status before the next write operation. • • k) Write Data to CG or DD RAM Write data to CG RAM RS R/W DB7 DB6 DB5 DB4 Code 1 0 D ∗ ∗ ∗ ← Higher order bit → Write data to DD RAM RS R/W Code 1 0 DB7 DB6 DB5 DB4 D D D D ← Higher order bit → DB3 DB2 DB1 DB0 D D D D ← Lower order bit → DB3 DB2 DB1 DB0 D D D D ← Lower order bit → ∗=Don’t Care Write Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS) and code “0” is written into (R/W). By the execution of this instruction, the binary 5-bit data “DDDDD” are written into the CG RAM, and the binary 8-bit data “DDDDDDDD” are written into the DD RAM. The selection of the CG RAM or DD RAM is determined by the previous instruction. After this instruction execution, the address increment(+1) or decrement(-1) is performed automatically according to the entry mode set. And the display shift is also executed according to the previous entry mode set. NJU6635 • • l) Read Data from CG or DD RAM Read data to DD RAM RS R/W DB7 DB6 DB5 DB4 Code 1 1 D D D D ← Higher order bit → Read data to CG RAM RS R/W Code 1 0 DB7 DB6 DB5 DB4 D ∗ ∗ ∗ ← Higher order bit → DB3 DB2 DB1 DB0 D D D D ← Lower order bit → DB3 DB2 DB1 DB0 D D D D ← Lower order bit → ∗=Don’t Care Read Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS) and (R/W). By the execution of this instruction, the binary 5-bit data “DDDDD” are read out from CG RAM, and the binary 8-bit data “DDDDDDDD” are read out from DD RAM. The selection of the CG RAM or DD RAM is determined by the previous instruction. Before executing this instruction, either the CG RAM address set or DD RAM address set must be executed, otherwise the first read out data Invalidated. When this instruction is serially executed, the next address data is normally read from the second read. The address set instruction is not required if the cursor shift instruction is executed just beforehand (only DD RAM reading). The cursor shift instruction has same function as the DD RAM address set, so that after reading the DD RAM, the address increment or decrement is executed automatically according to the entry mode. But display shift does not occur regardless of the entry mode. Note) The address counter (AC) is automatically incremented by 1 after write instructions to either of the CG RAM or DD RAM. Even if the read instruction is executed after this instruction, the addressed data can not be read out correctly. For a correct data read out, either the address set instruction or cursor shift instruction (only with DD RAM) must be implemented just before this instruction or from the second time read out instruction execution if the read out instruction is executed 2 times consecutively. NJU6635 (3-2)Initialization using the internal reset circuits a) 32-character 1-line in 8-bit operation Addressing Mode 1 (Using internal reset circuits). At the 32-character 1-line display, the Function set, On/Off Control and Entry Set Instruction must be executed before the data input, as shown below. Since the display shift operation changes only display position and the DD RAM contents are unchanged, display data which are entered first can be output when the return home operation is performed. Initialized. No display appears. Power On Function Set Display On/Off Control Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 0 ∗ RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 1 0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 1 0 Set the 8-bit operation, 32-Character 1-Line display, Pin configuration mode A, Addressing Mode 1. Turns on display and cursor. Entire display is in space mode by the initialization. Example for set address increment and cursor right shift when the data write to the DD or CG RAM. Write data to the CG or DD RAM and set the instruction. b) 32-character 1-line in 4-bit operation Addressing Mode 1 (Using internal reset circuits). In the 4-bit operation, the function set must be performed by the user programming. When the power is turned on, 8-bit operation is selected automatically, therefore the first input is performed under 8-bit operation. In this operation, full instruction can not input because of terminals DB0 to DB3 are no connection. Therefore, same instruction must be rewritten on the RS, R/W and DB7 to DB4, as shown below. Since one operation is completed by the two accesses in the 4-bit operation mode, rewrite is required to set the instruction code in full. 32-character 1-line in 4bit operation is shown as follows: Initialized. No display appears. Power On Function Set Function Set Display On/Off Control Entry Mode Set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0 0 0 0 ∗ RS R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 1 1 1 0 RS R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 0 1 1 0 Write data to the CG or DD RAM and set the instruction. Set the 4-bit operation. This step is executed in 8-bit mode set by initialization. Set the 4-bit operation /32-Character 1-Line display, Pin configuration mode A, Addressing Mode 1. The 4-bit operation starts from this step. Turns on display and cursor. Entire display is in space mode by the initialization. Example for set address increment and cursor right shift when the data write to the DD or CG RAM. NJU6635 (3-3)Initialization by instruction If the power supply conditions for the correct operation of the internal reset circuits are not method, the NJU6635 must be initialized by the instruction. a) Initialization by Instruction in 8-bit interface Initialized. No display appears. Power On Wait more than 15 ms after VDD rises to 4.5V RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set 0 0 0 1 1 ∗ ∗ ∗ ∗ (8-bit interface length) RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set 0 0 0 1 1 ∗ ∗ ∗ ∗ (8-bit interface length) Function Set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set 0 0 0 1 1 ∗ ∗ ∗ ∗ (8-bit interface length) Busy Flag(BF) can not be checked before this step, but it can be checked after this step. After this step, busy flag(BF) check or longer waiting time than each instruction execution time is required. Function Set RS 0 Display Off RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set the 8-bit operation, 0 0 0 1 1 0 0 0 ∗ /Addressing Mode 1. R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0 0 Display Clear RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 Function Set Wait more than 4.1ms Function Set Wait more than 100µs R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Example for set address 0 0 0 0 0 0 1 1 0 increment and cursor right shift when the data write to the DD RAM. Write data to the CG or DD RAM and set the instruction. Entry Mode Set RS 0 NJU6635 b) Initialization by Instruction in 4-bit interface Initialized. No display appears. Power On Wait more than 15ms after VDD rises to 4.5V Function set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set (8-bit interface length) Wait more than 4.1ms Function set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set (8-bit interface length) Wait more than 100µs Function set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 Function set RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0 0 1 0 ∗ Display Off RS R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 1 0 0 0 Display Clear RS R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 0 0 0 1 Entry Mode Set RS 0 0 R/W DB7 DB6 DB5 0 0 0 0 0 0 1 1 Write data to the CG or DD RAM and set the instruction. DB4 0 0 Function Set (8-bit inter face length) Busy Flag(BF) can be not be checked before this step, but it can be checked after this step. After this step, busy flag (BF) check or longer waiting time than each instruction execution time is required. Set the 4bit operation / Addressing mode 1 Example for set address increment and cursor right shift when the data write to the DD or CG RAM. NJU6635 (4) LCD DISPLAY NJU6635 incorporates bleeder resistance to generate the LCD display driving waveform. The bleeder resistance is set 1/5 bias suitable for 1/18 duty ratio and 1.5kΩ per resistance. The decoupling capacitor should be connected between VDD and V5 terminal. The value of capacitor is determined depending on the actual LCD panel display evaluation. Power Supply LCD Driving Voltage vs. Duty Ratio Duty Ratio 1/16 Bias 1/5 V2 VDD-2/5VLCD V3 VDD-3/5VLCD V5 VDD-VLCD ∗ The VLCD is maximum swing of LCD waveform. NJU6635 VDD 1.5kΩ V1 1.5kΩ V2 1.5kΩ 1.5kΩ 1.5kΩ V3 VLCD V4 V5 V5 LCD Driving Voltage example Note) Power ON or power OFF is in the following order. Power ON : V5 should be turned on after the VDD turned on or at the same time. Power OFF : V5 should be turned off before the VDD turned off or at the same time. NJU6635 (4-1) Relation between oscillation frequency and LCD frame frequency. LCD frame frequency example mentioned below is based on 540kHz oscillation. The clock for the LCD driving is using 270/2 kHz (1 clock = 1.852µs) • 1/16 duty 80 clock 1 2 3 4 •••••• 16 1 2 3 4 •••••• 16 1 2 3 VLCD V1 V2 V4 VSS 1 frame 1 frame 1 frame = 7.4 (µs) x 80 x 16 x 4 = 9.472(ms) Frame frequency = 1/9.472(ms) = 105.6(Hz) (5)Interface with MPU NJU6635 can be interfaced with both of 4/8 bit MPU and the two-time 4-bit or one-time 8-bit data transfer is available. (5-1)8-bit MPU interface RS R/W E Internal Status DB7 Operation Data Instruction Writing Busy Busy Flag Check Busy Busy Flag Check No Busy Busy Flag Check Data Instruction Writing NJU6635 (5-2)4-bit MPU interface When the interface length is 4-bit, the data transfer is performed by 4 lines connected to DB4 to DB7 (DB0 to DB3 are not used). The data transfer with the MPU is completed by the two-time 4-bit data transfer. The data transfer is executed in the sequence of upper 4-bit (the data DB4 to DB7 at 8-bit length) and lower 4-bit (the data DB0 to DB3 at 8-bit length). The busy flag check must be executed after two-time 4-bit data transfer (1 instruction execution). In this case the data of busy flag and address counter are also output twice. RS R/W E Internal Status DB7 Operation IR IR Instruction Writing Busy No Busy AC Busy Flag Check AC D7 Busy Flag Check D3 Instruction Writing RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 BF AC2 DR6 DR2 DB5 IR5 IR1 BF AC1 DR5 DR1 DB4 IR4 IR0 BF AC0 DR4 DR0 Writing Instruction into Instruction Register (IR) Readout Busy Flag(BF) and Address counter(AC) Reading data Register (DR) NJU6635 ■ ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Operating Temperature Storage Temperature (Ta=25°C) SYMBOL VDD VIN Topr Tstg RATINGS -0.3 to +7.0 -0.3 to VDD+0.3 -30 to +80 -55 to +125 UNIT V V °C °C Note 1.) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2.) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the LSI. Note 3.) All voltage values are specified as VSS =0V Note 4.) The relation VDD>V5≥VSS, VSS=0V must be maintained. ■ ELECTRICAL CHARACTERISTICS PARAMETER Operating Volt. Input Voltage 1 Input Voltage 2 Input Voltage 3 Output Voltage Driver On-resist. (COM) Driver On-resist.(SEG) Input Leakage Current Pull-up Resist Current Operating Current LCD Driving Voltage Bleeder Resistance Oscillation Frequency LCD Driving Voltage (VDD=4.5 to 5.5V, VSS=0V, Ta=-20 to 75°C) SYMBOL SYMBOL MIN VDD VDD 4.5 VIH1 2.3 All Input / Output Terminals except OSC and E Terminals VIL1 – VIH2 VDD-1.0 Only OSC Terminals VIL2 – VIH3 0.8 VDD Only E Terminal VIL3 – IOH IOL -IOH=0.205mA IOL=1.6mA TYP 5.0 – – – – – 2.4 – – – MAX 5.5 VDD 0.8 VDD 1.0 VDD 0.2 VDD – 0.4 – UNIT V V V V V V V V V RCOM ±Id=50µA (All com. Term.) – – 20 kΩ RSEG ±Id=50µA (All SEG. Term.) – – 30 kΩ ILI VIN=0 to VDD -1 – 1 µA -IP VDD=5V 50 125 250 µA IDD VDD=5V fOSC=540kHz(CR Oscillation) – 2.0 3.6 mA V2 V3 VDD=5V, Ta=25°C, V5=0V 2.7 1.7 3.0 2.0 3.3 2.3 V V RB VDD-V5=5V, Ta=25°C 3.7 7.5 11.3 kΩ fOSC VDD=5V, Ta=25°C 270 540 810 kHz VLCD VLCD= VDD-V5, V5≥VSS 3 – VDD V NOTE 5 5 5 6 9 7 8 10 NJU6635 Note 5) Input / Output structure except LCD driver are shown below: • Input Terminal Structure E Terminal RS, R/W, RESET Terminals VDD VDD VDD PMOS PMOS VSS (Pull-up MOS) NMO NMOS VSS VSS • Input / Output Terminal Structure DB0 to DB7 Terminals VDD VDD PMOS PMOS VDD NMO VSS PMOS ENABLE DATA NMOS VSS Note 6.) Apply to the Input / Output Terminals. Note 7.) Except pull-up resistance current and output driver current. Note 8.) Except Input / Output current but including the current flow on bleeder resistance. Note 9.) RCOM and RSEG are the resistance values between power supply terminals(VDD, V2, V3, V5) and each common terminal (COM1 to COM16), and supply voltage (VDD, V2, V3, V5) and each segment terminal(SEG1 to SEG80) respectively, and measured when the current Id is flown on every common and segment terminals at the same time. Note10.) Apply to the output voltage from each COM and SEG are less than ±0.15V against the LCD driving constant voltage (VDD,V5) at no load condition. • Bleeder resistance VDD NJU6635 1.5kΩ V1 1.5kΩ V2 1.5kΩ V3 1.5kΩ V4 1.5kΩ V5 V3 V2 V5 NJU6635 ■ Bus timing characteristics (VDD=4.5 to 5.5V, VSS=0V, Ta=-20 to 75°C) Write operation sequence (write from MPU to NJU6635) PARAMETER SYMBOL MIN Enable Cycle Time tCYCE 500 Enable Pulse “High” level PW EH 220 Width Low” level PW EL 280 Enable Rise Time, Fall Time tEr, tEf – Set up Time RS, R/W-E tAS 40 Address Hold Time tAH 10 Data Set up Time tDSW 60 Data Hold Time tH 10 • RS VIH VIL R/W VIL MAX – – – 20 – – – – ns Fig.1 VIL tAH PW EH tEf VIL CONDITION VIH VIL tAH tAS E UNIT VIH VIH tDSW tEr PW EL VIL VIL tH VIH VIH DB0 – DB7 Data VIL VIL tCYCE Fig.1 The timing characteristics of the bus write operating sequence.(Write from MPU to NJU6635) Read operation sequence ( Read from NJU6635 to MPU) PARAMETER SYMBOL MIN Enable Cycle Time tCYCE 500 Enable Pulse “High” level PW EH 220 Time Low” level PW EL 280 Enable Rise Time, Fall Time tEr, tEf – Set up Time RS, R/W-E tAS 40 Address Hold Time tAH 10 Data Delay Time tDDR – Data Hold Time tDHR 20 • VIH VIL RS tEf tEr ns Fig.2 tAH PW EH VIL CONDITION VIH VIH E UNIT VIH VIL tAH tAS R/W MAX – – – 20 – – 240 – VIH VIH PW EL VIL VIL tDHR tDDR VOH VOH DB0 – DB7 Data VOL VOL tCYCE Fig.2 The timing characteristics of the bus write operating sequence.(Write from NJU6635 to MPU) NJU6635 The Input Condition when using the Hardware Reset Circuit PARAMETER SYMBOL CONDITION RESET input tRSL fOSC =540kHz ”Low” level width • MIN TYP MAX UNIT 1.2 – – ms Input timing VRSL RESET VIL Power supply condition when using the internal initialization circuit PARAMETER SYMBOL CONDITION MIN Power supply rise time trDD – 0.1 Power supply OFF time tOFF – 1 • 0.2V trDD 0.1ms ≤ trDD ≤ 10ms (Ta=-20 to 75°C) MAX UNIT 5 ms – ms 3V 4.5V VD TYP – – 0.2V tOFF *tOFF specifies the power OFF time in a short period OFF or cyclical ON/OFF tOFF ≤ 1ms Note.) Since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case initialize by instruction(Refer to initialization by the instruction). NJU6635 ■ LCD DRIVING WAVE FROM NJU6635 1/16 Duty driving COM1 VDD COM2 V1 COM3 V2 COM4 COM1 V3 COM5 V4 COM6 V5 COM7 VDD COM8 V1 V2 COM9 COM2 V3 COM10 V4 COM11 V5 COM12 COM13 COM14 COM15 VDD COM16 V1 V2 COM16 V3 V4 V5 VDD V1 V2 SEG1 V3 V4 V5 VDD V1 V2 SEG2 V3 V4 V5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NJU6635 ■ APPLICATION CIRCUITS M0=0, M1=0 (32-character 1-line Mode A) M0=0, M1=1 (16-character 2-line Mode A) NJU6635 M0=1, M1=0 (32-character 1-line Mode B) M0=1, M1=1 (16-character 2-line Mode B) NJU6635 M0=0, M1=1 (16-character 1-line Mode A) M0=1, M1=1 (16-character 1-line Mode B) NJU6635 MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.