NJU6627

NJU6627
Preliminary
10-CHARACTER 3-LINE DOT MATRIX LCD
CONTROLLER DRIVER with KEYSCAN FUNCTION
 GENERAL DESCRIPTION
The NJU6627 is a Dot Matrix LCD controller driver for
10-character 3-line with icon display in single chip.
It contains voltage converter and regulator bleeder
resistance, Keyscan circuit, CR oscillator, microprocessor
interface circuit, instruction decoder controller, character
generator ROM/RAM, high voltage operation common and
segment drivers, and others.
The character generator ROM consisting of 7,840bits stores
224 kinds of character font, Each 1,120 bits CG RAM and
Icon display RAM can store 32 kind of special character
displayed on the dot matrix display area or 100 kinds of Icon
display area.
The 23-common(21 for character, 2 for Icon) and
50-segment drivers operate 10-character 3-line with 100
Icon LCD display.
th
The 16 display contrast control function is incorporated.
Therefore, only simple power supply circuit on chip operates
the contrast adjustment easily.
The complete CR oscillator requires external capacitor and
resistor.
The serial interface which operates by 1MHz, communicates
with external MCU.
 PACKAGE OUTLINE
NJU6627C
 FEATURES

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
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


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
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10-character 3-line Dot Matrix LCD Controller Driver
Maximum 100 Icon Display
Serial Direct Interface with Microprocessor
Display Data RAM
30 x 8 bits
:Maximum 10-character 3-line Display
Character Generator ROM
7,840bits
:224 Characters for 5 x 7 Dots
Character Generator RAM
1,120bits
:32 Patterns (5 x 7 Dots)
Icon Display RAM
Maximum 100-Icons
High voltage LCD Driver
23-common / 50-segment
Duty and Bias Ratio
1/23, 1/16 duty, 1/5 bias
Useful Instruction set Clear Display, Address Home, Display ON/OFF, Display blink,
Address shift, Character Shift, Keyscan ON/OFF cont. e.t.c.
24-Key input(4x6 Keyscan)
Power on Initialization / Hardware Reset
Bleeder resistance on chip
Software contrast control(16-step)
Voltage Booster Circuits (2-time)
Oscillation Circuit on-chip (External CR)
Operating Voltage
4.5 to 5.5V
Package Outline
Bare Chip
C-MOS Technology
Ver.2013-12-25
-1-
NJU6627
Preliminary
 PAD LOCATION
75
51
76
50
TOP VIEW
Y
X
100
26
1
Chip Center
Chip Size
Chip Thickness
PAD Size
PAD Pitch
Sub Striate
-2-
25
: X=0m, Y=0m
: X= 4.50 mm, Y= 4.61 mm
: 400m  25 m
: 90.0 m x 90.0 m
: 134m (Min.)
:P
Ver.2013-12-25
NJU6627
Preliminary
 PAD COODINATES
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ver.2013-12-25
PAD NAME
V4
V3
V2
V1
VLCD
VOUT
C1+
C1VCI
VDD
OSC1
REQ
DATA
SCL
CSb
RESETb
VSS
K1
K2
K3
K4
K5
K6
S1
S2
S3
S4
COMMK1
COM8
COM9
COM10
COM11
COM12
COM13
COM14
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
X= m
-2007.3
-1862.5
-1717.7
-1572.9
-1428.1
-1158.4
-1018.4
-878.4
-738.4
-497.6
-345.8
-204.0
-17.2
142.6
286.6
430.6
596.8
817.4
951.4
1098.6
1232.6
1379.8
1513.8
1743.2
1923.2
1978.6
1978.6
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
2088.0
Chip Size 4.50 x 4.61 mm(Chip Center X=0m, Y=0m)
PAD No. PAD NAME
Y= m
X= m
Y= m
-2038.5
51
SEG16
1930.0
2143.0
-2038.5
52
SEG17
1785.0
2143.0
-2038.5
53
SEG18
1640.0
2143.0
-2038.5
54
SEG19
1495.0
2143.0
-2038.5
55
SEG20
1350.0
2143.0
-2038.5
56
SEG21
1205.0
2143.0
-2038.5
57
SEG22
1060.0
2143.0
-2038.5
58
SEG23
915.0
2143.0
-2038.5
59
SEG24
770.0
2143.0
-2038.5
60
SEG25
625.0
2143.0
-2038.5
61
SEG26
480.0
2143.0
-2038.5
62
SEG27
335.0
2143.0
-2038.5
63
SEG28
190.0
2143.0
-2038.5
64
SEG29
-335.0
2143.0
-2038.5
65
SEG30
-480.0
2143.0
-2038.5
66
SEG31
-625.0
2143.0
-2038.5
67
SEG32
-770.0
2143.0
-2038.5
68
SEG33
-915.0
2143.0
-2038.5
69
SEG34
-1060.0
2143.0
-2038.5
70
SEG35
-1205.0
2143.0
-2038.5
71
SEG36
-1350.0
2143.0
-2038.5
72
SEG37
-1495.0
2143.0
-2038.5
73
SEG38
-1640.0
2143.0
-2038.5
74
SEG39
-1785.0
2143.0
-2038.5
75
SEG40
-1930.0
2143.0
-1656.2
76
SEG41
-2088.0
1999.0
-1476.2
77
SEG42
-2088.0
1854.0
-1205.0
78
SEG43
-2088.0
1709.0
-1060.0
79
SEG44
-2088.0
1564.0
-915.0
80
SEG45
-2088.0
1419.0
-770.0
81
SEG46
-2088.0
1274.0
-625.0
82
SEG47
-2088.0
1129.0
-480.0
83
SEG48
-2088.0
984.0
-335.0
84
SEG49
-2088.0
839.0
-191.0
85
SEG50
-2088.0
694.0
-45.0
86
COMMK2
-2088.0
549.0
100.0
87
COM21
-2088.0
404.0
245.0
88
COM20
-2088.0
259.0
390.0
89
COM19
-2088.0
114.0
535.0
90
COM18
-2088.0
-31.0
680.0
91
COM17
-2088.0
-176.0
825.0
92
COM16
-2088.0
-321.0
970.0
93
COM15
-2088.0
-466.0
1115.0
94
COM7
-2088.0
-611.0
1260.0
95
COM6
-2088.0
-756.0
1405.0
96
COM5
-2088.0
-901.0
1550.0
97
COM4
-2088.0
-1046.0
1695.0
98
COM3
-2088.0
-1191.0
1840.0
99
COM2
-2088.0
-1336.0
1985.0
100
COM1
-2088.0
-1481.0
-3-
NJU6627
Preliminary
 BLOCK DIAGRAM
VCI
C1+
C1- VOUT
VLCD
V1
RB
V2
RB
V4
V3
RB
RB
RB
Voltage
Converter
S1 - S4
CSb
DATA
Icon Display
RAM(MKRAM)
20x5-bits
Character
Generator
RAM
(CG RAM)
5x7x32-bits
Character
Generator
ROM
(CG ROM)
7,840-Bits
Common Driver
SCL
Display Data RAM (DD RAM)
30x8bits
Timing
Generator
Segment Driver
I/O Buffer
REQ
Serial to parallel Convector
Reset
RESETb
Address
Counter
8bit shift Reg.
Power On Reset
Instruction
Decoder(ID)
K1 - K6
71bit Latch
CR osc. circuit
Data Resistor(DR)
OSC1
Instruction Resister(IR)
Keyscan circuit
COM1
- COM21
/COMMK1
COMMK2
SEG1
- SEG50
VSS
-4-
Ver.2013-12-25
NJU6627
Preliminary
 TERMINAL DESCRIPTION
No.
SYMBOL
10
VDD
17
VSS
9
I/O
FUNCTION
-
Power Source :VDD=+5V, GND :VSS=0V
VCI
I
Input terminal for voltage doubler
6
VOUT
O
Voltage doubler output terminal.
5
VLCD
4
V1
3
V2
I
2
V3
LCD driving voltage stabilization capacitor terminals.
Connect the capacitor between VSS.
typ. : 0.1uF
1
V4
7
C1+
8
C1-
11
OSC1
I
15
CSb
I
Resistor connection terminal for oscillation
/ External clock input terminal
Chip select signal input of serial I/F.
14
SCL
I
Shift clock input of serial I/F.
13
DATA
I/O
16
RESETb
I
12
REQ
O
Serial data input of serial I/F.
Reset terminal
When the "L" level is input over than 900us to this terminal,
the system will be reset ( at fOSC 200KHz ).
Key request signal output terminal.
18-23
K1-K6
I
Key scanning input terminals.
24-27
S1-S4
O
Key scanning output terminals.
36-85
SEG1-SEG50
O
LCD segment driving signal output terminals.
COM1-COM21
O
LCD common driving signal output terminals.
O
LCD Icon common driving signal output terminals.
Boosted capacitor connecting terminals used for voltage booster.
94-100
29-35
87-93
96
Ver.2013-12-25
COMMK1
COMMK2
-5-
NJU6627
Preliminary
 FUNCTIOAL DESCRIPTION
(1-1) Register
The NJU6627 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores instruction codes such as “Clear Display” and “Cursor Shift” or address data for
Display Data RAM (DDRAM), Character Generator ROM (CGRAM) and Icon Display RAM (MKRAM).
The Register (DR) is a temporary register, the data in the Register (DR) is written into the DDRAM,
CGRAM or MK RAM.
The data in the Register (DR) written by the MPU is transferred automatically to the DDRAM, CGRAM or
MKRAM by internal operation.
These two registers are selected by the selection signal RS as shown below.
(1-2) Address Counter (AC)
The address counter (AC) addresses the DDRAM, CGRAM or MKRAM.
When the address setting instruction is written into the Register (IR), the address information is
transferred from Register (IR) to the Counter (AC). The selection of either the DDRAM, CGRAM or
MKRAM is also determined by this instruction.
After writing (or reading) the display data to (or from) the DDRAM, CGRAM or MKRAM, the Counter (AC)
increments (or decrements) automatically.
(1-3) Display Data RAM(DD RAM)
The Display Data RAM (DD RAM) consist of 30 x 8 bits stores up to 30-character display data
represented in 8-bit code.
The DDRAM address data set in the address counter (AC) is represented in Hexadecimal.
AC
AD5
AD4
AD3
2bit.
AD2
AD1
Example) DD RAM address ”08”
0
0
1
0
0
AD0
4bit
0
8
0
The relation between DDRAM address and display position on the LCD is shown below.
1
00
10
20
2
01
11
21
3
02
12
22
4
03
13
23
5
04
14
24
6
05
15
25
7
06
16
26
8
07
17
27
9
08
18
28
10
09
19
29
Display Position
DD RAM address(Hex.)
When the display shift is performed, the DDRAM address changes as follows:
(00) 
(10) 
(20) 
(Left Shift Display)
01
02 03 04
11
12 13 14
21
22 23 24
05
15
25
06
16
26
07
17
27
08
18
28
09
19
29
00
10
20
(Right Shift Display)
09
00 01 02
19
10
11
12
29
20 21 22
03
13
23
04
14
24
05
15
25
06
16
26
07
17
27
08
18
28
(09)
(19)
(29)
(1-4) Character Generator ROM (CG ROM)
The Character Generator ROM (CG ROM) generates 5 x 7 dots character pattern represented in 8-bit
character code.
The storage capacity is up to 224 kinds of 5 x 7 dots character pattern (available address is (20)H
through (FF)H).
The correspondence between character code and standard character pattern of NJU6627 is shown in
Table 1. User-defined character patterns (Custom Font) are also available by mask option.
-6-
Ver.2013-12-25
NJU6627
Preliminary
Table 1. CG ROM Character Pattern ( ROM version -02 )
Ver.2013-12-25
CG
RAM
(01)
(17)
(02)
(18)
(03)
(19)
(04)
(20)
(05)
(21)
(06)
(22)
(07)
(23)
(08)
(24)
(09)
(25)
(10)
(26)
(11)
(27)
(12)
(28)
(13)
(29)
(14)
(30)
(15)
(31)
(16)
(32)
-7-
NJU6627
Preliminary
Table 2. CG ROM Character Pattern ( ROM version -03 )
-8-
CG
RAM
(01)
(17)
(02)
(18)
(03)
(19)
(04)
(20)
(05)
(21)
(06)
(22)
(07)
(23)
(08)
(24)
(09)
(25)
(10)
(26)
(11)
(27)
(12)
(28)
(13)
(29)
(14)
(30)
(15)
(31)
(16)
(32)
Ver.2013-12-25
NJU6627
Preliminary
(1-5) Character Generator RAM (CG RAM)
The character generator RAM (CG RAM) can store any kind of character pattern in 5 x 7 dots written
by the user program to display user's original character pattern. The CG RAM can store 32 kind of
character in 5 x 7 dots mode.
To display user's original character pattern stored in the CG RAM, the address data (00)H-(1F)H should
be written to the DD RAM as shown in Table 1.
Table 2. shows the correspondence among the character pattern, CG RAM address and Data
Table 2. Correspondence of CG RAM address, DD RAM character code
and CG RAM character pattern( 5 x 7 dots )
Character Code
(DD RAM Data)
CG RAM Address
76543210
76543210
Character
Pattern
(CG RAM Data)

Upper bit

Lower bit

Upper bit
00000000
00000
00000001
00001





00011111





11111

Lower bit
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001





100
101
110
111
43210


Upper
bit
Lower
bit
11110
10001
10001
11110
10100
10010
10001
* * * * *
10001
01010
11111
00100
11111
00100
00100
* * * * *
Character Pattern
Example (1)
Character Pattern
Example (2)





Character Pattern
Example (32)
* Don’t Care
Note) 1. Character code bit 0 to 4 correspond to the CG RAM address bit 3 to 7 (5bits:32 patterns).
2. CG RAM address 0 to 2 designate character pattern line position. The 8th line is Don't care line.
In case of input CG RAM data continuously, invalid address are Cursor position automatically.
3. Character pattern row position correspond to the CG RAM data bits 0 to 4 are shown above.
4. CG RAM character patterns are selected when character code of DD RAM bits 5 to 7 are all "0" and
these are addressed by character code bits 0 and 1.
5. "1" for CG RAM data corresponds to display On and "0" to display Off.
Ver.2013-12-25
-9-
NJU6627
Preliminary
(1-6) Icon Display RAM (MK RAM)
The NJU6627 can display maximum 100 Icons.
The Icon Display can be controlled by writing the Data in MK RAM corresponds to the Icon.
The relation between MK RAM address and Icon Display position is shown below:
COMMK1

1
COM8
COM9
COM10
COM11
COM12
COM13
COM14






COM15
COM16
COM17
COM18
COM19
COM20
COM21






COMMK2

51
SEG
Table 3.
12345
6 7 8 9 10
100
46 47 48 49 50
Correspondence among Icon Position, MK RAM Address and Data
MK RAM Address
(40H to 53H)
100 0000
100 0001
100 0010
100 0011
:
100 0101
50







COM1
COM2
COM3
COM4
COM5
COM6
COM7
40H
41H
42H
43H
:
53H
Bits for Icon Display Position
D7
0
0
0
0
D6
0
0
0
0
D5
0
0
0
0
D4
“1”
“6”
“11”
“16”
0
0
0
“96”
D3
“2”
“7”
“12”
“17”
D2
“3”
“8”
“13”
“18”
D1
“4”
“9”
“14”
“19”
D0
“5”
“10”
“15”
“20”
“97”
“98”
“99”
“100”
:
Note) After power on or hardware reset, the data of MK RAM can not be initialized. To display Icons, the data
of MKRAM need to be written in before display on. The displayed icons can not be shifted by Display Shift
instruction.
(1-7) Timing Generator
The timing generator generates a timing signals for the DD RAM, CG RAM and MK RAM and other
internal circuits.
RAM read timing for the display and internal operation timing for MPU access are separately
generated, so that they may not interfere with each other.
Therefore, when the data write to the DD RAM for example, there will be no undesirable influence,
such as flickering, in areas other than the display area.
(1-8) LCD Driver
LCD Driver consists of 23-common driver and 50-segment driver.
The character pattern data are latched to the addressed Segment-register respectively. This latched
data controls display driver to output LCD driving waveform.
- 10 -
Ver.2013-12-25
NJU6627
Preliminary
(1-9) Keyscan circuit
The Keyscan circuit consists of a detector block of key pressing and a fetching block of key status. It
scans 4x6 key matrix and fetches conditions of 24 keys. Furthermore, it operates correctly against the
key roll over input.
Key matrix
S4 S3 S2 S1
NJU6627
K6 K5 K4 K3 K2 K1
ON
OFF
(1-10) Timing of Key scan
Key scan cycle is 64 x T[s]. The data of key scan is a result of comparison with a couple of Key scan
for correct judge whether Key On or Off. When the result of comparison is correct (accord), the NJU6627
recognizes Key On and outputs “L” level from SO terminal after 128 x T[s] from start of Key scan for a
request to read key data out to external CPU. When the REQ terminals outputs “H” signal, the key
scan does not operate until end of key data reading by CPU, and scanned key data is kept. When the
result of comparison is incorrect (not accord), Key scan operates again if any key is On. Therefore,
Key scan may operate incorrectly in case of shorter period of Key on than 128 x T[s]
Key turn ON
64 x T[s]
S1
S2
S3
S4
1
1
2
2
3
3
4
REQ
4
T=1/ fosc
128 x T [s]
 Request signal output
When the NJU6627 detect the key-in to scan start by the key scan circuit, it outputs “H” signal as the
request signal from the “REQ” terminal to notice the key pressing information to an application system.
The request signal resets to “L” level after Keyscan data read.
 Contents of key register renewal
Contents of key register are no fixed in case of no key operation.
Contents of key register are not changed in busy of key data reading operation.
It stops when a couple of data by continuously twice key scan operations are accorded and fixed as a
correct key status. The correct key status data is stored and newly key scan operation does not start
until external CPU reads data out after key status is fixed.
When a key on the key matrix is pressed, the bit corresponding to terminals (S1 to S4, K1 to K6)
connected the switch goes to “1” and another bits go to “0”.
In case of Example 1, when the switch connecting to K2 and S3 is pressed, bit (D1) corresponding to
S3 and K2 go to “1” but another bits go to “0”.
Ver.2013-12-25
- 11 -
NJU6627
Preliminary
Example 1. One key is pressed
NJU6627
Key matrix
S4 S3 S2 S1
K6 K5 K4 K3 K2 K1
ON
OFF
Key register
D5
D4
D3
D2
D1
D0
K6
K6
K6
K6
K5
K5
K5
K5
K4
K4
K4
K4
K3
K3
K3
K3
K2
K2
K2
K2
K1
K1
K1
K1
S1
S2
S3
S4
Keyscan data format
Scanned 6-bit data of key are read out through the srial I/F. After the register is chosen, data is read.
D15
1
D14
0
D13
1
D12
0
D11
0
D10
1
D9
D8
SX1
SX0
Input
SX1
0
0
1
1
D7
*
D6
*
D5
K6
D4
K5
D3
K4
D2
K3
D1
K2
D0
K1
Output
SX0
0
1
0
1
Keyscan output terminal
S1
S2
S3
S4
 Keyscan OFF mode
Keyscan operation is turned ON or OFF by the instruction.
After the scanning ends, the key scanning is turned off.
The request signal is output until reading out data even if the turn off command enters while scanning
the key. The REQ signal outputs "L" if it reads out data.
- 12 -
Ver.2013-12-25
NJU6627
Preliminary
Key scan operates shown as follows
1, Key scan signal output terminals S1 – S4 output “L” signals when key scan does not operate, and output
key scan signals after start of key scan operation. The conditions of key scan signal input terminals K1 –
K6 are “H” state with internal pull-up resistances, though “L” signal comes in to K1 – K6 corresponding to
the turned on keys.
2, The function of key scan starts twice operations when any key is turned on. It stops when a couple of
data by continuously twice key scan operations are accorded and fixed as a correct key status. It operates
more 2 times when the key status is not fixed and any keys are still turning on. It repeats again and again
until key status is fixed. The correct key status data is stored and newly key scan operation does not start
until external CPU reads data out after key status is fixed.
3, When the key status is fixed, REQ terminal outputs “H” signal as Key data read out request to CPU. CPU
should read key data out at detection of this “L” signal.
4, The Key data read out request signal is released and REQ terminal outputs “L” signal after finish of CPU
key data read out for newly key scan operation. REQ signal shall not be reading between "L".
Keyscan example
T = 1/fosc
Key input 1
Key input 2
Keyscan
128T[s]
128T[s]
128T[s]
Key data read request
Key data read request
Key data read request
REQ
CSb
SCL
DATA
S1
S2
S3
S4
S1 to S4
Key data read
Ver.2013-12-25
S1
S2
S3
S4
S1 to S4
Key data read
S1
S2
S3
S4
S1 to S4
Key data read
- 13 -
NJU6627
Preliminary
Key data read flow example
Key Data Read Process
No
Note)After key data read, please decision R
EQ signal at the time of REQ decision ti
me of the figure below.
REQ=”H” ?
Yes
CSb
Key data read (S1)
1xT [s]
REQ=”H” ? (note)
REQ decision time
127 x T [s]
No
Yes
REQ
Key data read (S2)
T=1/ fosc
REQ=”H” ? (note)
No
Yes
Ex.) Cace of fosc=200KHz
REQ decision time = 127 x 5us = 635us
Key data read (S3)
REQ=”H” ? (note)
No
Yes
Key data read (S4)
Fix Key data
No
Finish ?
Yes
Finish
(1-11) Key More Input
non-pressed key data may change pressed key data in triple or more key Input as shown in Fig. 1 and
incorrect key data may be output to external CPU. For prevention of miss-recognition by incorrect key
data, diodes should be inserted or control program of CPU should ignore the combination of key data
miss-recognition. For example, 4 keys and more ON data should be ignored.
S1
Pressed key
S2
Miss-recognized key
S3
S4
K1
K2
In case of 3 keys operation in left
picture, if S4 terminal outputs “L”
signal, this signal goes around on
the dotted line and non-pressed key
is miss-recognized as pressed
key.
K3
K4
K5
K6
Fig. 1 Miss-recognized example by key more input
- 14 -
Ver.2013-12-25
NJU6627
Preliminary
(2) Power on Initialization by internal circuits
(2-1) Initialization By Internal Reset Circuits
The NJU6627 is automatically initialized by internal power on initialization circuits when the power is
turned on. In the internal power on initialization, following instructions are executed. During the Internal
power on initialization, this status is kept 1.45ms (fosc=200kHz) after VDD rises to 2.4V. Initialization flow
is shown below:
Display ON/OFF control
D=0
M=0
B=0
Display OFF
Icon OFF
Cursor Blink OFF
Entry mode set
I/D=1
S=0
Increment by 1
No Shift
Cntrast control
Set Display mode
Clear Display
E.V.R Value=0000
VLCD Low
V=0
DU=1
K=1
PD=0
Voltage Booster Circuits OFF
Set 1/23Duty (3-line + Icon)
Keyscan ON
Release the power down mode
AC=00H
Initialize the address counter to 00H
20H is written on DD RAM
End
Note) If the condition of power supply rise time described in the Electrical Characteristics is not satisfied,
the internal Power On Initialization Circuits will not operated and initialization will not performed.
In this case the initialization by MPU software is required.
(2-2) Initialization By Hardware
The NJU6627 incorporates RESETb terminal to initialize the all system. When the "L" level input over
900us to the RESETb terminal, reset sequence is executed. In this time, busy signal output during
550us (fosc=200kHz) after RESETb terminal goes to "H". During this 550us period, any other instruction
must not be input to the NJU6627.
 Timing Chart
Over 900us
External
RESETb Signal
550us
Busy
Ver.2013-12-25
- 15 -
NJU6627
Preliminary
(3) Instructions
The NJU6627 incorporates two registers, an Instruction Register (IR) and a Data Register (DR).
These two registers store control information temporarily to allow interface between NJU6627 and MPU or
peripheral ICs operating different cycles.
Table 4.
Table of Instructions
Code
Instruction
D15
D14 D13
D12
D11
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(a)
Maker Testing
1
0
0
1
1
1
1
1
(b)
Clear Display
1
0
0
1
1
0
0
1
*
*
*
*
*
*
*
*
234.48us
(c)
Return Home
1
0
0
1
0
0
0
1
*
*
*
*
*
*
*
*
0us
(d)
Entry Mode Set
1
0
0
0
1
0
0
0
*
*
*
*
*
*
I/D
S
0us
(e)
Display ON/OFF
Control
1
0
0
0
1
0
0
1
*
*
*
*
*
D
M
B
0us
(f)
Address Shift
1
0
0
1
0
0
1
0
*
*
*
*
*
*
*
ARL
0us
(g)
Display Shift
1
0
0
0
1
0
1
0
*
*
*
*
*
*
*
DRL
0us
(h)
Contrast Control
1
0
0
0
1
1
0
0
*
*
*
*
1
0
0
0
1
1
1
0
*
*
*
*
1
0
0
1
0
0
1
1
*
*
1
0
0
1
0
0
0
0
CG RAM (00 to FE)H
0us
1
0
0
1
1
0
0
0
Write Data (DD RAM)
41.38us
1
0
0
1
1
0
0
0
*
*
*
1
0
0
1
1
0
0
0
*
*
*
1
0
1
0
0
1
*
*
(i)
(j)
(k)
(l)
(m)
*1
- 16 -
Set Display
Mode
Set DD/MK
RAM Address
Set CG RAM
Address
Write DD RAM
Data
Write MK RAM
Data
Write CG RAM
Data
Read Keyscan
Data
SX
Test Data
Execute Time
*1
*
-
E.V.R Value
V
DU
K
0us
PD
DD RAM (00 to 29)H
MK RAM (40 to 53)H
Write Data
(MK RAM)
Write Data
(CG RAM)
Key Data
0us
0us
41.38us
41.38us
0us
fOSC=200KHz. If the oscillation frequency is changed, the execution time is also changed.
Ver.2013-12-25
NJU6627
Preliminary
(3-1) Description of each instructions
(a) Maker Test
Code
D15
1
D14
0
D13
0
D12
1
D11
1
D10
1
D9
1
D8
1
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
*
D0
*
*: Don’t care
This code is using for device testing mode (only for maker).
Therefore, please avoid all "0" input or no meaning Enable signal input at data "0".
(Especially please check the output condition of Enable signal when the power turns on.)
(b)
Clear Display
Code
D15
1
D14
0
D13
0
D12
1
D11
1
D10
0
D9
0
D8
1
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
*
D0
*
When this instruction is executed, the space code (20)H is written into every DD RAM address, the DD
RAM address (00)H is set into the address counter and entry mode is set to increment. The S of entry
mode does not change.
Note) The character pattern for character code (20)H must be blank code in the user-defined
character
pattern (Custom font).
(c)
Return Home
Code
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
0
D8
1
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
*
D0
*
Return home instruction is executed, the DD RAM address (00)H is set into the address counter.
Display is returned its original position if shifted. The DD RAM contents do not change.
(d)
Entry Mode Set
Code
D15
1
D14
0
D13
0
D12
0
D11
1
D10
0
D9
0
D8
0
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
I/D
D0
S
Entry mode set instruction which sets the address moving direction and display shift On/Off, is
executed when the codes of (I/D) and (S) are written into DB1(I/D) and DB0(S), as shown below.
(I/D) sets the address increment or decrement, and the (S) sets the whole display shift in the DD RAM
writing.
I/D
1
0
S
1
0
Ver.2013-12-25
Function
Address increment : The address of the DD RAM or MK RAM or CG RAM
increment(+1) when the write.
Address decrement : The address of the DD RAM or MK RAM or CG RAM
decrement(-1) when the write.
Function
Whole display shift.
The shift direction is determined by I/D. : Shift to the left at I/D=1 and shift
to the right at the I/D=0.
The display does not shift when writing into CG RAM, MK RAM
The display does not shift.
- 17 -
NJU6627
Preliminary
(e)
Display ON/OFF Control
Code
D15
1
D14
0
D13
0
D12
0
D11
1
D10
0
D9
0
D8
1
D7
*
D6
*
D5
*
D4
*
D3
*
D2
D
D1
M
D0
B
Display On/Off control instruction which controls the whole display On/Off and the addressed position
character blink, is executed when the codes of (D) and (B) are written into DB2(D) and DB0(B), as shown
below.
D
1
Function
Display On.
Display Off. In the mode, the display data remains in the DD RAM so that
it is retrieved immediately on the display when the D change to 1.
0
M
Function
1
Icon display ON.
0
Icon display OFF.
B
Function
The addressed position character is blinking. Blinking rate is 500ms at
fOSC=145kHz.
The cursor and the blink can be displayed simultaneously.
The character does not blink.
1
0
Character Font 5 x 7 dots
(1) Cursor display example
Alternating display
(2) Blink display example
When the number of dot-shift is not set “0” in (j) Dot shift instruction, the blink operation will be
appeared at the irregular position.
(f)
Address Shift
Code
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
1
D8
0
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
*
D0
ARL
The Address shift instruction shifts the Address to the right or left without writing or reading display
data.
ARL
- 18 -
Function
0
Shift the address position to the left ((AC) is decremented by 1)
1
Shift the address position to the right ((AC) is incremented by 1)
Ver.2013-12-25
NJU6627
Preliminary
(g)
Display Shift
Code
D15
1
D14
0
D13
0
D12
0
D11
1
D10
0
D9
1
D8
0
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
*
D0
DRL
The Display shift instruction shifts the Display to the right or left without writing or reading display data.
The contents of address counter (AC) does not change by operation of the display shift only.
DRL
(h)
Function
0
Shifts the whole display to the left and the cursor follows it.
1
Shifts the whole display to the right and the cursor follows it.
Contrast Contol
Code
D15
1
D14
0
D13
0
D12
0
D11
1
D10
1
D9
0
D8
0
D7
*
D6
*
D5
*
D4
*
D3
C3
D2
C2
D1
C1
D0
C0
Contrast Control instruction which adjusts the contrast of the LCD is executed when the code "1" is
written into D6 and the codes of C3 to C0 are written into D3 to D0 as shown below.
The contrast of LCD can be adjusted one of 16 voltage-stages by setting this 4-bit register.
See (4-1) "how to adjust the Contrast of LCD".
Set the binary code "1,1,1,1" when contrast adjustment is unused.
C3
C2
C1
C0
VLCD voltage (Spec)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT x 80/95
VOUT x 80/94
VOUT x 80/93
VOUT x 80/92
VOUT x 80/91
VOUT x 80/90
VOUT x 80/89
VOUT x 80/88
VOUT x 80/87
VOUT x 80/86
VOUT x 80/85
VOUT x 80/84
VOUT x 80/83
VOUT x 80/82
VOUT x 80/81
VOUT x 80/80
Ver.2013-12-25
Ex.) VLCD voltage by
VOUT=8.4V
7.074
7.149
7.226
7.304
7.385
7.467
7.551
7.636
7.724
7.814
7.906
8.000
8.096
8.195
8.296
8.400
- 19 -
NJU6627
Preliminary
(i)
Set Display Mode
Code
D15
1
D14
0
D13
0
D12
0
D11
1
D10
1
D9
1
D8
0
D7
*
D6
*
D5
*
D4
*
D3
V
D2
DU
D1
K
D0
PD
The Set Display Mode instruction control the function of Keyscan and power down mode.
V
1
0
DU
1
0
K
1
0
PD
1
0
Function
Voltage Booster Circuits ON.
Voltage Booster Circuits OFF.
When the internal voltage booster is not used, supply each level of LCD
driving voltage from VOUT terminal.
Function
1/23Duty (3-line + Icon)
1/16Duty (2-line + Icon)
Function
Keyscan ON
Keyscan OFF
All of segment terminal (S1 to S4) output the voltage of VSS.
Function
Power down mode.
All common and segment terminal set the voltage level of VSS.
Release the power down mode.
In busy of Power down mode, do not input any instructions except for release the power down mode.
The power down mode should be set before power off because any irregular display appearance at
power off is prevented.
 The Keyscan operation when switching to the power down mode during Keyscan
When switching to the power down mode during key scan operation, it stops Keyscan operation in the
period and after power down mode restart the Keyscan.
After power down mode cancellation, the REQ signal maintains "H" when detects key-in signal before
switches to power down mode and REQ signal rises to "H".
However, the key scan operation becomes invalid data even if it reads key-in data because it stopped.
- 20 -
Ver.2013-12-25
NJU6627
Preliminary
(j)
Set DD/MK RAM Address
Code
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
1
D8
1
D7
*
D6
D5
D4
D3
D2
D1
D0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
The address data (D4 to D0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed DD/MK RAM.
The RAM includes DD RAM and MK RAM, and these RAMs are shared by address as shown below.
DD RAM 1-line:
DD RAM 2-line:
DD RAM 3-line:
MK RAM :
(k)
RAM Address
(00)H to (09)H
(10)H to (19)H
(20)H to (29)H
(40)H to (53)H
Set CG RAM Address
Code
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
AC7
AC6
AC5
AD4
AD3
AD2
AD1
AD0
The CG RAM address set instruction is executed when the "H" level input to the AC terminal and the
address is written into D7 to D0 as shown above.
The address data (D7 to D0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed RAM.
The RAM includes CG RAM address as shown below.
CG RAM :
Ver.2013-12-25
RAM Address
(00)H to (FE)H
- 21 -
NJU6627
Preliminary
(l)
Write Data to CG, DD or MK RAM
 Write Data to DD RAM
Code
D15
1
D14
0
D13
0
D12
1
D11
1
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
D11
1
D10
0
D9
0
D8
0
D7
*
D6
*
D5
*
D4
D3
D2
D1
D0
DM4
DM3
DM2
DM1
DM0
D11
1
D10
0
D9
0
D8
0
D7
*
D6
*
D5
*
D4
D3
D2
D1
D0
DC4
DC3
DC2
DC1
DC0
 Write Data to MK RAM
Code
D15
1
D14
0
D13
0
D12
1
 Write Data to CG RAM
Code
D15
1
D14
0
D13
0
D12
1
By the execution of this instruction, the binary 8-bit data (D7 to D0) are written into the DD RAM, and
the binary 5-bit data (D4 to D0) are written into the CG or MK RAM. The selection of RAM is determined
by the previous instruction. After this instruction execution, the address increment (+1) or decrement (-1)
is performed automatically according to the entry mode set. And the display shift is also executed
according to the previous entry mode set.
(m)
Read Data Key
Code
D15
1
D14
0
D13
1
D12
0
D11
0
D10
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SX1
SX0
*
*
K6
K5
K4
K3
K2
K1
Input
Output
Read data key is a instruction for data reading out of Keyscan.
Select read register.
SX1
0
0
1
1
SX0
0
1
0
1
Keyscan output terminal
S1
S2
S3
S4
However, the bit 8 to 15 are input data. After this 8-bit data were input, the operation change to output
from input at the falling edge of 8th SCK clock.
- 22 -
Ver.2013-12-25
NJU6627
Preliminary
(3-2) Initialization by instruction
If the power supply conditions for the correct operation of the internal reset circuits are not satisfied,
the NJU6627 must be initialized by the instruction.
Initialized.
No display appears.
Power ON
Wait more than 1.45ms
after VDD rises to 2.4V
Entry Mode Set
1
0
0
0
1
0
0
0
*
*
*
*
*
*
I/D
S
Contrast Control
1
0
0
0
1
1
0
0
*
*
*
*
C3
C2
C1
C0
Set Display Mode
1
0
0
0
1
1
1
0
*
*
*
*
V
DU
K
PD
Clear Display
1
0
0
1
1
0
0
1
*
*
*
*
*
*
*
*
Note) When the Icon display function using, the
system should be initialized by software
initialization.
Write data to the DD, CG or MK RAM and set
the instruction
Display ON/OFF
Ver.2013-12-25
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
1
*
*
*
*
*
0
(D)
0
(M)
0
(V)
- 23 -
NJU6627
Preliminary
(4) Internal power circuits
(4-1) Voltage converter
The doubler power voltage input from the VCI terminal can be turned on and off by setting the
instruction.
Set Display Mode instruction D3 = "1" : Voltage Booster Circuits ON
The voltage input to the VCI terminal is boost 2-times. Please set the input so that the output
should not exceed 10.5V.
Set Display Mode instruction D3 = "0" : Voltage Booster Circuits OFF
The voltage converter output is turned off.
Irregular data displayed at power supply ON or OFF, and turn off Voltage converter.
When the internal voltage booster is not used, supply each level of LCD driving voltage from
VOUT terminal.
NJU6627
VOUT
For E.V.R. circuit /
Internal Bleeder Resistance
Cout
C1+
typ. : Cout=C1=1.0 uF
C1
C1Input voltage doubler power
VCI
Voltage Doubler
- 24 -
Ver.2013-12-25
NJU6627
Preliminary
(4-2) Bleeder Resistance
Each LCD driving voltage ( V1, V2, V3, V4 ) is LCD driving high voltage input to the VLCD1 terminal,
generated by the E.V.R. and high impedance bleeder resistance.
The bleeder resistance is set 1/4 bias suitable for 1/8 duty ratio.
The capacitor connected between VLCD2 / V1/ V2/ V4 and VSS is needed for stabilizing VLCD. The
determination of the each capacitance requires to operate with the LCD panel actually.
LCD Driving Voltage v.s. Duty Ratio
Duty Ratio
1/16, 1/23
Power supply
Bias
1/5
VLCD
VLCD2- VSS
VLCD is the maximum amplitude
for LCD driving voltage.
Internal NJU6627
From Voltage Doubler
VOUT
E.V.R (16 Step)
3.75KΩ
VLCD
+
VLCD
+
4KΩ
V1
V1
+
4KΩ
V2
V2
+
4KΩ
V3
V3
+
VLCD
4KΩ
V4
V4
+
4KΩ
Power Down OFF
VSS
VSS
(4-3) Oscillation Circuit
A resistor and capacitor are connected to OSC1 pin to configure the oscillation circuit. External clock
can also be inputted through the OSC1 pin.
VDD
NJU6627
120kΩ
(fOSC=200kHz TYP.)
OSC1
33pF
Ver.2013-12-25
- 25 -
NJU6627
Preliminary
(4-4) Relation between oscillation frequency and LCD frame frequency
As the NJU6627 incorporate oscillation capacitor and resistor for CR oscillation, 200kHz oscillation is
available without any external components.
The LCD frame frequency example mentioned below is based on 200kHz oscillation.(1clock =5.0us)
160 clock
23
COMMK1
1
2
3
4

23
1
2
3
4

23
1
2
3
VLCD
V1
V2
V3
V4
VSS
1 frame
1 frame
1 frame = 5.0(us) x 160 x 23 = 12.65(ms)
Frame frequency = 1 / 12.65(ms) = 79.0(Hz)
(5) Interface with MPU
The instructions and data are communicated with the serial port which is a clock synchronization type
based on 16-bit per word.
The NJU6627 can be controlled by the serial data as shown below.
CSb
SCL
DATA
The serial interface circuit operates in CSb=L.
A communication unit consists of 16-bit data. The communication period is from the falling edge of CSb
terminal to the rising edge. The inputs data and latched at rising edge of shift clock (SCL) and the first 16-bit
data are fetched into the NJU6627 at the rising edge of chip select (CSb). The data over than 16 bits are
ignored. If the input data are less than 16 bits, they are ignored at the rising edge of "CSb". Therefore, just 16
bits data should be input for the correct communication. In case of RAM data input, the RAM address is
changed automatically as increment or decrement.
The data to input is MSB first. Although the output data is just only key scan, data bits D8 to D15 in the key
data read out instruction are input. After these 8-bit instruction is input, this serial data input terminal is
changed to the output terminal at the 8th falling edge of SCL clock.
The electrical short between the NJU6627 and external circuit must be prevented in the application.
- 26 -
Ver.2013-12-25
NJU6627
Preliminary
 ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Input Voltage
Operating Temperature
Storage Temperature
(Ta=25°C)
SYMBOL
RATINGS
UNIT
NOTE
VDD
VCI
VOUT,
VLCD,
V1 to V4
-0.3 to +7.0
-0.3 to +7.0
V
V
VCI Terminal
VSS+0.3 to VSS+10.5
V
VOUT, VLCD,
V1 to V4 Terminal
Vt
-0.3 to VDD+0.3
V
OSC1, SCL, DATA,
CSb, RESETb,
K1-K6 terminals
Topr
Tstg
-40 to +85
-55 to +125
°C
°C
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed.
Using the LSI within electrical characteristics is strongly recommended for normal operation.
Use beyond the electric characteristics conditions will cause mal function and poor reliability.
Note 2) Decoupling capacitor should be connected between VDD-VSS, VCI-VSS, VOUT-VSS due to the stabilized
operation for the Voltage converter.
Note 3) All voltage values are specified as VSS = 0V
The relation : VOUT  VLCD > VDD > VSS, VSS=0V must be maintained.
Note 4) in case of internal Voltage Doubler use, VOUT  VCI x 2 must be maintained.
Ver.2013-12-25
- 27 -
NJU6627
Preliminary
 ELECTRICAL CHARACTERISTICS
(VDD=4.5V to 5.5V, Ta= -40 to +85°C)
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
Power supply (1)
VDD
VDD
4.5
-
5.5
V
Power supply (2)
VCI
VCI
3.0
-
5.0
V
Power supply (3)
VOUT
VIH1
VIL1
VIH2
VIL2
VOH1
VDD
0.8VDD
VSS
0.8VDD
VSS
4.0
-
10.0
VDD
0.2VDD
VDD
0.4VDD
-
V
-
-
0.5
Input Voltage (1)
Input Voltage (2)
Output Voltage (1)
VOL1
VOUT
OSC1,SCL, DATA, CSb, RESETb
K1-K6
IOH1=-2mA,VDD=5.0V
REQ,DATA
IOL1=1mA,VDD=5.0V
IOH=-20uA
,VDD=5.0V
IOL2=500uA
,VDD=5.0V
VOH2
Output Voltage (2)
S1-S4
VOL2
Driver On-resist. (COM)
RCOM
COM1-COM21
COMMK1,
COMMK2
Driver On-resist. (SEG)
RSEG
SEG1-SEG50
Pull-up MOS Current 1
Pull-up MOS Current 2
-Ip1
-Ip2
Input Leakage Current
ILI
DATA
K1-K6
SCL, CSb,
RESETb
IDD1
VDD
Operating Current
IDD2
ICI
VCI
±Id=1uA(COM)
VO=VLCD,VSS,V1,V4
±Id=1uA(SEG)
VO=VLCD,VSS,V2,V3
VDD=5V, VIN =VSS
VDD=5V, VIN =VSS
VIN=0 to VDD
VDD=5V, fOSC=200 kHz,
Display ON, Keyscan ON
VDD=5V,
Power down mode
VCI=5V, fOSC=200 kHz,
0.8VDD
VDD
VSS
0.2VDD
No
te
4
V
V
V
V
-
-
40
k
5
-
-
40
k
5
5
10
25
25
50
50
uA
uA
-1.0
-
1.0
uA
-
120
300
uA
6
-
5
10
uA
6
1.1
1.6
mA
Voltage Booster Circuits ON
E.V.R. value : "1111"
LCD Driving
Voltage
V1
V2
V3
V4
V1
V2
V3
V4
E.V.R. value : "1111"
VLCD= 8.0V
6.2
4.6
3.0
1.4
6.4
4.8
3.2
1.6
6.6
5.0
3.4
1.8
V
Bleeder
resistance
RB=
(VLCD-VSS)/IB
RB
VLCD
E.V.R. value : "1111"
VOUT=8.0V, Ta=25°C
14.0
20.0
26.0
K
Voltage Booster
output voltage
Vout
VOUT
9.0
9.8
Internal
Oscillation Frequency
fOSC
OSC1
160
200
240
kHz
External Clock Frequency
External Clock Duty
fCP
Duty
OSC1
OSC1
280
45
400
50
520
55
kHz
%
VOUT Current
IOUT
VOUT
-
0.4
1.0
mA
Bleeder
resistance
circuit
- 28 -
VCI=5V, fOSC=200 kHz,
Voltage Booster Circuits ON
Ta=25°C
VDD=5V, Ta=25°C
Rosc=120kΩ,
Cosc=33pF
Input from OSC1
Input from OSC1
VOUT=8.0V
E.V.R. value : ”1111”
Ta=25°C
V
Ver.2013-12-25
7
NJU6627
Preliminary
Note 4) Apply to the output voltage from each COM and SEG are less than +0.15V against the LCD driving
constant voltage (VDD, VLCD1) at no load condition.
Note 5) RCOM and RCOM are the resistance values between power supply terminals (VSS, VLCD or V1,V4) and each
common terminal (COM1 to COM21/COMMK1/COMMK2) and supply voltage (VSS, VLCD or V2,V3) and
each segment terminal (SEG1 to SEG50) respectively, and measured when the current Id is flown on
every common and segment terminals at a same time.
 Operating Current Measurement Circuit
5V
NJU6627
A
VDD
Vss
Note 6) If the input level is medium, current consumption will increase due to the penetration current. Therefore,
the input level must be fixed to "H" or "L".
Note 7) External Clock Frequency is 1/2 dividing frequency internally. Therefore, it becomes the same frequency
as the internal oscillation circuit.
Ver.2013-12-25
- 29 -
NJU6627
Preliminary
 Bus timing characteristics
 Serial Interface Sequence
(VDD=4.5V to 5.5V, Ta=-40 to +85°C)
MAX
UNIT
Note
us
ns
us
8
us
9
us
10
ns
ns
ns
ns
300
ns
PARAMETER
SYMBOL
MIN
Serial clock cycle time
tCYCE
1
Serial clock width
tSC
300
Chip select pulse width
800
Chip select pulse width
PW CS
50
Chip select pulse width
1
Chip select set up time
tCSU
300
Chip select hold time 1
tCHI
300
Serial input data set up time
tSISU
300
tSIH
Serial input data hold time
300
Key data output delay time
tKDD
Data port direction change time
tSRWD
300
from input to output
Data port direction change time
tCRWD
300
From output to input
Chip select hold time 2
tCH2
1
Input Signal Rising Edge
tR
15
Input Signal Falling Edge
tF
15
Note8) Condition: The clear display command input. (Refer to the Table 4)
Note9) Condition: The Ram writing and power down mode ON. (Refer to the Table 4)
Note10) Condition: The instruction input except Note8 and Note9. (Refer to the Table 4)
Fig.1
ns
ns
us
ns
ns
Input Data Sequence
tR
tF
tCSU
CSb
tCYCE
tR
tSC
SCL

tSC
tCH1
tR/tF

DATA
tSISU
Fig.2
PW CS
tF
F
tSIH
Output Data Sequence
tCH2
CSb
8
9
10
15
16

SCL
tKDD
DATA
Input
Output
Output

DATA I/O
Change timing
Output
Output
Input
- 30 -
Output
tCRWD
tSRWD
Input
Ver.2013-12-25
NJU6627
Preliminary
 The Input Condition when using the Hardware Reset Circuit
(Ta=25°C)
PARAMETER
Reset input “L” level width (fOSC=200KHz)
SYMBOL
MIN
TYP.
MAX
UNIT
tRSL
1.2
-
-
ms
NOTE
tRSL
RESET
VIL
 Power Supply Condition when using the internal initialization circuit
(Ta=25°C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Power supply rise time
trDD
0.1
-
5
ms
Power supply OFF time
tOFF
1
-
-
ms
NOTE
Since the internal initialization circuits will not operate normally unless the above conditions are met, in
such a case initialize by instruction. (Refer to initialization by the instruction)
2.4V
0.2V
VDD
0.2V
0.2V
tOFF
trDD
0.1ms ≤ trDD ≤ 5ms
tOFF ≥ 1ms
 Key scan timing
(fOSC=200KHz)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Keyscan time
tKS
-
320
-
us
Keyscan palse width
tKP
-
80
-
us
NOTE
VDD
S1
VSS
VDD
S2
VSS
tKP
VDD
S4
VSS
tKS
Ver.2013-12-25
- 31 -
NJU6627
Preliminary
 LCD DRIVING WAVE FORM
COMMK1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COMMK2
SEG
MK
1
COMMK1
COM1
COM2
COMMK2
SEG1
SEG2
- 32 -
1
1 2 3 4 5
2
3
----
21
MK MK
2
1
1
2
3
----
21
MK MK
2
1
1
2
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS








VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
Ver.2013-12-25
NJU6627
Preliminary
 APPLICATION CIRCUITS
OSC1
COMMK1
COM1
CPU

RESETb
REQ
SCL
CSb
DATA
COM21
COMMK2
VDD
SEG1
VLCD
V1
V2
V3
V4
+
+
+
+
+
NJU6627

+
VCI
C1+
C1VOUT
LCD Panel
10-character
3-line+Icon
SEG50
+
VSS
S4 S3 S2 S1 K6 K5 K4 K3 K2 K1
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2013-12-25
- 33 -