NJRC NJU6631ACH

NJU6631A
PRELIMINARY
16-CHARACTER 1-LINE DOT MATRIX
LCD CONTROLLER DRIVER
■ GENERAL DESCRIPTION
The NJU6631A is a 1 Chip Dot Matrix LCD controller
driver for up to 16-character 1-line or 8-character 2-line
display.
It contains microprocessor interface circuits,
instruction decoder controller, character generator
ROM/RAM and common and segment drivers.
The bleeder resistance generates for LCD Bias
voltage internally.
The CR oscillator incorporates C and R, therefore no
external components for oscillation are required.
The microprocessor interface circuits which operate
2MHz frequency, can be connected directly to 4bit/8bit
microprocessor.
The character generator consists of 9,600 bits ROM
and 32 x 5 bits RAM. The standard version ROM is
coded with 192 characters including capital and small
letter fonts.
The 16-common and 40-segment drives up to 16character 1-line LCD panels which divided two common
electrode blocks.
The rectangle outlook is very applicable to COG or
Slim TCP.
■ PACKAGE OUTLINE
NJU6631ACH
■ FEATURES
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16-character 1-line Dot Matrix LCD Controller Driver
4/8 Bit Microprocessor Direct Interface
Display Data RAM
- 16 x 8 bits : Maximum 16-character 1-line Display
Character Generator ROM - 9,600 bits : 240 Characters for 5 x 8 Dots
Character Generator RAM - 32 x 5 bits : 4 Patterns(5 x 8 Dots)
Microprocessor can access to Display Data RAM and Character Generator RAM
High Voltage LCD Driver
: 16-common / 40-segment
Duty Ratio
: 1/16 Duty
Number of Maximum Display Characters : 16-character
Useful Instruction Set
Clear Display, Return Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink,
Cursor Shift, Character Shift,
Common and Segment driver Location order Select Function(Pin configuration mode A / mode B)
Power On Initialize / Hardware Reset Function
Bleeder Resistance On-chip
Oscillation Circuit On-chip
Low Power Consumption
Operating Voltage --- +5V
Package Outline
--- Bumped Chip
C-MOS Technology
31.Mar,2000
Ver.1
NJU6631A
■ PAD LOCATION
31
74
Y
X
18
1
Chip Size
: 3.58mm x 1.68mm
Chip Center
: X=0um, Y=0um
Bump Material : Au
Bump Size
Bump Height
: 90um x 55um
: 17.5um TYP.
8
4
Busy
Flag
VSS
5
5
Character
Generator
RAM
(CG RAM)
32x5bits
5
VDD
R1
LCD Driver
V1
R1
V2
R1
V3
R1
V4
R1
V5
8
Character
Generator
ROM
(CG ROM)
9,600bits
40
5
Parallel to Serial
Converter
40bit
Shift Reg.
Common
Driver
16
Segment
Driver
8
8
Data Reg.
(DR)
DB0∼DB3
I/O Buffer
DB4∼DB7
Display Data RAM
(DD RAM)
16x8bits
16bit
Shift Reg.
7
8
4
7
7
8
RS
R/W
E
Timing
Gen.
Latch
CR
OSC
Instruction 7 Address
Decoder(ID)
Counter(AC)
40bit
OSC1
OSC2
8
Cursor Blink
Cont.
Power On
Reset
RESET
Instruction
Reg.(IR)
■ BLOCK DIAGRAM
16 COM
1
∼COM16
40
SEG1
∼SEG40
NJU6631A
■ PAD COORDINATES
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PAD Name
Pin Configuration
Mode A
Mode B
Dummy1 Dummy1
VDD
VDD
VDD
VDD
VDD
VDD
V5
V5
V5
V5
V5
V5
V3
V3
V2
V2
RESET
RESET
RS
RS
R/W
R/W
E
E
DB0
DB0
DB1
DB1
DB2
DB2
Dummy2 Dummy2
DB3
DB3
DB4
DB4
DB5
DB5
DB6
DB6
DB7
DB7
COM1
COM9
COM2
COM10
COM3
COM11
COM4
COM12
COM5
COM13
COM6
COM14
COM7
COM15
COM8
COM16
Dummy3 Dummy3
Dummy4 Dummy4
SEG1
SEG40
SEG2
SEG39
SEG3
SEG38
SEG4
SEG37
SEG5
SEG36
SEG6
SEG35
SEG7
SEG34
SEG8
SEG33
SEG9
SEG32
SEG10
SEG31
SEG11
SEG30
Center
X=(um)
Y=(um)
-1501
-1426
-1353
-1281
-1138
-1066
-993
-844
-614
-98
132
361
591
824
1091
1328
1406
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1630
1459
1383
1313
1243
1173
1103
1033
963
893
823
753
683
613
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-680
-486
-416
-322
-253
-160
-13
57
127
197
267
337
407
477
690
690
690
690
690
690
690
690
690
690
690
690
690
Note) Dummy1∼ Dummy5 are Dummy Pad.
Chip Size 3.58×1.68mm(Chip Center X=0um,Y=0um)
PAD Name
Center
PAD
Pin
Configuration
No.
X=(um)
Y=(um)
Mode A
Mode B
44
SEG12
SEG29
543
690
45
SEG13
SEG28
473
690
46
SEG14
SEG27
403
690
47
SEG15
SEG26
333
690
48
SEG16
SEG25
263
690
49
SEG17
SEG24
193
690
50
SEG18
SEG23
123
690
51
SEG19
SEG22
53
690
52
SEG20
SEG21
-17
690
53
SEG21
SEG20
-87
690
54
SEG22
SEG19
-157
690
55
SEG23
SEG18
-227
690
56
SEG24
SEG17
-297
690
57
SEG25
SEG16
-367
690
58
SEG26
SEG15
-437
690
59
SEG27
SEG14
-507
690
60
SEG28
SEG13
-577
690
61
SEG29
SEG12
-647
690
62
SEG30
SEG11
-717
690
63
SEG31
SEG10
-787
690
64
SEG32
SEG9
-857
690
65
SEG33
SEG8
-927
690
66
SEG34
SEG7
-997
690
67
SEG35
SEG6
-1067
690
68
SEG36
SEG5
-1137
690
69
SEG37
SEG4
-1207
690
70
SEG38
SEG3
-1277
690
71
SEG39
SEG2
-1347
690
72
SEG40
SEG1
-1417
690
73
Dummy5 Dummy5
-1501
690
74
COM16
COM8
-1630
402
75
COM15
COM7
-1630
332
76
COM14
COM6
-1630
262
77
COM13
COM5
-1630
192
78
COM12
COM4
-1630
122
79
COM11
COM3
-1630
52
80
COM10
COM2
-1630
-18
81
COM9
COM1
-1630
-88
82
OSC1
OSC1
-1630
-230
83
OSC2
OSC2
-1630
-300
84
VSS
VSS
-1630
-370
85
VSS
VSS
-1630
-443
86
VSS
VSS
-1630
-515
NJU6631A
■ TERMINAL DESCRIPTION
PAD No.
Pin Configuration
Mode A
Mode B
2,3,4
2,3,4
84,85,86 84,85,86
9,8,
9,8,
7,6,5
7,6,5
82
83
82
83
SYMBOL
VDD
VSS
V2,V3,
V5
OSC1
OSC2
11
11
RS
12
12
R/W
13
13
E
22∼19
22∼19
DB7∼DB4
18∼14
18∼14
DB3∼DB0
23∼30
81∼74
81∼74
23∼30
COM1∼COM8
COM9∼COM16
33∼72
72∼33
SEG1∼SEG40
10
10
RESET
FUNCTION
Power Source (+5V)
Power Source ( 0V)
LCD Driving Power Source
Oscillation Frequency Adjust Terminals. Normally Open.
(Oscillation C and R are incorporated, OSC Freq.=270kHz)
For external clock operation, the clock should be input on OSC1.
Register selection signal input
“0” : Instruction Register (Writing)
Busy Flag (Reading)
“1” : Data Register (Writing/Reading)
Read/Write selection signal input
“0” : Write, “1” : Read
Read/Write activation signal input
3-state Data Bus (Upper) to transfer the data between MPU and
NJU6631A
DB7 is also used for the Busy flag reading.
3-state Data Bus (Lower) to transfer the data between MPU and
NJU6631A
These bus are not used in the 4-bit operation.
LCD Common driving signal Terminals
Common driver Location order Select as Shown in Table 4.
Pin configuration mode A : M0=0 / mode B : M0=1.
LCD Segment driving signal Terminals
Segment driver Location order Select as Shown in Table 4.
Pin configuration mode A : M0=0 / mode B : M0=1.
Reset Terminal. When the “L” level input over than 1.2ms to this
terminal the system will be reset. (fOSC=270kHz)
NJU6631A
■ FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Register
The NJU6631A incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores instruction codes such as “Clear Display” and “Return Home”, and address data for
Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the instruction
code and address data to the Register (IR), but it cannot read out from the Register (IR).
The Register (DR) is a temporary stored register, the data stored in the Register (DR) is written into the DD
RAM or CG RAM and read out from the DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred automatically to the DD RAM or CG RAM by
internal operation.
When the address data for the DD RAM or CG RAM is written into the Register (IR), the addressed data in
the DD RAM or CG RAM is transferred to the Register (DR). By the MPU read out the data in the Register
(DR), the data transmitting process is performed completely.
After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is
transferred automatically to the Register (DR) to provide for the next MPU reading.
These two registers are selected by the selection signal RS as shown below :
Table 1. shows register operation controlled by RS and R/W signals.
Table 1. Register Operation
RS
R/W
0
0
1
1
0
1
0
1
Selected Register
Operation
Write
Read busy flag (DB7) and address counter (DB0∼DB6)
Write (DR to DD RAM or CG RAM)
Read (DD RAM or CG RAM to DR)
IR
DR
(1-2) Busy Flag (BF)
When the internal circuits are in the operation mode, the busy flag is "1", and any instruction reading is
inhibited.
The busy flag (BF) is output at DB7 when RS="0" and R/W="1" as shown in table 1.
The next instruction should be written after busy flag (BF) goes to "0".
(1-3) Address Counter (AC)
The address Counter (AC) addressing the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is transferred
from Register (IR) to counter (AC). The selection of either the DD RAM or CG RAM is also determined by this
instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the Counter (AC)
increments (or decrements) automatically.
The address data in the Counter (AC) is output from DB6∼DB0 when RS="0" and R/W="1" as shown in Table
1.
(1-4) Display Data RAM (DD RAM)
The display data RAM (DD RAM) consists of 16 x 8 bits, stores up to 16-character display data represented
in 8-bit code.
The DD RAM address data set in the address Counter (AC) is represented in Hexadecimal.
Higher order bit
AC
AC6
AC5
AC4
Hexadecimal
Lower order bit
AC3
AC2
AC1
Hexadecimal
AC0
(Example) DD RAM address “08”
0
0
0
1
0
0
8
0
0
NJU6631A
(1-4-1) 16-character 1-line Display
The NJU6631A has two kinds of addressing mode called "Addressing mode 1" and "Addressing mode 2"
which is determined by the Function Set Instruction (A= 0 and 1).
"Addressing mode 1" is using consecutive address of (00)H through (0F)H for front half 8-character and last
half 8-character. "Addressing mode 2" is not using consecutive address likes as (00)H through (07)H and (40)H
through (47)H for front half 8-character and last half 8-character respectively.
16-character 1-line and 8 character 2-line are also determined by the Function Set Instruction (M1= 0 and 1).
<Addressing mode 1: A=0, M1=0>
-The relation between DD RAM address and display position on the LCD is shown below.
1
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
COM1∼COM8
11
0A
12
0B
13
0C
14
0D
15
0E
16
0F
←Display position
←DD RAM address
(Hexadecimal)
COM9∼COM16
When the display shift is performed, the DD RAM address changes as follows:
(00)←
01
02
03
04
05
06
(Left Shift Display)
07 08 09 0A
0B
0C
0D
0E
0F
00
0F
00
01
02
03
04
(Right Shift Display)
05 06 07 08
09
0A
0B
0C
0D
0E
→(0F)
<Addressing mode 2: A=1, M1=0>
-The relation between DD RAM address and display position on the LCD is shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
←Display position
00
01
02
03
04
05
06
07
40
41
42
43
44
45
46
47
←DD RAM address
(Hexadecimal)
COM1∼COM8
COM9∼COM16
When the display shift is performed, the DD RAM address changes as follows:
(00)←
01
02
03
04
05
06
(Left Shift Display)
07 40 41 42
43
44
45
46
47
00
47
00
01
02
03
04
(Right Shift Display)
05 06 07 40
41
42
43
44
45
46
→(47)
NJU6631A
(1-4-2) 8-character 2-line
<Addressing mode 1: A=0, M1=1>
-The relation between DD RAM address and display position on the LCD is shown below.
1
2
3
4
5
6
7
8
05
0D
06
0E
07
0F
←Display Position
COM1∼COM8
1st Line
2nd Line
00
08
01
09
02
0A
03
0B
04
0C
COM9∼COM16
←DD RAM Address
←
(Hexadecimal)
When the display shift is performed, the DD RAM address changes as follows:
1st Line(00)←
2nd Line(08)←
1st Line
2nd Line
01
09
02
0A
(Left Display Shift)
03 04 05 06
0B 0C 0D 0E
0F
07
00
08
(Right Display Shift)
01 02 03 04
09 0A 0B 0C
07
0F
08
00
05
0D
06
0E
→(07)
→(0F)
<Addressing mode 2: A=1, M1=1>
-The relation between DD RAM address and display position on the LCD is shown below.
1
2
3
4
5
6
7
8
← Display Position
05
45
06
46
07
47
←DD RAM Address
←
(Hexadecimal)
COM1∼COM8
1st Line
2nd Line
00
40
01
41
02
42
03
43
04
44
COM9∼COM16
When the display shift is performed, the DD RAM address changes as follows:
1st Line(00)←
2nd Line(40)←
1st Line
2nd Line
01
41
02
42
(Left Display Shift)
03 04 05 06
43 44 45 46
07
47
08
00
47
07
00
40
(Right Display Shift)
01 02 03 04
41 42 43 44
05
45
06
46
→(07)
→(47)
NJU6631A
(1-5) Character Generator ROM (CG ROM)
The Character Generator ROM (CG ROM) generates 5 x 8 dots character pattern represented in 8-bit
character codes.
The storage capacity is up to 240 kinds of 5 x 8 dots character pattern. The correspondence between
character code and standard character pattern of NJU6631A is shown in Table 2.
User-defined character pattern (Custom Font) are also available by mask option.
NJU6631A
Table 2. CG ROM Character Pattern (ROM version -02)
NJU6631A
(1-6) Character Generator RAM (CG RAM)
The character generator RAM (CG RAM) can store any kinds of character pattern in 5 x 7 dots written by
the user program to display user’s original character pattern. The CG RAM can store 4 kinds of character in 5
x 7 dots mode.
To display user’s original character pattern stored in the CG RAM, the address data (00)H ∼ (03)H should be
written to the DD RAM as shown in Table 2.
Table 3. shows the correspondence among the character pattern, CG RAM address and Data.
Table 3. Correspondence of CG RAM address, DD RAM character code
and CG RAM character pattern (5 x 7 dots).
Character Code
(DD RAM Data)
7 6 5 4 3 2 1 0
←
→
Upper bit
Lower bit
0 0 0 0 *
0 0 0 0 *
*
*
0 0
0 1
CG RAM Address
4 3 2 1 0
←
→
Upper bit Lower bit
0 0 0
0 0 1
0 1 0
0 1 1
0 0 1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
0 1 1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Character Pattern
(CG RAM Data)
4 3 2 1 0
→
←
Upper bit
Lower bit
1 1 1 1 0
1 0 0 0 1
1 0 0 0 1
1 1 1 1 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
0 0 0 0 0
1 0 0 0 1
0 1 0 1 0
1 1 1 1 1
0 0 1 0 0
1 1 1 1 1
0 0 1 0 0
0 0 1 0 0
0 0 0 0 0
Character Pattern
Example (1)
←Cursor Position
Character Pattern
Example (2)
←Cursor Position
* : Don’t Care
0 0 0 0 *
*
1 1
1 1
1
1
1
1
0
0
1
1
0
1
0
1
Notes : 1.Character code bits 0 to 1 correspond to the CG RAM address 3 and 4 (2 bits : 4 patterns)
2.CG RAM address 0, 1 and 2 designate character pattern Line position.
The 8th line is the cursor position and the display is performed by logical OR with cursor. Therefore,
in case of the cursor display, the 8th line should be "0". If there is "1" in the 8th line, the bit "1" is
always displayed on the cursor position regardless of cursor existence.
3.Character pattern row position correspond to the CG RAM data bits 0 to 4 are shown above.
The bits 5 to 7 of the CG RAM do not exist.
4.CG RAM character patterns are selected when character code bits 4 to 7 are all "0" and it is
addressed by character code bits 0 to 1. Therefore, the address (00)H, (04)H, (08)H and (0C)H, select
the same character pattern as shown in Table 2 and Table 3.
5."1" for CG RAM data corresponds to display On and "0" to display Off.
NJU6631A
(1-7) Timing Generator
The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal
circuits operation.
RAM read timing for the display and internal operation timing for MPU access are separately generated, so
that they may not interfere with each other.
Therefore, when the data write to the DD RAM for example, there will be no undesirable influence, such as
flickering, in areas other than the display area.
(1-8) LCD Driver
LCD driver circuits consist of 16-common driver and 40-segment driver.
The 40 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift
performed completely. This latched data controls display driver to output LCD driving waveform.
(1-9) Cursor Blinking Control Circuit
This circuits controls cursor On/Off and cursor position character blinks.
The cursor or blinks appear in the digit residing at the DD RAM address set in the address counter (AC).
When the address counter is (04)H, a cursor position is shown as follows :
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC
0
0
0
0
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
←Display Position
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
←DD RAM Address
(Hexadecimal)
Cursor Position
Note)The cursor or blinks appear when the address counter (AC) selects the CG RAM.
But the displayed the cursor and blink are meaningless.
If the AC storing the CG RAM address data, the cursor and blink are displayed in the meaningless
position.
NJU6631A
(2) Power on Initialization by internal circuits
(2-1) Initialization by Internal Reset circuits
The NJU6631A is automatically initialized by internal power on initialization circuits when the power is turned
on. In the internal power on initialization, following instructions are executed.
During the Internal power on initialization, the busy flag (BF) is "1" and this status is kept 10 ms after VDD
rises to 4.5V.
Initialization flow is shown below :
Clear Display
DL=1
A=0
M0=0
M1=0
: 8-bit long interface data
: Addressing mode 1
: Pin configuration mode A
: 16-Character 1-Line
Display On/Off
Control
D=0
C=0
B=0
: Display Off
: Cursor Off
: Cursor Blink Off
Entry Mode Set
I/D=1 : Increment by 1
S=0 : No Shift
Function Set
NOTE
If the condition of power supply rise
time described in the Electrical
Characteristics is not satisfied, the
internal Power On Initialization
Circuits will not operate and
initialization will not be performed.
In this case the initialization by MPU
software is required.
(2-2) Initialization by Hardware
The NJU6631A incorporates RESET terminal to initialize the all system. When the "L" level input over
1.2ms to the RESET terminal, reset sequence is executed. In this time, busy signal output during 10ms after
RESET terminal goes to "H".
- Reset Circuit
System Clock
RESET
C
Q
Counter
RST
S
R
Q
RS-F/F
Power On Reset
- Timing Chart
External Reset
Signal
Over than
1.2ms
Counter Output
RS-F/F Output
Internal Reset
Signal
Busy
10ms
System Reset
NJU6631A
(3) Instruction
The NJU6631A incorporates two registers, an Instruction Register (IR) and a Data Register (DR).
These two registers store control information temporarily to allow interface between NJU6631A and MPU or
peripheral ICs operating different cycles. The operation of NJU6631A is determined by this control signal from
MPU.
The control information includes register selection signals (RS), read/write signals (R/W) and data bus
signals (DB0 to DB7).
Table 4. shows each instruction and its operating time.
Note) The execution time mentioned in Table 4. based on fcp or fosc=270kHz.
If the oscillation frequency is changed, the execution time is also changed.
Table 4. Table of Instructions
Code
Instructions
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Maker Test
Description
Exec
Time
All “0” code is using for maker
testing.
Clear Display
Display clear and sets DD RAM
0 0 0 0 0 0 0 0 0 1 address 0 in AC.
1.52ms
Return Home
Sets DD RAM address 0 in AC and
returns display being shifted to
0 0 0 0 0 0 0 0 1
* original position.
37us
DD
RAM
contents
remain
unchanged.
Entry Mode Set
Sets cursor move direction and
specifies shift of display are
0 0 0 0 0 0 0 1 I/D S performed in data read/write.
37us
I/D=1:Increment, I/D=0:Decrement
S=1:Accompanies display shift.
Display On/Off
Sets of display On/Off(D), cursor
Control 0 0 0 0 0 0 1 D C B On/Off(C) and blink of cursor 37us
position character(B).
Cursor or
Moves cursor and shifts display
Display Shift
without changing DD RAM contents
S/C=1 : Display shift
0 0 0 0 0 1 S/C R/L *
* S/C=0 : Cursor shift
56us
R/L=1 : Shift to the right
R/L=0 : Shift to the left
Function Set
Sets interface data length(DL),
Display address mode(A).
DL=1 : 8 bits, DL=0 : 4 bits
A=0 : Addressing mode 1
0 0 0 0 1 DL A * M1 M0 A=1 : Addressing mode 2
37us
M1=0: 16-Character 1-Line
M1=1: 8-Character 2-Line
M0=0: Pin configuration mode A
M0=1: Pin configuration mode B
Sets CG RAM address. After this
Set CG RAM
instruction, the data is transferred 37us
address 0 0 0 1
*
ACG
on CG RAM.
Sets DD RAM address. After this
Set DD RAM
instruction, the data is transferred 37us
address 0 0 1
ADD
on DD RAM.
Reads busy flag and AC contents.
Read Busy Flag
ACDD
BF=1 : Internally operating
& Address 0 1 BF
0us
BF=0 : Can accept instruction
*
*
ACCG
Writes data into CG or DD RAMs.
Write Data to
Write Data(DD RAM)
37us
CG or DD RAM 1 0
*
*
* Write Data(CG RAM)
Reads data from CG or DD RAMs.
Read Data to
Read Data(DD RAM)
56us
CG or DD RAM 1 1
*
*
* Read Data(CG RAM)
Explanation of
DD RAM : Display data RAM, CG RAM : Character generator RAM
Abbreviation A : CG RAM address, A : DD RAM address, Corresponds to cursor address
CG
DD
AC : Address counter used for both of DD and CG RAMs
* = Don’t Care
0
0
0
0
0
0
0
0
0
0
NJU6631A
(3-1) Description of each instructions
(a) Maker Test
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
All "0" code in 4-bit length is using for device testing mode (only for maker).
Therefore, please avoid all "0" input or no meaning Enable signal input at data "0".
(Especially please pay attention the output condition of Enable signal when the power turns on.)
All "0" code in 8-bit length is usable for NOP (Not Operating instruction).
(b) Clear Display
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
1
Clear display instruction is executed when the code "1" is written into DB0. When this instruction is executed,
the space code (20)H is written into every DD RAM address, the DD RAM address 0 is set into the address
counter and entry mode is set increment. If the cursor or blink are displayed, they are returned to the left end
of the LCD.
The S of entry mode does not change.
Note: The character pattern for character code (20)H must be blank code in the user-defined character
pattern(Custom font).
(c) Return Home
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
*
* = Don’t Care
Return home instruction is executed when the code "1" is written into DB1. When this instruction is executed,
the DD RAM address 0 is set into the address counter. Display is returned its original position if shifted, the
cursor or blink are returned to the left end of the LCD, if the cursor or blink are on the display.
The DD RAM contents do not change.
(d) Entry Mode Set
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
1
DB1
I/D
DB0
S
Entry mode set instruction which sets the cursor moving direction and display shift On/Off, is executed when
the code "1" is written into DB2 and the codes of (I/D) and (S) are written into DB1(I/D) and DB0(S), as shown
below.
(I/D) sets the address increment or decrement, and the (S) sets the entire display shift in the DD RAM
writing.
I/D
1
0
S
1
0
Function
Address increment : The address of the DD or CG RAM increment (+1) when the
read/write, and the cursor or blink move to the right.
Address decrement : The address of the DD or CG RAM decrement (-1) when the
read/write, and the cursor or blink move to the left.
Function
Entire display shift.
The shift direction is determined by I/D : shift to the left at I/D=1 and shift to the right
at the I/D=0. The shift is operated only for the character, so that it looks as if the
cursor stands still and the display moves.
The display does not shift when reading from the DD RAM and writing/reading
into/from CG RAM.
The display does not shifting.
NJU6631A
(e)Display On/Off Control
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
D
DB1
C
DB0
B
Display On/Off control instruction which controls the display On/Off, the cursor On/Off and the cursor
position character blink, is executed when the code "1" is written into DB3 and the codes of (D), (C) and (B)
are written into DB2(D), DB1(C) and DB0(B), as shown below.
D
1
Function
Display On.
Display Off. In this mode, the display data remains in the DD RAM so that it is
retrieved immediately on the display when the D change to 1.
0
C
1
0
Function
Cursor On. The cursor is displayed by 5 dots on the 8th line.
Cursor Off. Even if the display data write, the I/D etc does not change.
B
Function
The cursor position character is blinking. Blinking rate is 303.4ms at or fOSC=270kHz.
The blink is displayed alternatively with all on (it means all black) and characters
display. The cursor and the blink can be displayed simultaneously.
The character does not blink.
1
0
□■■■□
■□□□■
■□□□□
■□■■■
■□□□■
■□□□■
□■■■■
□■■■□
■□□□■
■□□□■
■□□□■
■■■■■
■□□□■
■□□□■
■■■■■
■■■■■
■■■■■
■■■■■
■■■■■
■■■■■
■■■■■
■■■■■
↑
Cursor
Character Font 5 x 7 dots
(1) Cursor display example
□□□□□
■■■■■
Alternating display
(2) Blink display example
(f) Cursor / Display Shift
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
1
DB3
S/C
DB2
R/L
DB1
*
DB0
*
* = Don’t Care
The Cursor/Display shift instruction shifts the cursor position or display to the right or left without writing or
reading display data. This function is used to correct or search the display.
The contents of address counter (AC) does not change by operation of the display shift only.
This instruction is executed when the code "1" is written into DB4 and the codes of (S/C) and (R/L) are
written into DB3(S/C) and DB2(R/L), as shown below.
S/C
0
0
1
1
R/L
0
1
0
1
Function
Shifts the cursor position to the left. ((AC) is decremented by 1)
Shifts the cursor position to the right. ((AC) is incremented by 1)
Shifts the entire display to the left and the cursor follows it.
Shifts the entire display to the right and the cursor follows it.
NJU6631A
(g) Function Set
Code
RS
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
DL
DB3
A
DB2
*
DB1
M1
DB0
M0
* = Don’t Care
Function set instruction which sets the interface data length, the addressing Mode for the DD RAM, 1-line or
2-line display, and Pin configuration mode, is executed when the code "1" is written into DB5 and the codes of
(DL), (A), (M1) and (M0) are written into DB4(DL), DB3(A), DB1(M1) and DB0(M0), as shown below (character
font is fixed 5 x 7 dots).
(DL) sets the interface data length, (A) sets the DD RAM address mode (00)H through (0F)H or (00)H through
(07)H and (40)H through (47)H, (M1) sets the number of display line either the 1-line or 2-line display, and (M0)
sets the Pin configuration for Common and Segment drivers as shown in coordinates.
NOTE
This function set instruction must be performed at the head of the program prior to all other
existing instructions (except Busy flag/Address read). This function set instruction can not be
executed afterwards unless the interface data length change.
DL
1
Function
Set the interface data length to 8 bits (DB7 to DB0).
Set the interface data length to 4 bits (DB7 to DB4).
The data must be sent or received twice.
0
A
0
1
Function
Set the Addressing Mode 1 for the DD RAM.
Set the Addressing Mode 2 for the DD RAM.
M1
0
1
Set the 16-Character 1-Line Display.
Set the 8-Character 2-Line Display.
Function
M0
0
1
Function
Set the Pin configuration mode A for Common and Segment Driver.
Set the Pin configuration mode B for Common and Segment Driver.
Refer to
coordinates
(h) Set CG RAM Address
Code
RS
0
R/W
0
DB7 DB6 DB5 DB4
0
1
*
A
Higher order bit
DB3
A
DB2 DB1 DB0
A
A
A
Lower order bit
* = Don’t Care
Set CG RAM address instruction is executed when the code "1" is written into DB6 and the address is
written into DB4 to DB0 as shown above.
The address data mentioned by binary code "AAAAA" is written into the address counter (AC) together with
the CG RAM addressing condition. After this instruction execution, the data writing/reading is performed
into/from the CG RAM.
(i) Set DD RAM Address
Code
RS
0
R/W
0
DB7 DB6 DB5 DB4
1
A
A
A
Higher order bit
DB3
A
DB2 DB1 DB0
A
A
A
Lower order bit
Set DD RAM address instruction is executed when the code "1" is written into DB7 and the address is written
into DB6 to DB0 as shown above.
The address data mentioned by binary code "AAAAAAA" is written into the address counter (AC) together
with the DD RAM addressing condition. After this instruction, the data writing/reading is performed into/from
the DD RAM.
Note : When the "Addressing mode 1" selection, (00)H through (0F)H are available but (10)H through (7F)H are
ignored. When the "Addressing mode 2" selection, (00)H through (07)H and (40)H through (47)H are
available but (08)H through (3F)H and (48)H through (7F)H are ignored.
NJU6631A
(j) Read Busy Flag & Address
Code
RS
0
R/W
1
DB7 DB6 DB5 DB4
BF
A
A
A
Higher order bit
DB3
A
DB2 DB1 DB0
A
A
A
Lower order bit
This instruction reads out the internal status of the NJU6631A. When this instruction is executed, the busy
flag (BF) which indicate internal operation is read out from DB7 and the address of CG RAM or DD RAM is
read out from DB6 to DB0 (the address for CG RAM or DD RAM is determined by the previous instruction).
(BF)=1 indicates that internal operation is in progress. The next instruction is inhibited when (BF)=1.
Check the (BF) status before the next write operation.
(k) Write Data to CG or DD RAM
Code
RS
1
R/W
0
DB7 DB6 DB5 DB4
D
D
D
D
Higher order bit
DB3
D
DB2 DB1 DB0
D
D
D
Lower order bit
(DD RAM)
Code
RS
1
R/W
0
DB7 DB6 DB5 DB4
*
*
*
D
Higher order bit
DB3
D
DB2 DB1 DB0
D
D
D
Lower order bit
(CG RAM)
Write Data to CG RAM or DD RAM instruction is executed when the code "1" is written into (RS) and code
"0" is written into (R/W).
By the execution of this instruction, the binary 5-bit data "DDDDD" are written into the CG RAM, and the
binary 8-bit data "DDDDDDDD" are written into the DD RAM. The selection of the CG RAM or DD RAM is
determined by the previous instruction.
After this instruction execution, the address increment (+1) or decrement (-1) performed automatically
according to the entry mode set. And the display shift is also executed according to the previous entry mode
set.
(l) Read Data from CG or DD RAM
Code
RS
1
R/W
1
DB7 DB6 DB5 DB4
D
D
D
D
Higher order bit
DB3
D
DB2 DB1 DB0
D
D
D
Lower order bit
(DD RAM)
Code
RS
1
R/W
1
DB7 DB6 DB5 DB4
*
*
*
D
Higher order bit
DB3
D
DB2 DB1 DB0
D
D
D
Lower order bit
(CG RAM)
Read Data from CG RAM or DD RAM instruction is executed when the code "1" is written into (RS) and
(R/W).
By the execution of this instruction, the binary 5 bit data "DDDDD" are read out from CG RAM, and the
binary 8 bit data "DDDDDDDD" are read out from DD RAM. The selection of the CG RAM or DD RAM is
determined by the previous instruction.
Before executing this instruction, either the CG RAM address set or DD RAM address set must be executed,
otherwise the first read out data are invalidated.
When this instruction is serially executed, the next address data is normally read from the second read.
The address set instruction is not required if the cursor shift instruction is executed just beforehand (only DD
RAM reading).
The cursor shift instruction has same function as the DD RAM address set, so that after reading the DD
RAM, the address increment or decrement is executed automatically according to the entry mode.
But display shift does not occur regardless of the entry mode.
Note : The address counter(AC) is automatically incremented or decremented by 1 after write instructions to
either of the CG RAM or DD RAM. Even if the read instruction is executed after this instruction, the
addressed data can not be read out correctly. For a correct data read out, either the address set
instruction or cursor shift instruction (only with DD RAM) must be implemented just before this
instruction or from the second time read out instruction execution if the read out instruction is
executed 2 times consecutively.
NJU6631A
(3-2) Initialization using the internal reset circuits
(a) 16-character 1-line in 8-bit operation Addressing Mode 1 (Using internal reset circuits).
At the 16-character 1-line display, the Function set, Display On/Off Control and Entry Set Instruction must be
executed before the data input, as shown below.
Since the display shift operation changes only display position and the DD RAM contents remain unchanged,
display data which are entered first can be output when the return home operation is performed.
Initialized.
No display appears.
Power On
↓
Function Set
Set
0
8-bit operation, 161-line display, Pin
configuration mode A, Addressing
Mode 1.
0
0
0
0
1
1
0
*
0
0
Turns on display and cursor.
Entire display is in space
mode by the initialization.
↓
Disp. On/Off Control
0
0
0
0
0
0
1
1
1
↓
Entry Mode Set
the
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Character
0
0
0
0
0
0
0
1
1
0
↓
Example for set address
increment and cursor right
shift when the data write to
the DD or CG RAM.
Write data to the DD/CG RAM and set
the Instruction
(b) 8-character 2-line in 4-bit operation Addressing Mode 2 (Using internal reset circuits).
In the 4-bit operation, the function set must be performed by the user programming.
When the power is turned on, 8-bit operation is selected automatically, therefore the first input is performed
under 8-bit operation. In this operation, full instruction can not input because of terminals DB0 to DB3 are no
connection. Therefore, same instruction must be rewritten on the RS, R/W and DB7 to DB4, as shown below.
Since one operation is completed by the two accesses in the 4-bit operation mode, rewrite is required to set
the instruction code in full. 8-character 2-line in 4-bit operation is shown as follows:
Initialized.
No display appears.
Power On
↓
Function Set
RS R/W DB7 DB6 DB5 DB4 Set the 4-bit operation.
0
0
0
0
1
0 This step is executed in 8-bit mode set by the initialization.
↓
Function Set
↓
Disp. On/Off Control
↓
Entry Mode Set
↓
Set the 4-bit operation / 2-line 8-Character
display / Pin configuration mode B / Addressing
Mode 2. The 4-bitoperation starts from this step.
0
0
0
0
0
1
0
*
1
1
0
1
0
0
0
0
0
1
0
1
0
1
0
0
Turn on display and cursor.
Entire display is in space mode by the
initialization.
0
0
0
0
0
0
0
1
0
1
0
0
Example for set address increment and cursor
right shift when the data write to the DD or CG
RAM.
Write data to the DD/CG RAM and set
the Instruction
NJU6631A
(3-3) Initialization by instruction
If the power supply conditions for the correct operation of the internal reset circuits are not met, the
NJU6631A must be initialized by the instruction.
(a) Initialization by Instruction in 8-bit interface
Initialized.
No display appears.
Power On
↓
Wait more than 15ms
after VDD rises to 4.5V
↓
Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set
0
0
0
0
1
1
*
*
*
*
(8-bit interface length)
↓
Wait more than 4.1ms
↓
Function Set
0
0
0
0
1
1
*
*
*
*
Function Set
(8-bit interface length)
↓
Wait more than 100us
↓
Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set
(8-bit interface length)
0
0
0
0
1
1
*
*
*
*
Busy Flag(BF) can not be
checked before this step, but
it can be checked after this
step.
After this step, busy flag(BF)
check or longer waiting
time than each instruction
execution time is required.
↓
Function Set
↓
Display Off
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set the 8-bit operation, 161-Line,
Pin
0
0
0
0
1
1
1
*
0
0 Character
Configuration
mode
A,
Addressing Mode 2.
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
Display Clear
↓
Entry Mode Set
0
0
0
↓
Write data to the DD/CG RAM and set
the Instruction
0
0
0
0
1
1
0
Example for set address
increment and cursor right
shift when the data write to
the DD or CG RAM.
NJU6631A
(b) Initialization by Instruction in 4-bit interface
Initialized.
No display appears.
Power On
↓
Wait more than 15ms
after VDD rises to 4.5V
↓
Function Set
RS R/W DB7 DB6 DB5 DB4 Function Set
0
0
0
0
1
1 (8-bit interface length)
↓
Wait more than 4.1ms
↓
Function Set
0
0
0
0
1
1
Function Set
(8-bit interface length)
0
0
0
0
1
1
Function Set
(8-bit interface length)
↓
Wait more than 100us
↓
Function Set
Busy Flag (BF) can not be checked before this
step, but it can be checked after this step.
After this step, busy flag (BF) check or longer
waiting time than each instruction execution
time is required.
↓
0
0
0
0
1
1
Function Set in 8-bit interface length.
(Set 4-bit interface length)
↓
0
0
0
0
0
0
0
*
1
0
0
0
Set the 4-bit operation, 16-Character 1-Line, Pin
Configuration mode A, Addressing Mode 1.
Display Off
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
Function Set
↓
Display Clear
↓
Entry Mode Set
↓
Write data to the DD/CG RAM and set
the Instruction
Example for set address increment and cursor
right shift when the data write to the DD or CG
RAM.
NJU6631A
(4) LCD Display
(4-1) Power Supply for LCD Driving
NJU6631A incorporates bleeder resistance to generate the LCD display driving waveform.
The bleeder resistance is set 1/5 bias suitable for 1/18 duty ratio and 1.5kΩ per resistance.
Furthermore, the bias level can be changed by connecting external resistance between the V2, V3 terminals,
if needed.
Table 5. LCD Driving Voltage vs Duty Ratio
Duty Ratio
1/16
Bias
1/5
Power
V2
VDD-2/5VLCD
Supply
V3
VDD-3/5VLCD
VDD-VLCD
V5
VDD
VDD
R1
V1
R1
V2
V2
R1
VLCD
V3
V3
R1
V4
R1
V5
V5
NJU6631A internal
Note) Power ON or power OFF is in the following order.
Power ON
: V5 should be turned on after the VDD turned on or at the same time.
Power OFF
: V5 should be turned off before the VDD turned off or at the same time.
(4-2) Relation between oscillation frequency and LCD frame frequency.
LCD frame frequency example mentioned below is based on 270kHz oscillation.
The clock for the LCD Driving is using 270kHz (1 clock=3.7us).
1/16 Duty
40 clock
1
2
3
4
16
1
2
3
4
VDD
V1
V2
V3
V4
V5
1 frame
1 frame
1 frame=3.7(us)x40x16x4=9,472(ms)
Frame frequency=1/9,472(ms)=105.6(Hz)
16
1
2
3
NJU6631A
■ Interface with MPU
NJU6631A can be interfaced with both of 4/8 bit MPU and the two-time 4-bit or one-time 8-bit data transfer
is available.
(1) When the interface length is 4-bit, the data transfer is performed by 4 lines connected to DB4 to DB7
(DB0 to DB3 are not used). The data transfer with the MPU is completed by the two-time 4-bit data
transfer.
The data transfer is executed in the sequence of upper 4-bit (the data DB4 to DB7 at 8-bit length) and
lower 4-bit (the data DB0 to DB3 at 8-bit length).
The busy flag check must be executed after two-time 4-bit data transfer (1 instruction execution). In
this case the data of busy flag and address counter are also output twice.
RS
R/W
E
Operation
Internal Status
DB7
IR7
IR3
Bus
Instruction
writing
AC3
Busy Flag
Check
No
Bus
AC3
Busy Flag
Check
D7
D3
Instruction
writing
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
Writing Instruction into Read out Busy Flag (BF)
Read out data Register (DR)
instruction Register (IR) and Address counter (AC)
NJU6631A
(2) 8-bit MPU interface
RS
R/W
E
Operation
Internal Status
DB7
Data
Writing Instruction into
instruction Register (IR)
Bus
Busy Flag
Check
Bus
Busy Flag
Check
No
Bus
Busy Flag
Check
Data
Writing Instruction into
instruction Register (IR)
NJU6631A
■ ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
(Ta=25°C)
UNIT
RATINGS
Supply Voltage
VDD
-0.3 ~ +7.0
V
Input Voltage
VIN
-0.3 ~ VDD + 0.3
V
Operating Temperature
Topr
-30 ~ +80
°C
Storage Temperature
Tstg
-55 ~ +125
°C
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed.
Using the LSI within electrical characteristics is strongly recommended for normal operation. Use
beyond the electric characteristics conditions will cause malfunction and poor reliability.
Note 2) All voltage values are specified as VSS=0V.
Note 3) The relation : VDD>V5≥V5OUT, VSS=0V must be maintained.
Turn on VDD first then turn on V5 must be required.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for
the LSI.
■ ELECTRICAL CHARACTERISTICS
Parameter
Operating Voltage
Symbol
VDD
1
VIH1
VIL1
Input Voltage
2
3
Output Voltage
Driver On-resist.(COM)
Driver On-resist.(SEG)
Input Leakage Current
Pull-up Resist. Current
Operating Current
LCD Driving Voltage
VIH2
VIL2
VIH3
VIL3
VOH
VOL
RCOM
RSEG
ILI
-Ip
IDD
V2
V3
Conditions
(VDD=5.0V±10%, VSS=0V, Ta= -20~75°C)
MIN
TYP
MAX
Unit Note
4.5
5.0
5.5
V
All Input/Output Terminals
2.3
except
OSC
and
E
Terminals
Only OSC Terminal
VDD-1.0
Only E Terminal
0.8VDD
-IOH=0.205mA
2.4
IOL=1.6mA
±Id=50uA(All COM term.)
±Id=50uA(All SEG term.)
VIN=0cVDD
-1
VDD=5V
50
CR Oscillation
VDD=5V, fOSC=270kHz
Ta=25°C, VDD=5V, V5=0V
2.7
Measurement Terminal is
1.7
SEG.
-
VDD
-
0.8
125
VDD
1.0
VDD
0.2VDD
0.4
20
30
1
250
1.0
1.8
3.0
3.3
2.0
2.3
6.65
9.5
12.35
kΩ
135
VDD-3
270
-
405
VDD-5
KHz
V
V
5
V
6
kΩ
kΩ
uA
uA
9
9
7
mA
8
V
VDD-V5=5V
Ta=25°C
Bleeder Resistance
Oscillation Frequency
LCD Driving Voltage
RB
fOSC
VLCD
VDD=5V, Ta=25°C
V5 Terminal, VDD=5V
10
NJU6631A
Note 5) Input / Output structure except LCD driver are shown below :
-Input Terminal Structure
E Terminal
RS, R/W, RESET Terminals
VDD
VSS
PMOS
VDD
VDD
PMOS
PMOS
NMOS
NMOS
VSS
VSS
-Input / Output Terminal Structure
DB0 ~ DB7
VDD
PMOS
VDD
PMOS
NMOS
VDD
PMOS
ENABLE
NMOS
DATA
Note 6) Apply to the Input / Output Terminal.
Note 7) Except pull-up resistance current and output driver current.
Note 8) Except Input/output current but including the current flow on bleeder resistance.
Note 9) RCOM and RSEG are the resistance values between power supply terminals(VDD,V2,V3,V5) and each
common terminal (COM1~COM16), and supply voltage (VDD,V2,V3,V5) and each segment terminal
(SEG1~SEG40) respectively, and measured when the current Id is flown on every common and
segment terminals at a same time.
Note 10) Apply to the output voltage from each COM and SEG are less than ±0.15V against the LCD
Driving constant voltage(VDD, V5) at no load condition.
-Bleeder Resistance
VDD
R1
V1
R1
V2
V2
R1
V3
V3
R1
V4
R1
V5
V5
NJU6631A internal
NJU6631A
■ Bus timing characteristics
-Write operation sequence (Write from MPU to NJU6631A)
(VDD=5.0V±10%, VSS=0V, Ta=-20~75°C)
SYMBOL
MIN.
MAX.
CONDITION UNIT
tCYCE
500
ns
PW EH
220
ns
280
ns
PW EL
tEr, tEf
20
ns
fig.1
tAS
40
ns
tAH
10
ns
tDSW
60
ns
tH
10
ns
PARAMETER
Enable Cycle Time
Enable Pulse
“High” level
Width “Low” level
Enable Rise Time, Fall Time
Set up Time
RS, R/W-E
Address Hold Time
Data Set up Time
Data Hold Time
Timing Characteristics (Write operation)
RS
VIH1
VIH1
VIL1
VIL1
tAS
R/W
tAM
VIL1
VIL1
tAM
PW EH
tEf
E
VIH3
VIL3
tEr
DB0∼DB7
VIH3
PW EL
VIL3
tDSW
VIH1
VIL1
Valid Data
tH
VIH1
VIL1
tCYCE
fig. 1 The timing characteristics of the bus write operating sequence.
(Write from MPU to NJU6631A)
VIL3
NJU6631A
-Read operation sequence (Read from NJU6631A to MPU)
PARAMETER
Enable Cycle Time
Enable Pulse
“High” level
Width “Low” level
Enable Rise Time, Fall Time
Set up Time
RS, R/W-E
Address Hold Time
Data Delay Time
Data Hold Time
SYMBOL
tCYCE
PW EH
PW EL
tEr, tEf
tAS
tAH
tDDR
tDHR
(VDD=5.0V±10%, VSS=0V, Ta=-20~75°C)
MIN.
MAX.
CONDITION UNIT
500
ns
220
ns
280
ns
20
ns
fig.2
40
ns
10
ns
240
ns
20
ns
-DB0~DB7 Load Condition : CL=100pF
Timing Characteristics (Read operation)
RS
VIH1
VIH1
VIL1
VIL1
tAM
tAS
R/W
VIH1
VIH1
PW EH
tAM
tEf
E
VIH3
VIL3
tEr
DB0∼DB7
VIH3
PW EL
VIL3
tDDR
tDHR
VOH1
VOL1
Valid Data
VOH1
VOL1
tCYCE
fig. 2 The timing characteristics of the bus read operating sequence.
(Read from NJU6631A to MPU)
VIL3
NJU6631A
-The Input Condition when using the Hardware Reset Circuit
PARAMETER
SYMBOL
CONDITION
Reset Input ”L” Level Width
tRSL
fOSC=270kHz
MIN.
1.2
TYP.
-
MAX.
-
UNIT
ms
Input Timing
tRSL
RESET
fig. 3 The timing characteristics of the Hardware Reset input
Power supply condition when using the internal initialization circuit
PARAMETER
SYMBOL
CONDITION
MIN
Power supply rise time
trDD
–
0.1
Power supply OFF time
tOFF
–
1
•
0.2
trDD
0.1ms ! trDD ! 10ms
(Ta=-20 to 75°C)
MAX
UNIT
5
ms
–
ms
3V
4.5
VDD
TYP
–
–
0.2
tOFF
*tOFF specifies the power OFF
time in a short period OFF or
cyclical ON/OFF
tOFF ≤ 1ms
Note.) Since the internal initialization circuits will not operate normally unless the above conditions are met, in
such a case initialize by instruction(Refer to initialization by the instruction).
NJU6631A
■ LCD DRIVING WAVEFORM
VDD
COM1
COM2
V1
COM3
V2
COM4
COM1
V3
COM5
V4
COM6
V5
COM7
COM8
VDD
V1
V2
COM9
COM2
V3
COM10
V4
COM11
V5
COM12
COM13
COM14
COM15
VDD
COM16
V1
COM16
V2
V3
V4
V5
VDD
V1
V2
SEG1
V3
V4
V5
VDD
V1
SEG2
V2
V3
V4
V5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NJU6631A
■ APPLICATION CIRCUITS
(1) LCD display interface Pin configuration mode A (BOTTOM VIEW)
SEG1
20
40
21
LCD Panel
(16-character 1-line)
SEG1
SEG20
20
21
SEG21
40
SEG40
COM16
COM8
NJU6631A
BOTTOM VIEW
COM9
COM1
Mode A, 16-character 1-line display example (M0=0, M1=0)
LCD Panel
(8-character 2-line)
SEG1
SEG20
SEG21
SEG40
COM16
COM8
NJU6631A
BOTTOM VIEW
COM1
COM9
Mode A, 8-character 2-line display example (M0=0, M1=1)
1
NJU6631A
■ APPLICATION CIRCUITS
(2) LCD display interface Pin configuration mode B (TOP VIEW)
SEG1
20
40
21
LCD Panel
(16-character 1-line)
SEG1
SEG20
20
21
SEG21
40
SEG40
COM16
COM8
NJU6631A
TOP VIEW
COM9
COM1
Mode B, 16-character 1-line display example (M0=1, M1=0)
LCD Panel
(8-character 2-line)
SEG1
SEG20
SEG21
SEG40
COM16
COM8
NJU6631A
TOP VIEW
COM1
COM9
Mode B, 8-character 2-line display example (M0=1, M1=1)
1
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.