NJU3430 16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER n GENERAL DESCRIPTION n PACKAGE OUTLINE The NJU3430 is a Dot Matrix VFD (Vacuum Fluorescent Display) Controller Driver for 16-character 1-line with Icon display. It contains character generator ROM/RAM, address counter, oscillation circuit, command register, Icon display RAM, high voltage drivers, and serial interface circuit. The display data or the command data is transmitted with the serial interface circuits. NJU3430FG1 The character generator consists of 8,400 bits ROM and 35 x 8 bits RAM. The CG RAM stores 8 kinds of character by 5 x 7dots maximum. The 16-common and 37-segment (35 for character, 2 for icon) drivers operated up to 45V drive the display of 16-character 1-line with 32Icon. Furthermore, the NJU3430 incorporates one Output port which drives the LED. n FEATURES l 16-character 1-line Dot Matrix VFD Controller Driver l Serial Interface with Microprocessor l Display Data RAM 16 x 8 bits : 16-character 1-line Display l Character Generator ROM 8,400 bits : 240 Characters for 5 x 7 Dots l Character Generator RAM 35 x 8 bits : 8 Patterns (5 x 7 Dots) l Icon Display RAM 16 x 2 bits : Maximum 32 Icon | VDD-V FDP | ≤ 45V l VFD Driving Voltage Timing Signal : 16 Segment Signal : 35 (Except for Icon Segment Signal) l Output Port for LED : 1 l Display ON/OFF Function l Digit Scan Function l Display Duty (Contrast Control) : 8-step (8/16 to 15/16) l Character / Icon Shift Function l Display Mode (9 to 16 Digits) l Oscillation Circuit on-chip (External Resistor and Capacitor Required) l Operating Voltage 3.0V to 5.5V (Except VFD Driving Voltage) l Package Outline QFP 64 l C-MOS Technology Jul. 2003 Ver. 3 NJU3430 48 V SS T2 T5 T4 T3 T6 T8 T7 T9 T11 T10 T12 T15 T14 T13 V F DP T 16 n PIN CONFIGURATION 33 32 49 T1 O SC 1 S 35 O SC 2 S 34 R ST S 33 C S S 32 CLK S 31 SI S 30 R S S 29 N J U 3 4 3 0 VDD S 28 P1 M K2 S 27 S 26 M K1 S 25 S1 S 24 S2 S 23 S3 S 22 17 64 S 21 S17 S18 S19 S16 S14 S15 S11 S12 S13 S10 S7 S8 S9 16 S6 S5 1 S20 S4 n BLOCK DIAGRAM RST RESET Instruction MK RAM Decoder SI CS Icon 16x2bit Driver MK1∼MK2 8bits Line Shift CLK Address Counter Reg. RS CG RAM Segment 35x8bit Driver Port Driver Timing Gen. State Address Reg. Selector S1∼S35 P1 CG ROM 8,400bit Read OSC1 CR OSC. OSC2 Display Control Address Counter DD RAM 16x8bit VDD VSS VFDP Timing Driver T1∼T16 NJU3430 n TERMINAL DESCRIPTION No. SYMBOL I/O F U N C T I O N 57 VDD - Power Source : VD D =+3.0 to 5.5V 49 V SS - GND : VSS =0V 48 VFDP - VFD Driving Power Sourse V D D -20V to V D D -45V 50 OSC1 I 51 OSC2 O 54 CLK I Serial Clock Input Terminal The serial data input synchronizing the rise edge of this terminal. 53 CS I Chip Select Terminal When the CS terminal is "H" the serial data input is not available. 55 SI I Serial Data Input Terminal The data input is MSB first. 56 RS I Register Selection Signal Input Terminal RS="0" : Instruction Register RS="1" : Data Register CR Oscillation Terminal External R and C connect to these terminals. (Target f O S C = 3 6 0 k H z ) Reset Terminal RST="L" : Reset -Each Address -Each RAM Data -Display Digits -Contrast Control -All Display Off -All Outputs are "L" : : : : (00)H Unfixed 16-digit 8/16 Dury 52 RST I 61 to 64, 1 to 31 S 1 to S 3 5 O Segment Output Terminals (Internal Pull-down Resistance) 32 to 47 T 1 to T 1 6 O Timing Output Terminals (Internal Pull-down Resistance) 60 59 MK 1 MK 2 O Icon Output Terminals (Internal Pull-down Resistance) 58 P1 O Output Port Terminal This terminal is suitable for LED. NJU3430 n FUNCTION DESCRIPTION (1)CG RAM data and Character Dot Matrix The character generator RAM (CG RAM) stores any kinds of character pattern by 5 x 7 dots written by the user program to display user’s original character pattern. The CG RAM stores 8 kinds of character by 5 x 7 dots maximum. To display user’s original character pattern stored in the CG RAM, the address data (00)H - (07) should be written to the DD RAM as shown in Table 2. Table 1.Correspondence of CG RAM address, DD RAM character code and CG RAM character pattern(5 x 7 dots). Character Code (DD RAM Data) (00) H (01) H AC5 0 0 : : : (07) H Correspondence of CG RAM Data and SEG Terminal CG RAM Address AC4 0 AC3 0 0 1 AC2 AC1 AC0 SC4 SC3 SC2 SC1 SC0 0 0 0 S1 S2 S3 S4 S5 0 0 1 S6 S7 S8 S9 S 10 0 1 0 S 11 S 12 S 13 S 14 S 15 0 1 1 S 16 S 17 S 18 S 19 S 20 1 0 0 S 21 S 22 S 23 S 24 S 25 1 0 1 S 26 S 27 S 28 S 29 S 30 1 1 0 S 31 S 32 S 33 S 34 S 35 1 1 1 0 0 0 S1 S2 S3 S4 S5 0 0 1 S6 S7 S8 S9 S 10 0 1 0 S 11 S 12 S 13 S 14 S 15 0 1 1 S 16 S 17 S 18 S 19 S 20 1 0 0 S 21 S 22 S 23 S 24 S 25 1 0 1 S 26 S 27 S 28 S 29 S 30 1 1 0 S 31 S 32 S 33 S 34 S 35 1 1 1 : : : 1 Invalid Address Invalid Address : : : 1 1 : : : 0 0 0 S1 S2 S3 S4 S5 0 0 1 S6 S7 S8 S9 S 10 0 1 0 S 11 S 12 S 13 S 14 S 15 0 1 1 S 16 S 17 S 18 S 19 S 20 1 0 0 S 21 S 22 S 23 S 24 S 25 1 0 1 S 26 S 27 S 28 S 29 S 30 1 1 0 S 31 S 32 S 33 S 34 S 35 1 1 1 Invalid Address * When the data is written to CG RAM successively, the invalid address is skipped automatically. (Ex.)CG RAM Address : (06)H CG RAM Address : (08)H After data writing operation NJU3430 Table 2.CG ROM Character Pattern (ROM version -02) NJU3430 (2)Reset Function (2-1)Initialization by Reset Terminal The NJU3430 incorporates RST terminal to initialize the all system. When the "L" level is input over 1us to the RST terminal, the reset sequence is executed. The Initialization flow is shown below : Each RAM Address --- (00)H Each RAM Data --- Unfixed Output Port --- "L" Level (V SS) Display Digits --- 16-digit Contrast Control --- 8/16 Duty All Display ON/OFF --- All Display OFF (2-2)Initialization (After the Reset) Reset ↓ Display Digits Set ← (Initialization : 16-digit) ↓ Contrast Control Set ← (Initialization : 8/16 Duty) ↓ DD RAM Address Set → Data Writing ↓ CG RAM Address Set → Data Writing ↓ MK RAM Address Set → Data Writing ↓ Output Port Set ↓ All Display Off ← Data set should be executed because the data in DD RAM is unfixed. ← Data set should be executed because the data in CG RAM is unfixed. ← Data set should be executed because the data in MK RAM is unfixed. ← (Initialization : All “Low” level) NJU3430 (3)Instruction Each instruction is shown in the Table 3. The data should be written to the RAM continuously after the RAM address set. The order of data writing is MSB first. Table 3. Table of Instruction MSB Serial Data LSB INSTRUCTION DESCRIPTION RS B7 B6 B5 B4 B3 B2 B1 B0 Maker Test 0 0 0 0 0 0 0 0 0 Output Port Set 0 0 0 0 0 0 0 1 P1 Output Port Control Display On/Off 0 0 0 0 0 0 1 M D Display Duty Set 0 0 0 0 0 1 D2 D1 Display Shift 0 0 0 0 1 0 LR M D Set the Display Shift (Character and Icon) Display Blink Set 0 0 0 1 B2 B1 B0 M D Set the Blink Interval (Character and Icon) Display Digits Set 0 0 1 0 0 0 C2 C1 0 0 0 AD3 AD2 0 0 1 AM3 RAM Address Set 0 1 1 Write Data to RAM 1 AM2 D0 Set the Contrast Control C0 Set the Display Digits (9 to 16 degits) Set the RAM Address (AD0 to AD3 : DD RAM) (AM0 to AM3 : MK RAM) AM1 AM0 (AC0 to AC5 : CG RAM) AD1 AD0 AC5 AC4 AC3 AC2 AC1 AC0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 0 0 0 0 0 0 SC4 SC3 SC2 Set the Display On/Off (Character and Icon) After the RAM Address Set, the data should be written to RAM (SD0 to SD7 : DD RAM) SM1 SM0 (SM0 to SM1 : MK RAM) (SC0 to SC4 : CG RAM) SC1 SC0 *Instruction is executed within 32uS from the rise edge of the Chip Select CS Signal. (at fOSC=250kHz) NJU3430 (3-1)Description of each Instruction (a)Maker Testing R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 0 0 0 0 0 0 R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 0 0 0 0 1 P 1 Set the test mode. (b)Output Port Set Set the Output Port (1 bit static operation)."P1" is Output Port name. *P1 does not drive VFD. P 1 F U N C T I O N 0 "L" level is output. 1 "H" level is output. (c)Display On/Off R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 0 0 0 1 M D Set the Display On/Off (Character and Icon). All Display are Off after Reset. M D F U N C T I O N 0 0 Icon Display "Off", Character Display "Off" 0 1 I c o n D i s p l a y " O f f " , C h a r a c t e r D i s p l a y " O n " 1 0 Icon Display "On", Character 1 1 I c o n D i s p l a y " O n " , C h a r a c t e r Display "Off" D i s p l a y " O n " (d)Display Duty Set R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 0 0 1 D 2 D 1 D 0 One duty is selected from among eight kinds of duty by Display Duty Set. 8/16 Duty (lowest contrast) is set after reset, an optional duty should be selected before display operation. B2 B1 B0 Duty 0 0 0 8/16 0 0 1 9/16 : : : : 1 1 0 14/16 1 1 1 15/16 NJU3430 (e)Display Shift R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 0 1 0 LR M D The display positions of Character and Icon are shifted by Display Shift instruction. When the codes of "LR", "M" and "D" mentioned below are written into "B2", "B1" and "B0", the display positions are shifted individually. L R F U N C T I 0 Shift the display position to the right. 1 Shift the display position to the left. M F U N C T I O N O N 0 The shift operation is not available. 1 The shift oparation is selected for Icon. D F U N C T I O N 0 The shift operation is not available. 1 The shift oparation is selected for Character. 16-digit Display Example [Input Data] 1-digit [Correspondence of DD RAM, MK RAM Address and Display] 8-digit 16-digit 00010001 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ← MK RAM (DD RAM right shift) 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E ← DD RAM 00010010 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E ← MK RAM (MK RAM right shift) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ← DD RAM 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E ← MK RAM 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E ← DD RAM 00010011 (DD,MK RAM right shift) 9-digit Display Example [Input Data] 1-digit [Correspondence of DD RAM, MK RAM Address and Display] 8-digit 00010001 00 01 02 03 04 05 06 07 08 ← MK RAM (DD RAM right shift) 0F 00 01 02 03 04 05 06 07 ← DD RAM 00010010 0F 00 01 02 03 04 05 06 07 ← MK RAM (MK RAM right shift) 00 01 02 03 04 05 06 07 08 ← DD RAM 0F 00 01 02 03 04 05 06 07 ← MK RAM 0F 00 01 02 03 04 05 06 07 ← DD RAM 00010011 (DD,MK RAM right shift) *In spite of display digits, the data of 16-digit is required to write into DD RAM. NJU3430 (f)Display Blink Set R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 0 1 B 2 B 1 B 0 M D One blink state of Character and Icon is selected from among eight-step blink state by Display Blink Set. NonBlink is selected after Reset. The optional blink state should be selected before display operation. B 2 B 1 B 0 0 0 0 N o n - B l i n k S 0 0 1 B l i n k a t a b o u t 0 . 1 s : : : 1 1 0 B l i n k a t a b o u t 0 . 6 s 1 1 1 B l i n k a t a b o u t 0 . 7 s F C T A T U S : M U N T I O 0 The blink operation is not available. 1 The blink oparation is selected for Icon. D F U N C T I O N N 0 The blink operation is not available. 1 The blink oparation is selected for Character. *At fOSC=360kHz (g)Display Digits Set R S B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 0 0 1 0 0 0 C 2 C 1 C 0 The number of display digits is selected from among 9-digit to 16-digit by Display Digits Set. 16-digit is selected after Reset. The optional number of display digits should be selected before display operation. C 2 C 1 C 0 Display Digits 0 0 0 16-digit display 0 0 1 : : : : 1 1 0 14-digit display 1 1 1 15-digit display 9-digit display NJU3430 (h)RAM Address Set RS 0 B7 B6 B5 B4 B3 B2 B1 B0 1 0 0 0 A D 3 A D 2 A D 1 A D 0 ← DD RAM Addredd Set:(00)H to (0F)H 1 0 0 1 A M 3 A M 2 A M 1 A M 0 ← MK RAM Address Set:(00)H to (0F)H 1 1 A C 5 A C 4 A C 3 A C 2 ← CG RAM Address Set:(00)H to (3F)H A C 1 A C 0 The DD RAM, MK RAM and CG RAM Address are set by RAM Address Set. Correspondences of each RAM address and Display position are shown below : Correspondence of DD RAM Address and Timing terminals (Not shift) DD RAM Address 00 Digits 1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Correspondence of MK RAM Address and Timing terminals (Not shift) MK RAM Address 00 Digits 1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 About the detail of CG RAM Address, refer to "(1)CG RAM data and Character Dot Matrix”. (i)Write Data to RAM RS 1 B7 B6 B5 B4 S D 7 S D 6 S D 5 S D 4 0 0 0 0 0 0 0 S C 4 B3 B2 S D 3 S D 2 0 0 S C 3 S C 2 B1 B0 S D 1 S D 0 ← DD RAM Data Set:(00)H to (FF)H S M 1 S M 0 ← MK RAM Data Set:(00)H to (03)H S C 1 ← CG RAM Data Set:(00)H to (1F)H S C 0 The data are written into DD RAM, MK RAM and CG RAM by Write Data to RAM. The writing data address is used that is set the address just before writing data. Therefore, when the new data writing, the address set should be executed before writing data. The address is increased by 1 automatically after writing data, therefore, the MPU writes the data into the each RAM without any address setting after the start address. (Writing example) 1Byte 2Byte 3Byte 4Byte 10000011 01010101 11111000 00110101 DD RAM Address set(03)H DD RAM Address(03)H DD RAM Address(04)H DD RAM Address(05)H set CG ROM(55)H set CG ROM(F8)H set CG ROM(35)H The writing data in the each RAM are shown below. DD RAM Data[SD7 to SD0] --- Character code of each digit : (00)H to (FF)H MK RAM Data[SM1 to SM0] --- Icon display of each digit : SM1→ SM1→MK2, SM0→ SM0→MK1 CG RAM Data[SC4 to SC0] --- Character code : (00)H to (0F)H Dot Data (About the detail, refer to "(1)CG RAM data and Character Dot Matrix”.) NJU3430 n Interface with MPU The instruction and RAM data are input through the serial port. The data form is 8-bit per word, and data transfer is performed by synchronizing clock. The shift clock is input from external, and the data is loaded at the rising edge of the shift clock. One time transfer is executed by 8-bit unit. The transfer period is from falling edge to rising of the CS signal from external. Therefore, when the rising edge of the CS signal is input, the operation is started. When more than 8-bit data is input, the last 8-bit data is valid. The input data is judged as instruction or RAM data by the RS signal at the rising edge of the CS signal (RS=”H” : RAM data, RS=”L” : Instruction). When the input data is RAM data, the RAM address is increased one by one automatically after data writing. CS CLK RS SI B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 MSB MSB MSB [For example] DD RAM writing LSB LSB 1Byte 2Byte (Instruction) (Data) Select the Address LSB 3Byte (Data) Character Code Data of the Next Address Character Code Data n ABSOLUTE MAXIMUM RATINGS SYMBOL R A T I N G S UNIT Supply Voltage (1) V DD -0.3 to 6.5 V Supply Voltage (2) V FDP - 4 0 t o V D D +0.3 V V IN - 0 . 3 t o V D D +0.3 V P A R A M E T E R Input Voltage C O N D I T I O N S Ta ≤ 2 5 ° C Power Dissipation PD 800 mW Storage Temperature T stg -55 to 125 °C Operating Temperature Topr -40 to 85 °C IO 1 -40 mA T 1 - T 16 IO 2 -20 mA M K 1 - MK2 IO 3 -10 mA S 1 - S 35 Output Current Total Output Current QFP-64 IO 4 -4.0 mA P 1(LED drive is available) Σ IOH -100 mA All Terminals at "H" level Σ IO L 100 mA All Terminals at "L" level Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2) Decoupling capacitor should be connected between VDD and VSS, VFDP and VSS due to the stabilized operation for the LSI. Note 3) All voltage values are specified as VSS = 0V. The relation : VDD > VSS, VDD > VSS ≥ VFDP, VSS=0V must be maintained. NJU3430 - Timing Chart tCSU VIH CS PWCS tCYCE VIL tCH VIH tSC CLK tSC tSISU VIL tSIH VIH SI VIL tRS tRH VIH RS VIL Fig.1 Data Input Timing 0.8VDD VDD VSS tPRZ tRSOFF tRSON VIH tRSL RST tRSL VIL VIH SI VIL Fig.2 Reset Timing tR tR 0.8VDD 0.2VFDP Fig.3 Output Timing (CL=100pF, tR=20 to 80% or 80 to 20%) NJU3430 n VFD DRIVING WAVE FORM tCYCE OSC1 tDG tBK T1 T2 T3 : : T16 tSP S1 to S35 MK1 to MK2 Oscillation Frequency : tCYCE Minimum Blanking Time : tBK=t CYCE x 4 (Duty15/16) 1-character Display Time : tDG=t BK x 16 1-cycle Display Time : tSP=t DG x Digits NJU3430 n APPLICATION CIRCUIT 5x7 Dot Matrix VFD Display Heater ANODE ANODE VDD VDD MK1-MK2 S1 -S35 GRID T1 -T16 VDD NJU3 4 30 Output Port MC U VS S RST CS CLK SI RS P1 VS S VFDP OSC1 OSC2 LED VFDP ZD MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.