NJW1263 Analog Signal Input Class-D Amplifier for Piezo Speaker with DC-DC Converter Q GENERAL DESCRIPTION Q PACKAGE OUTLINE The NJW1263 is an analog signal input monaural class-D amplifier for Piezo speaker. And a built-in DC-DC converter generates variable output voltage (up to 20 V) with input voltage (3.0 to 4.2V). The NJW1263 incorporates BTL amplifier, which eliminate AC coupling capacitors, and it is capable of driving Piezo speaker with simple external LC low-pass filters. Class-D operation achieves lower power operation for Piezo speaker, thus the NJW1263 is suited for battery-powered applications. NJW1263WLC1 Q FEATURES O Output Voltage VDD=3.0V to 4.2V VDDO=8.0 to 20.0V@SP MODE VDDO=4.5V@REC MODE O Analog Audio Signal Input O 2input selector (Speaker Mode and Receiver Mode) O 1-channel BTL Output, Piezo Speaker Driving O Built-in DC-DC Converter O Built-in Low Voltage Detector O Standby (Hi-Z), Soft Start, Soft Mute Control O Built-in Pop noise reduction O Built-in Short Protector) O Built-in Thermal Protection O Package Outline: WCSP42 Q BLOCK DIAGRAM EQ1 VDD EQ2 VDDO VDD UVLO VDDO UVLO INSP INPREC OUTP Level Shifter Selector INNREC Pulse Width Modulator EQ3 VSS OCP OUTN Level Shifter OSC BIAS TSD SW COM Pulse Width Modulator COM STBYb OCP CONTROL LOGIC SOFT MODE NJW1263 Ver.3.1_E VSSREG - ROSC1 ROSC2 FB RSW SP RSW REC IN- -1- NJW1263 Q PIN CONFIGURATION No. A5 D5,D6 F1 G2 G3 E1 E2 D1 G4 C3 SYMBOL VDD VDDO INSP INPREC INNREC EQ1 EQ2 EQ3 COM SOFT I/O − − I I I I/O I/O I/O I/O I/O F3 STBYb I E3 MODE I A4 F2 A2,B3,B5,B6,C4 D4,E4,F4,F5,F6 E5,E6 C5,C6 ROSC1 ROSC2 I/O I/O 機 能 Power supply:VDD =3.7 V Output Power supply:VDDO =8.0 to 20.0 V Noninverted signal input (SP Mode) terminal Noninverted signal input (REC Mode) terminal Inversion signal Input (REC Mode) LPF Setting terminal LPF Setting terminal LPF Setting terminal Bias terminal Capacitor connection terminal for soft start Standby control terminal (STBYb =L: Standby) SP/REC mode switch terminal (MODE =H: SP Mode, MODE =L: REC Mode) The mode maintains the logic when the STBYb terminal is started up. Resistance connection terminal for Class-D Amp. Resistance connection terminal for switching regulator VSS − GND:VSS =0 V OUTP OUTN O O Noninverted signal output terminal Inversion signal output terminal A1,B1,B2 SW O Inductor connection terminal C1,C2 B4 VSSREG IN- − I/O A3 FB I/O GND:VSSREG =0 V Resistance connection terminal for DC/DC Phase compensating device connection terminal for G5 RSWREC I/O Resistance connection terminal to adjust DC/DC D2 RSWSP I/O Resistance connection terminal to adjust DC/DC D3 TEST1 I A6,G1,G6 NC - switching regulator Test Pin (50kΩ ground) Should be floating or VSS fixation. NC pin Should be floating or VSS fixation. Note: VBAT = VDD Note: Do not do floating the input terminal. -2- NJW1263 Ver.3.1_E NJW1263 NJU3555 Q TERMINAL CONFIGURATION 6 A6 B6 C6 D6 E6 F6 G6 5 A5 B5 C5 D5 E5 F5 G5 4 A4 B4 C4 D4 E4 F4 G4 3 A3 B3 C3 D3 E3 F3 G3 2 A2 B2 C2 D2 E2 F2 G2 1 A1 B1 C1 D1 E1 F1 G1 A B C D E F G (Top View) ■ INPUT TERMINAL Terminal Internal Circuit Vss NJW1263 Ver.3.1_E -3- NJW1263 Q ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VDD VDDO Supply Voltage Input Voltage VIN Operating Temperature Storage Temperature Power Dissipation Thermal resistance Topr Tstg PDMAX2 PDMAX4 θja2 θja4 CONDITIONS VDD VDDO INSP, INPREC, INNREC, STBYb, IN-, RSWREC, RSWSP MODE 2 layers (EIAJ), Tj = 125°C 4 layers (EIAJ), Tj = 125°C 2 layers (EIAJ), Tj = 125°C 4 layers (EIAJ), Tj = 125°C RATING -0.3 to +5.5 -0.3 to +36 (Ta=25°C) UNIT V -0.3 to VDD+0.3 V -40 to +85 -40 to +125 610 1200 164.5 81.8 °C °C mW mW °C /W °C /W Note 1) All voltage are relative to “VSS =0V” reference. Note 2) The LSI must be used within the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. Mounted on 2-layer/ 4-layer board based on EIA/JEDEC Note 3) The IC must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. Note 4) De-coupling capacitors must be connected between each power supply terminal and GND (VDD-VSS, VDDO-VSS). Note 5) The maximum power dissipation in the system is calculated, as shown below. PDMAX = T jMAX [°C ] − Ta [°C ] θ ja [°C / W ] Pdmax: Maximum Power Dissipation, Tjmax: Junction Temperature = 125°C Ta: Ambient Temperature, θja: Thermal Resistance of package = 164.5°C/W PD = 125℃ − 50℃ = 456[mW ] 164.5℃/W Note 6 ) The W-CSP package must not be illuminated by light because the characteristic may be affected by the photoelectric effect. -4- NJW1263 Ver.3.1_E NJW1263 NJU3555 QELECTRICAL CHARACTERISTICS O DC Characteristics Ta = 25 °C, VDD = 3.7 V, VDDO = 13.0 V(SP Mode: RSW=180 kΩ, RSP= 15 kΩ) VDDO = 4.5 V (REC Mode: RSW= 180 kΩ, RREC= 51 kΩ), VSS = 0.0 V, Load Impedance = 1.5 µF ROSC1=82 kΩ、ROSC2=82 kΩ、CLPF= 330 pF、Cc=0.033 µF、Output Filter: [LOUT= 22µH、RDAMP= 3.9Ω] SW regulator: [LSW= 6.8µH, CSW= 20µF+0.1µF, Ccmpn1= 10 nF, Ccmpn2= 33 pF, Rcmpn= 33 kΩ] Input Signal: INSP= 100 mVrms, INPREC- INNREC = 100 mVrms, Input Frequency = 1 kHz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. VDD VDD,VDDO Supply Voltage Output Driver On-state Resistance (High-side) Output Driver On-state Resistance (Low-side) Switching Regulator Output Driver On-state Resistance 3.0 8.0 4.2 3.7 13.0 4.5 4.2 20.0 4.8 V V V 1.3 2.0 2.4 Ω 1.3 2.2 2.8 Ω 1.3 2.0 2.4 Ω 1.3 2.2 2.8 Ω 0.05 0.4 0.7 Ω INSP 90 120 150 kΩ RINPREC INPREC 180 240 300 kΩ RINNREC INNREC 280 360 440 kΩ - - 1 µA - 13.0 16.5 mA - 4.0 5.0 mA VDDO RONHSP RONHREC RONLSP RONLREC RONSW RINSP Input Impedance Operating Current (Standby) Operating Current (No signal input) IST IBATSP IBATREC NJW1263 Ver.3.1_E UNIT SP Mode REC Mode SP Mode, OUTP, OUTN VOUTP, N = VDDO - 0.1 V REC Mode, OUTP, OUTN VOUTP, N = VDDO - 0.1 V SP Mode, OUTP, OUTN VOUTP, N = 0.1 V REC Mode, OUTP, OUTN VOUTP, N =0.1 V SW VSW = 0.1 V STBYb: "L",No Load SP Mode, Non-LC Filter, No Load REC Mode Non-LC Filter, No Load -5- NJW1263 PARAMETER SYMBOL MIN. TYP. MAX. UNIT 1.5 0 70 70 100 100 VDD 0.5 ±1 130 130 V V µA µA kΩ kΩ fOSCD 180 250 320 kHz fOSCSW 500 600 750 kHz 35 35 5.0 10.0 10 50 50 50 6.7 13.3 27.6 5.1 - 65 65 8.4 16.6 - kΩ kΩ ms ms dB dB VIH VIL ILK Input Voltage Input Leakage Current SW Off Leak Current OUTP Ground Resistance OUTN Ground Resistance Class-D Amplifier Oscillation Frequency Switching Regulator Oscillation Frequency Soft Start Resistance Soft Mute Resistance Start-up Time Stop Time Class-D Amplifier Voltage Gain MODE Setup Time MODE Holding Time ILKSW ＲOUTP ROUTN RSST RSMT TON TOFF AvSP AvREC TSTUP THLD CONDITIONS STBYb,MODE Pin STBYb,MODE Pin STBYb, MODE Pin SW Pin OUTP Pin OUTＮ Pin SOFT Pin SOFT Pin SP Mode, No Load REC Mode, No Load Refer to Figure 1. Refer to Figure 1. µs µs STBYb MODE TSTUP THLD Figure 1: STBYb/MODE input timing -6- NJW1263 Ver.3.1_E NJW1263 NJU3555 O AC Characteristics Ta = 25 °C, VDD = 3.7 V, VDDO = 13.0 V(SP Mode: RSW=180 kΩ, RSP= 15 kΩ) VDDO = 4.5 V (REC Mode: RSW= 180 kΩ, RREC= 51 kΩ), VSS = 0.0 V, Load Impedance = 1.5 µF ROSC1=82 kΩ、ROSC2=82 kΩ、CLPF= 330 pF、Cc=0.033 µF、Output Filter: [LOUT= 22µH、RDAMP= 3.9Ω] SW regulator: [LSW= 6.8µH, CSW= 20µF+0.1µF, Ccmpn1= 10 nF, Ccmpn2= 33 pF, Rcmpn= 33 kΩ] Input Signal: INSP= 100 mVrms, INPREC- INNREC = 100 mVrms, Input Frequency = 1 kHz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. SP Mode, THD+NSP 0.1 VOUTSP =3 Vrms THD+N REC Mode 0.05 THD+NREC VOUTREC =1 Vrms SP Mode, VOUTSP 20 THD+N=1% Maximum Output Voltage REC Mode, 2.7 VOUTREC THD+N=1% REC MODE, A-weight 80 S/N SN VOUTREC =1 Vrms Noise Floor VN REC MODE, A-weight 100 - NJW1263 Ver.3.1_E UNIT % % VPP Vrms dB µVrms -7- NJW1263 Q FUNCTIONAL DESCRIPTION O Signal Input Terminal (INSP, INPREC, INNREC) Analog signal input. The input signal is selected by the operational mode. O Capacitor connection terminal for LPF (EQ1, EQ2, EQ3) The amount of current passing through a capacitive load increases proportionately with frequency of audio signal. Input filters should be put in the input line to reduce load current at high frequency-band. The input low pass filters are composed of feedback resister (R1) and capacitor (CLPF). Refer to the following expression. R1= 120kΩ, CLPF= 330pF f LPF = 1 1 = ≒ 4.0[kHz] 2πR1C LPF 2 × 3.14 × 120kΩ × 330 pF CLPF EQ1 EQ2 NJW1261 INSP INPREC INNREC EQ3 R1 RINSP RINPREC Selector RINNREC R1 R1=120[kΩ] CLPF Figure 2: Input LPF composition O Signal Output Terminal (OUTP, OUTN) The output signals are PWM signals, which will be converted to analog signal via external 2nd-order or higher LC filter. Should be connected to the damping resistor (RDAMP) between OUTP pin and coil, and between OUTN pin and coil to reduce the current consumption with signal-input close to cutoff-frequency of LPF (fc). Set the value of LOUT, CL, and RDAMP to become Q<1. Refer to the following expression. LOUT =22µH, CL=1.5µF, RDAMP=3.9Ω, Equivalent direct resistance of L (RDCR) =0.5Ω fc = 1 1 = ≒ 19.6[kHz] 2π 2 LOUT C L 2 × 3.14 × 2 × 22 µH × 1.5µF Q= -8- 1 R DAMP + RDCR LOUT 1 22 µH ≒ 0.61 = × 2C L 3.9Ω + 0.5Ω 2 × 1.5µF NJW1263 Ver.3.1_E NJW1263 NJU3555 O Standby Terminal (STBYb) By setting the STBYb pin to “L” level, it switches the NJW1261 into standby condition. During the standby condition, output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. Keep the STBYb pin to “L” level at least 13.3ms once switched into the standby condition. For normal operation, the STBYb pin requires “H” level. Time from the standby release to class-D power amplifier operation is 6.7ms(TYP). Do not change to the standby mode until the power amplifier operation. Set the standby mode at power supply ON/OFF. O Capacitor connection terminal for soft start (SOFT) Capacitor connection terminal for soft start and soft mute VDD RSFT RSFT=50[kΩ] CSFT=0.1[µF] SOFT SOFT START CIRCUIT RSFT CSFT VSS O Step-up switching regulator The switching regulator is used as power supply (VDDO) for power amplifier of class-D. The PFM controlled switching regulator works with external components, which are coil, capacitor, Schottky barrier diode and step-up voltage setting resistance. NJW1263 Ver.3.1_E -9- NJW1263 O Mode SP/REC mode selection terminal. The output power-supply voltage, the input selector, and the voltage gain change when the mode is switched. MODE= H :SP（Speaker）Mode Audio input terminal: INSP(Shingle end input) Class-D amplifier output power-supply voltage: Step-up switching regulator ⎛ R VSWSP = 1.0V × ⎜⎜1 + SW RSP ⎝ ⎞ ⎟⎟ ⎠ RSW + RSP = 100 Kohm to 1300 Kohm. Voltage gain: 27.6 dB (TYP) MODE= L ：REC（Receiver）Mode Audio input terminal: INPREC、INNREC(Difference input) Class-D amplifier output power-supply voltageStep-up switching regulator ⎛ R VSWREC = 1.0V × ⎜⎜1 + SW ⎝ RREC ⎞ ⎟⎟ ⎠ Set the 4.5V(TYP) DC/DC voltage by RSW and RSP. RSW + RSP = 100 Kohm to 1300 Kohm. Voltage gain: 5.1 dB (TYP) SW LSW VBAT Pulse Width Modulator DSW VSSREG 1V VDDO CSW FB RSWREC RSWSP IN- R SP R SW RREC Switching regulator circuit Note) Set the Step-up switching regulator voltage within the range of the VDDO operation voltage. Note) Reset it when you switch MODE. (STBYb“L") O Low Voltage Detector When the power-supply voltage drops down to below VDD, the output driver is turned off output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. - 10 - NJW1263 Ver.3.1_E NJW1263 NJU3555 O Short Circuit Protection The short-circuit protection circuit operates at the condition of the following. -Short between OUTP and OUTN - Power supply short and earth fault of OUTP terminal - Power supply short and earth fault of OUTN terminal - Power supply short of SW terminal When OUTP and OUTN of the short-circuit protection circuit operates, the OUTP and OUTN become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. It restarts by pulse-by-pulse of built-in clock of class-D amplifier. When SW terminal of the short-circuit protection circuit operates, the SW terminal become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. It restarts by pulse-by-pulse of built-in clock of the switching regulator. Note) *1 The detectable current and the period for the protection depend on the power supply voltage, chip temperature and ambient temperature. *2 The short protector is not effective for a long term short-circuit current but for an instantaneous accident. Continuous high current may cause permanent damage to the NJW1261. O Thermal protection When the junction temperature is more than specified value, the output driver is turned off output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. When the junction temperature is less than specified value, protection is released. Q TOTAL HARMONIC DISTORTION MEASUREMENT CIRCUIT NJW1263 AUX-0025 NJW1263 Evaluation Board LPF NJW1263 Ver.3.1_E Filters 20kHz(AES17) THD METER Audio Analyzer - 11 - NJW1263 Q TYPICAL APPLICATION CIRCUIT Q Recommended Parts CDD1: GRM31CB31E106KA75L(muRata) CSW1: GRM31CB31E106KA75L(muRata)×2 CDD2, CSW2, CSFT: GRM155B31E104KA87D(muRata) CCM: GRM155B31A105KE15D(muRata) CCSP, CCPREC, CCNREC: GRM033B10J333KE01D(muRata) Ccmpn1: GRM155R11C103KA01D(muRata) Ccmpn2: GRM1552C1H330JA01D(muRata) CLPF1, CLPF2,: GRM155B11H331KA01D(muRata) LSW: LQH44PN6R8MPO(muRata) LOUTP, LOUTN: LQH44PN220MP0(muRata) DSW: RSX201VA-30(ROAM) RDAMP: ERJ-14YJ3R9U(Panasonic) Q Specified Parts Rosc1, Rosc2: RK73H1JTTD8202F(KOA) Note) De-coupling capacitors must be connected between each power supply terminal and GND (VDD-VSS, VDDO-VSS). Note) VSS should be connected at a nearest point to the IC on PCB. Note) INSP, INPREC, INNREC, EQ1, EQ2 and EQ3 should be not designed near OUTP,OUTN and SW, which emit PWM noise. Note) The transition time for MODE and STBYb signals must be less than 100µs. Otherwise, a malfunction may be occurred. Note) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carefully to fit your application. Note) RDAMP includes the resistance of the current limitation series of the piezoelectric element and the direct current resistance of coil LOUT. Decide the value of RDAMP considering the piezo and the value of the coil. Note) The speaker should be designed at a near the IC. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 12 - NJW1263 Ver.3.1_E