SM8222A/B Caller ID Service IC with Call Waiting NIPPON PRECISION CIRCUITS INC. ina ry OVERVIEW The SM8222A/B is a calling number identification (caller ID) and call waiting signal (dual tone signal) receiver decoder IC that conforms with the TRNWT-000030 and SR-TSV-002476 (Bellcore) dialer FEATURES ■ ■ ■ ■ ■ ■ ■ Conforms to TR-NWT-000030 and SR-TSV002476 (Bellcore) standards Call waiting FSK demodulator Ring signal detect circuit built-in High input sensitivity Input gain adjust circuit built-in Power-down mode ■ ■ Telephones that display dialer number before and during conversation Adapters to display dialer number before and during conversation ORDERING INFORMATION D e vice SM8222AS SM8222AP P ackag e SM8222BP ■ ■ ■ ■ ■ Crystal oscillator circuit built-in Single supply operation Microcontroller I/O interface Molybdenum-gate CMOS process 24-pin SOP and 24-pin DIP packages SM8222A : 2.7 to 3.3V operation SM8222B : 4.5 to 5.5V operation ■ ■ ■ Answering machines Facsimile machines Computer peripheral devices PINOUT (Top View) 24-pin SOP 24-pin DIP 24-pin SOP TIP 24-pin DIP RING pre SM8222BS ■ ■ lim APPLICATIONS telephone number display standards. It is implemented in CMOS and incorporates a power-down function for low power operation. 1 24 VDD STGT GS EST AGND STD CAP INT RDIN CDET RDRC DR RDET DOUT MODE DCLK OSCIN FSKEN OSCOUT PDWN GND 12 13 IC NIPPON PRECISION CIRCUITS—1 SM8222A/B PACKAGE DIMENSIONS (Unit: mm) 24-pin DIP ina ry 24-pin SOP + 0.20 1.27 0.10 0.45 0.10 0.13 M 0.05min 2.80max 15 max 0.50 0.20 2.54 lim BLOCK DIAGRAM TIP Amplifier RING GS 0.25 0 .05 3.00min 4.96max + 0.50 1.50 − 0 0.51min + 0.05 0.15 − 0.02 + 0.25 15.24 − 0.20 15.24 13.55 0.25 7.60 0.30 10.20 0.40 30.20 − 0.30 Filter FSK Demodulator FSKEN 0.45 0.08 MODE DOUT Data Timing Control DR Carrier Detector Interrupt Generator pre Level Detector Filter CAP Bias Generator CDET INT Data Detector (2130Hz) Filter (2130Hz) AGND DCLK Guard Time Control Data Detector (2750Hz) Filter (2750Hz) STD STGT EST Level Detector Oscillator OSCIN OSCOUT RDIN RDRC RDET PDWN VDD GND NIPPON PRECISION CIRCUITS—2 SM8222A/B PIN DESCRIPTION Name I/O Description 1 TIP I Tip input: Connected to the telephone through a protection circuit. 2 RING I Ring input: Connected to the telephone through a protection circuit. 3 GS O Input stage amplifier output: Used to select the input amplifier gain 4 AGND O Analog ground: Internal reference voltage (VDD /2) output. 5 CAP I Reference voltage capacitor connection. C = 0.1 µF 6 RDIN I Ring detect input: Line reversal and ring signal detect input. Connect to detect attenuated ring signals. Schmitt-trigger input. 7 RDRC I/O Ring detect RC connection: RC network connection to set the ring detect delay time. Open-drain output and schmitt-trigger input. 8 RDET O Ring detect output: RDRC schmitt-trigger buffer output. LOW when a ring signal is detected. 9 MODE I FSK interface mode select: Demodulated FSK signal output method select. LOW [Mode = 0]: Demodulated data output and data sync clock output. HIGH [Mode = 1]: Data output in sync with an external clock. 10 OSCIN I Crystal oscillator element input: Oscillator element connection between OSCIN and OSCOUT. 11 OSCOUT O Crystal oscillator element output: Oscillator element connection between OSCIN and OSCOUT. 12 GND – Ground: Connect to system ground. 13 IC I Test input: Tie LOW for normal operation. 14 PDWN I Power-down control: LOW for normal operation. HIGH for device power-down state. When device is powered-down, AGND, OSCOUT, DCLK, DOUT, INT, CDET are all HIGH. DR also goes HIGH in mode 0 output. Schmitt-trigger input. lim ina ry Number FSK signal output control: Demodulated FSK signal output and carrier detect output control. Mode 0: DCLK, DOUT, DR, CDET control Mode 1: DCLK, DOUT, CDET control FSK signal reception enabled when HIGH. Signal pins (above) go HIGH when FSKEN is LOW. FSKEN I 16 DCLK I/O FSK interface clock: Demodulated FSK signal output clock. Mode 0: Clock output in sync with data Mode 1: Data read clock input 17 DOUT O Data output: Demodulated FSK signal output. HIGH-level output when PDWN is HIGH or FSKEN is LOW, or when CDET is HIGH in receive state. 18 DR O Data output trigger: Demodulated FSK data timing output. Active-LOW. Becomes active when 8 bits of data are completed. 19 CDET O Carrier (FSK signal) detect output: Goes LOW when a valid carrier signal is detected. 20 INT O Interrupt signal output: Goes LOW when either RDET is LOW, DR is LOW or STD is HIGH. 21 STD O Dual tone indicator output: Goes HIGH if the dual tone detect signal is recognized after the external RC circuit time delay has elapsed. 22 EST O Dual tone detect output: Goes HIGH when the dual tone is detected. 23 STGT I/O Dual tone RC time constant circuit connection: External RC network connection for dual tone signal detection processing. Sets STD output. 24 VDD – pre 15 Supply voltage NIPPON PRECISION CIRCUITS—3 SM8222A/B SPECIFICATIONS Absolute Maximum Ratings GND = 0 V Symbol Supply voltage range V DD Input voltage range V IN Input current IIN Power dissipation PD Storage temperature range Tstg Condition Rating SM8222A −0.5 to 5.0 SM8222B −0.5 to 7.0 Unit ina ry P arameter V −0.3 to V DD + 0.3 V 10 mA 44 mW −40 to 125 °C Recommended Operating Conditions GND = 0 V Rating P arameter Supply voltage range Symbol V DD fCLK Clock frequency accuracy ∆fC typ max SM8222A 2.7 – 3.3 SM8222B 4.5 – 5.5 – 3.579545 – MHz −0.1 – +0.1 % −20 – 85 °C V Topr pre Operating temperature Unit min lim Clock frequency Condition NIPPON PRECISION CIRCUITS—4 SM8222A/B DC Electrical Characteristics ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit min Power-down current consumption IDPD LOW-level input voltage 1 V IL1 HIGH-level input voltage 1 V IH1 LOW-level input voltage 2 V IL2 HIGH-level input voltage 2 V IH2 LOW-level input voltage 3 V IL3 HIGH-level input voltage 3 V IH3 LOW-level output current IOL HIGH-level output current IOH Input leakage current Output leakage current ■ SM8222B IIN IOFF max OSCIN = PWDN = RDIN = RDRC = MODE = 0 V, FSKEN = V DD, all other inputs open – 2.5 4.5 mA OSCIN = RDIN = RDRC = MODE = 0 V, PWDN = FSKEN = V DD, all other inputs open – – 15 µA PWDN, MODE, FSKEN – – 0.3VDD V PWDN, MODE, FSKEN 0.7VDD – – V RDIN, RDRC – – 0.3VDD V RDIN, RDRC 0.7VDD – – V OSCIN – – TBD V OSCIN TBD – – V DOUT, EST, STD, STGT, DCLK, DR, RDET, CDET 2 – – mA DOUT, EST, STD, STGT, DCLK, DR, RDET, CDET – – −0.8 mA OSCIN, PWDN, RDIN −1 – 1 µA RDRC, INT – – 1 µA ina ry IDD lim Current consumption typ VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter IDD Rating Condition OSCIN = PWDN = RDIN = RDRC = MODE = 0 V, FSKEN = V DD, all other inputs open pre Current consumption Symbol Unit min typ max – 4.5 8.0 mA – – 15 µA Power-down current consumption IDPD OSCIN = RDIN = RDRC = MODE = 0 V, PWDN = FSKEN = V DD, all other inputs open LOW-level input voltage 1 V IL1 PWDN, MODE, FSKEN – – 0.3VDD V HIGH-level input voltage 1 V IH1 PWDN, MODE, FSKEN 0.7VDD – – V LOW-level input voltage 2 V IL2 RDIN, RDRC – – 0.3VDD V HIGH-level input voltage 2 V IH2 RDIN, RDRC 0.7VDD – – V LOW-level input voltage 3 V IL3 OSCIN – – TBD V HIGH-level input voltage 3 V IH3 OSCIN TBD – – V LOW-level output current IOL DOUT, EST, STD, STGT, DCLK, DR, RDET, CDET 2 – – mA HIGH-level output current IOH DOUT, EST, STD, STGT, DCLK, DR, RDET, CDET – – −0.8 mA Input leakage current IIN OSCIN, PWDN, RDIN −1 – 1 µA RDRC, INT – – 1 µA Output leakage current IOFF NIPPON PRECISION CIRCUITS—5 SM8222A/B AC Electrical Characteristics FSK decoder ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Symbol Input sensitivity Bandpass filter frequency response (relative gain for 1700 Hz sine wave input) Carrier detect sensitivity CD ON No-carrier detect sensitivity CD OFF Oscillator frequency ■ fCLK SM8222B ina ry Rating P arameter Condition Unit min typ max – −48 CD ON 60 Hz – −80 – 1200 Hz – −1 – 2200 Hz – 0 – 4000 Hz – −43 – ≥ 10,000 Hz – −54 – – −48 −44 dBm −55 −51 – dBm −0.1% 3.579545 +0.1% MHz dBm dB P arameter Input sensitivity lim VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Symbol typ max – −48 CD ON 60 Hz – −80 – 1200 Hz – −1 – 2200 Hz – 0 – 4000 Hz – −43 – ≥ 10,000 Hz – −54 – CD ON – −48 −44 dBm CD OFF −55 −51 – dBm −0.1% 3.579545 +0.1% MHz pre No-carrier detect sensitivity Oscillator frequency Unit min Bandpass filter frequency response (relative gain for 1700 Hz sine wave input) Carrier detect sensitivity Rating Condition fCLK dBm dB NIPPON PRECISION CIRCUITS—6 SM8222A/B Dual tone detector ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit Low tone frequency fL High tone frequency fH Detection frequency deviation No-detection frequency deviation Detection sensitivity No-detection sensitivity Signal level difference ■ SM8222B typ max ina ry min – 2130 – Hz – 2750 – Hz 1.1 – – % 3.5 – – % −37.78 – – dBm – – −43.78 dBm – – 6 dB VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit min typ max – 2130 – Hz – 2750 – Hz Detection frequency deviation 1.1 – – % No-detection frequency deviation 3.5 – – % −37.78 – – dBm – – −43.78 dBm – – 6 dB fL High tone frequency fH Detection sensitivity No-detection sensitivity pre Signal level difference lim Low tone frequency NIPPON PRECISION CIRCUITS—7 SM8222A/B Input Stage Amplifier Characteristics ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit Input leakage current IIN Input resistance R IN DC open loop voltage gain AVOL Unity gain frequency fC Maximum load capacitance CL Maximum load resistance RL ■ SM8222B typ max ina ry min – – 1 µA – TBD – MΩ TBD – – dB TBD – – MHz – – TBD pF 50 – – kΩ VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit min typ max – – 1 µA – TBD – MΩ TBD – – dB fC TBD – – MHz Maximum load capacitance CL – – TBD pF Maximum load resistance RL 50 – – kΩ Input leakage current IIN Input resistance R IN Unity gain frequency AVOL lim DC open loop voltage gain Timing Characteristics FSK decoder ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Symbol pre P arameter Rating Condition Unit min typ max Power-down release to oscillator start time tDOSC – 5 – ms Carrier detect ON time tDAQ 2.5 – 10 ms Final data to carrier detect OFF time tDCH 3.75 – 11.25 ms ■ SM8222B VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C P arameter Symbol Rating Condition Unit min typ max Power-down release to oscillator start time tDOSC – 5 – ms Carrier detect ON time tDAQ 2.5 – 10 ms Final data to carrier detect OFF time tDCH 3.75 – 11.25 ms NIPPON PRECISION CIRCUITS—8 SM8222A/B Output timing circuit: mode 0 ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol Condition Unit Rise time tr0 Fall time tf0 LOW-level pulsewidth tPWL HIGH-level pulsewidth tPWH DCLK frequency fDCLK0 Input/output delay tIDD DOUT to DCLK delay tDCD DCLK to DOUT delay tCDD DCLK to DR delay tCRD Data rate ■ SM8222B typ max ina ry min DR, DCLK, DOUT – – TBD ns DR, DCLK, DOUT – – TBD ns DR, DCLK 415 416 417 µs DCLK 415 416 417 µs DCLK 1201.6 1202.8 1204 Hz Input → DOUT – – TBD ms DOUT → DCLK TBD 416 – µs DCLK → DOUT TBD 416 – µs DCLK → DR 415 416 417 µs DOUT 1188 1200 1212 baud VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating Rise time Fall time LOW-level pulsewidth HIGH-level pulsewidth DCLK frequency Input/output delay DOUT to DCLK delay DCLK to DOUT delay Condition Data rate Unit min typ max tr0 DR, DCLK, DOUT – – TBD ns tf0 DR, DCLK, DOUT – – TBD ns tPWL DR, DCLK 415 416 417 µs tPWH DCLK 415 416 417 µs fDCLK0 DCLK 1201.6 1202.8 1204 Hz tIDD Input → DOUT – – TBD ms tDCD DOUT → DCLK TBD 416 – µs tCDD DCLK → DOUT TBD 416 – µs tCRD DCLK → DR 415 416 417 µs DOUT 1188 1200 1212 baud pre DCLK to DR delay Symbol lim P arameter NIPPON PRECISION CIRCUITS—9 SM8222A/B Output timing circuit: mode 1 ■ SM8222A VDD = 3.0 ± 0.3 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating Symbol DCLK rise time tr1 DCLK fall time tf1 Duty Frequency fDCLK1 DCLK to DR setup time tDDS DR to DCLK hold time tDDH ■ SM8222B Condition Unit min typ max DCLK – – TBD ns DCLK – – TBD ns DCLK 30 – 70 % DCLK – – 1 MHz DCLK → DR 500 – – ns DR → DCLK 500 – – ns ina ry P arameter VDD = 5.0 ± 0.5 V, GND = 0 V, fCLK = 3.579545 MHz, Ta = −20 to 85 °C Rating P arameter Symbol tr1 DCLK fall time tf1 Duty Frequency DCLK to DR setup time typ max DCLK – – TBD ns DCLK – – TBD ns DCLK 30 – 70 % DCLK – – 1 MHz tDDS DCLK → DR 500 – – ns tDDH DR → DCLK 500 – – ns pre DR to DCLK hold time fDCLK1 Unit min lim DCLK rise time Condition NIPPON PRECISION CIRCUITS—10 SM8222A/B FUNCTIONAL DESCRIPTION ■ ■ ■ Ring signal detection FSK demodulation Dual tone detection Using these functions enables systems with the following features to be easily constructed. ■ ■ ■ Ring signal and polarity reversal signal detection dialer telephone number display before telephone off-hook dialer telephone number display after telephone off-hook (during conversation) Ring Signal Detection Mode 0 In mode 0, the received data and the clock that the data is synchronized to are both output. In addition, an output pulse occurs on DR with the same timing as each stop bit in the input data stream. ina ry The SM8222A/B conforms with the SR-TSV002476 (Bellcore) dialer telephone number display standards. It supports the following functions. In mode 1, DR goes LOW when data is received. From that point on, the data is read out with timing set by an external clock input on DCLK. In this mode, data can be read out at a different speed to the input data rate. Dual Tone Detection After a conversation has been initiated (after telephone is off-hook), the dialer telephone number service information is sent by mixing two signals, 2130 and 2750 Hz, on the line inputs L1 and L2. The SM8222A/B incorporates detectors to recover these two signals from the conversation “noise” signal. The two signals are recovered using two high-order filters with center frequencies of 2130 and 2750 Hz, respectively, in the final stage. The SM8222A/B uses a detection circuit with time delay built-in so that detection is maintained for an input signal where the input level temporarily rises above the rated value or falls below the rated value to a level of non-detection. When the 2130 and 2750 Hz signals are simultaneously detected, EST goes HIGH and starts charging the time constant circuit formed by an external capacitor and resistor. When the time constant circuit voltage STGT rises above a threshold voltage, STD goes HIGH to indicate the dual tone signal has been detected. When a dual tone signal is detected, INT also becomes active and goes LOW. lim The telephone line input signals L1 and L2 pass through surge protection circuits and are input to a capacitor, resistor and diode bridge, as shown in the typical application circuit example. The signal is full-wave rectified by the diode bridge and the bridge output is level shifted by the resistor voltage divider for input to RDIN. A ring signal input on RDIN causes RDRC to become active, driving an RC time constant circuit formed by an external capacitor and resistor, before the detection signal is output on RDET. If the ring signal supplied by the inputs L1 and L2 is above the level set by the resistor divider, then the detect output RDET goes LOW. When a ring signal is detected, INT also goes LOW. Mode 1 FSK Demodulation pre The SM8222A/B incorporates an FSK demodulator to recover the dialer telephone number and other information which is sent as an FSK signal. It supports two demodulator output modes to facilitate various circuit design approaches. The FSK signal (Bellcore) standard is described as follows. ■ ■ ■ ■ ■ ■ Modulation type: Continuous-phase binary frequency-shift-keying Logic 1 data (mark): 1200 ± 12 Hz Logic 0 data (space): 2200 ± 22 Hz Input level (mark): −32 to −12 dBm Input level (space): −36 to −12 dBm Transmission speed: 1200 ± 12 baud The FSK output is controlled by the FSKEN pin. When FSKEN is HIGH, the signal pins DOUT, DCLK, DR and CDET are all HIGH. The decoded FSK signal is output on DOUT. The mode of the output timing circuit, mode 0 or mode 1, is set by the input on MODE. NIPPON PRECISION CIRCUITS—11 SM8222A/B TIMING DIAGRAMS Ring Detector and FSK Demodulator 2nd Ring 1st Ring L1/L2 1 Data ina ry 101010... RDRC RDET PDWN CDET tDCH tDAQ DOUT Data lim OSCOUT 101010...1 pre tDOSC NIPPON PRECISION CIRCUITS—12 SM8222A/B Output Mode 0 tDCD tCDD 90% DOUT tr0 ina ry 10% tf0 90% DCLK 10% tf0 tPWL tPWH tr0 tPWL 90% DR 10% tf0 tr0 lim STOP START TIP/RING b6 b7 1 STOP START 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 tIDD START DOUT b4 b5 b6 b7 STOP DCLK tPWL b0 b1 b2 b3 b4 STOP 1/fDCLK0 tCRD pre DR START b0 b1 b2 b3 b4 b5 b6 b7 NIPPON PRECISION CIRCUITS—13 SM8222A/B Output Mode 1 0.7VDD DCLK tf1 tr1 N Input Data N+1 b7 STOP START DR tDDS tDDH DCLK DATA b7 ina ry 0.3VDD b0 b1 b2 b3 b4 b5 b6 b7 STOP 1/fDCLK1 b0 b1 b2 b3 b4 b5 b6 b7 pre lim N NIPPON PRECISION CIRCUITS—14 SM8222A/B TYPICAL APPLICATION CIRCUIT VDD VDD 430K 22nF (240k) 5% 1% L1 34k 1% VDD 0.1µF 20% ina ry Surge Protection 464k 1% L2 34k 1% 22nF 430K 5% (240k) 1% 53.6k 1% VDD 100nF 499k 5% 5% 60.4k 1% 200k 150k 5% 5% VDD 100nF 499k 5% 5% 301k 5% TIP RING EST AGND STD CAP INT RDIN CDET RDRC DR RDET DOUT MODE DCLK OSCIN FSKEN 100k 20% PDWN IC lim GND VDD STGT GS OSCOUT 220nF 100nF 20% 20% VDD ( ) = when SM8222B pre All circuit component values are shown for reference only. These values are not guaranteed for mass production specification. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9811BE 1999.1 NIPPON PRECISION CIRCUITS—15