SM5852CS Dynamic Range Compression LSI NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT The SM5852CS is a digital signal processor IC that performs dynamic range compression for use in digital audio reproduction equipment. It is designed for use with a 44.1 kHz sampling frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DB/DS 2 MOD2 DI 3 14 MOD1 13 OPT CLK 4 VSS 5 RSTN 6 TESTN 7 MUTEN 8 SM5852CS ■ 2-channel processing 6 input-level dependent dynamic gain characteristics Dynamic range compression bypass mode 2 attack time settings Soft muting function Serial input/output interface 2s complement, MSB first, 16-bit 384fs system clock 23 × 23-bit multiplier/30-bit high-precision accumulator TTL-compatible input/output 3.2 to 5.5 V operating voltage range 16-pin SOP Molybdenum-gate CMOS 16 15 LRCI FEATURES ■ 1 BCKI 12 VDD 11 LRCO 10 BCKO 9 DOUT PACKAGE DIMENSIONS 16-pin SOP (Unit: mm) ORDERING INFOMATION 10.16±0.3 10.5 MAX 6.8±0.3 8.0±0.3 16pin SOP 8.0±0.3 SM5852CS 0.17±0.05 5.5±0.3 Package 0˚ to 15˚ 2.0±0.2 0.1±0.1 Device 0.635±0.15 1.27±0.15 0.4±0.15 NIPPON PRECISION CIRCUITS—1 SM5852CS BLOCK DIAGRAM LRCI BCKI DI Input data Interface VDD DSP Block CLK RSTN VSS System Clock Sequence Control Output data Interface TESTN MUTEN DB/DS OPT MOD1 LRCO BCKO DOUT Mute Control Mode Control MOD2 NIPPON PRECISION CIRCUITS—2 SM5852CS PIN DESCRIPTION Number Name I/O1 1 LRCI Ip Input data sample rate (fs) clock input 2 BCKI Ip Bit clock input 3 DI Ip Serial data input 4 CLK I Clock input 5 VSS – Ground 6 RSTN Ip System reset initialization. Reset when LOW. 7 TESTN Ip Test mode input. Testing when LOW. 8 MUTEN Ip Mute input. Muting when LOW. 9 DOUT O Serial data output 10 BCKO O Bit clock output 11 LRCO O Output data sample rate (fs) clock output 12 VDD – 3.2 to 5.5 V supply 13 OPT Ip Attack time switch input. Attack-1 when HIGH, and attack-2 when LOW. Description Gain characteristics switch inputs. 14 15 16 MOD1 MOD2 DB/DS Ip Ip Ip DB/DS MOD2 MOD1 Compression mode LOW LOW LOW 6 LOW LOW HIGH 5 LOW HIGH LOW 4 LOW HIGH HIGH Off HIGH LOW LOW 3 HIGH LOW HIGH 2 HIGH HIGH LOW 1 HIGH HIGH HIGH Off 1. Ip = Input pin with pull-up resistor. Accordingly, they can be left open for HIGH-level input. NIPPON PRECISION CIRCUITS—3 SM5852CS SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Symbol Condition Rating Unit Supply voltage V DD −0.3 to 7.0 V Input voltage V IN V SS − 0.3 to V DD + 0.3 V Storage temperature T stg −40 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Rating Unit Recommended Operating Conditions VSS = 0 V Parameter Symbol Condition Supply voltage V DD 3.2 to 5.5 V Operating temperature Topr −35 to 85 °C DC Characteristics Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −35 to 85 °C Rating Parameter Current consumption1 Input voltage for all inputs Symbol Condition Unit min typ max – 16 23 mA V IH 2.4 – – V V IL – – 0.5 V 2.5 – – V IDD V DD = 5.0 V VOH IOH = −0.4 mA VOL IOL = 1.6 mA – – 0.4 V Input leakage current for all inputs ILH V IN = V DD – – 1.0 µA CLK input leakage current ILL V IN = 0 V – – 1.0 µA Input current for all inputs except CLK IIL V IN = 0 V – – 20 µA Output voltage for all outputs 1. fCLK = 384fs = 16.9344 MHz, no output load, input data conformance with NPC test pattern Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Current consumption1 Input voltage for all inputs Symbol Condition Unit min typ max – 7 10 mA V IH 2.4 – – V V IL – – 0.5 V 2.5 – – V IDD V DD = 3.4 V VOH IOH = −0.2 mA VOL IOL = 0.8 mA – – 0.4 V Input leakage current for all inputs ILH V IN = V DD – – 1.0 µA CLK input leakage current ILL V IN = 0 V – – 1.0 µA Input current for all inputs except CLK IIL V IN = 0 V – – 12 µA Output voltage for all outputs 1. fCLK = 384fs = 16.9344 MHz, no output load, input data conformance with NPC test pattern NIPPON PRECISION CIRCUITS—4 SM5852CS AC Characteristics Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −35 to 85 °C Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 70 °C CLK (384fs) Rating Parameter Symbol Condition Unit min typ max Clock pulsewidth tCW 24 – 500 ns Clock cycle time tCY 55 59 1000 ns tcy VIH CLK 1.5V tCW VIL tCW RSTN Rating Parameter Symbol Reset LOW-level pulsewidth tRST Condition Unit min typ max At power-ON 1 – – µs At all other times 50 – 1000 ns 3.2V VDD tRST ≥ 1µsec tRST RSTN 1.5V RSTN should be set LOW at power-ON and after reacquiring synchronization. Note that if RSTN is LOW for longer than 1 µs, a through-current flows in the internal dynamic circuits because the internal clock is stopped. The through-current has no rated value, so the reset pulse should be kept as short as possible at all times other than at power-ON. NIPPON PRECISION CIRCUITS—5 SM5852CS Serial input timing Rating Parameter Symbol Condition Unit min typ max BCKI pulsewidth tBCIW 100 – – ns BCKI cycle time tBCIY 200 – – ns DI setup time tDIS 75 – – ns DI hold time tDIH 75 – – ns LRCI setup time tLIS 75 – – ns LRCI hold time tLIH 75 – – ns BCKI 1.5V tBCIW tBCIW tBCIY DI 1.5V tDIS tDIH 1.5V LRCI tLIS tLIH DB/DS, OPT Rating Parameter Minimum pulsewidth Symbol Condition tW Unit min typ max 2/fs – – ns When DB/DS or OPT change state, the input level must be constant for a minimum of 2/fs (2 × LRCI cycle time). Input levels of duration less than 2/fs may be ignored. NIPPON PRECISION CIRCUITS—6 SM5852CS Serial output timing Rating Parameter Symbol Condition Unit min typ max BCKO pulsewidth tBCOW 15 pF load 180 1/96fs – ns BCKO cycle time tBCOY 15 pF load 400 1/48fs – ns tDHL 15 pF load −20 – 60 ns tDLH 15 pF load −20 – 60 ns DOUT, LRCO output delay time BCKO 1.5V tBCOW tBCOW tBCOY DOUT LRCO 1.5V tDHL tDLH NIPPON PRECISION CIRCUITS—7 SM5852CS Dynamic Compression Characteristics Compression mode 1 (DB/DS = HIGH, MOD2 = HIGH, MOD1 = LOW) Compression Compression ratio Mode 1 30 dB Input level Output level ≤ −60 dB +20 dB linear relative to input −60 to 0 dB −40 to −10 dB 0 COMP1 OFF -10 -20 Output(dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—8 SM5852CS Compression mode 2 (DB/DS = HIGH, MOD2 = LOW, MOD1 = HIGH) Compression Compression ratio Mode 2 19 dB Input level Output level ≤ −38 dB +15 dB linear relative to input −38 to 0 dB −23 to −4 dB 0 COMP2 OFF -10 -20 Output(dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—9 SM5852CS Compression mode 3 (DB/DS = HIGH, MOD2 = LOW, MOD1 = LOW) Compression Compression ratio Mode 3 18 dB Input level Output level ≤ −54 dB +0 dB linear relative to input −54 to −18 dB −54 to −36 dB −18 to 0 dB −36 to −18 dB 0 COMP3 OFF -10 -20 Output (dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—10 SM5852CS Compression mode 4 (DB/DS = LOW, MOD2 = HIGH, MOD1 = LOW) Compression Compression ratio Mode 4 20 dB Input level Output level ≤ −40 dB +15 dB linear relative to input −40 to 0 dB −25 to −5 dB 0 COMP4 OFF -10 -20 Output(dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—11 SM5852CS Compression mode 5 (DB/DS = LOW, MOD2 = LOW, MOD1 = HIGH) Compression Compression ratio Mode 5 15 dB Input level Output level ≤ −40 dB +15 dB linear relative to input −40 to −10 dB −25 to −10 dB −10 to 0 dB +0 dB linear relative to input 0 COMP5 OFF -10 -20 Output(dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—12 SM5852CS Compression mode 6 (DB/DS = LOW, MOD2 = LOW, MOD1 = LOW) Compression Compression ratio Mode 6 18 dB Input level Output level ≤ −54 dB +18 dB linear relative to input −54 to −18 dB −36 to −18 dB −18 to 0 dB +0 dB linear relative to input 0 COMP6 OFF -10 -20 Output(dB) -30 -40 -50 -60 -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input (dB) NIPPON PRECISION CIRCUITS—13 SM5852CS Filter Characteristics Attack-1 filter +10 0 -10 Attenuation (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 1.0 2.0 5.0 10 20 50 100 200 500 1K 2k 5k 10K 20k 100K 50k Frequency (Hz) Attack-2 filter +10 0 -10 Attenuation (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 1.0 2.0 5.0 10 20 50 100 200 500 1K 2k 5k 10K 20k 50k 100K Frequency (Hz) NIPPON PRECISION CIRCUITS—14 SM5852CS FUNCTIONAL DESCRIPTION Dynamic Range Compression Soft Muting Dynamic range compression varies the effective amplification of the input as a function of the input signal level. The mode control block selects one of 6 dynamic range compression characteristics according the states of DB/DS, MOD1 and MOD2. Also, dynamic range compression can be turned OFF, bypassing all processing. Soft muting is active when MUTEN is LOW. When MUTEN is LOW, the attenuation changes smoothly from 0 to −∞ dB in 1024/fs, or approximately 23.2 ms. DB/DS MOD2 MOD1 Compression mode LOW LOW LOW 6 LOW LOW HIGH 5 LOW HIGH LOW 4 LOW HIGH HIGH Off HIGH LOW LOW 3 HIGH LOW HIGH 2 HIGH HIGH LOW 1 HIGH HIGH HIGH Off Attack Time Selection The input interface block incorporates a peak hold circuit to determine the input level. The peak hold circuit has a time constant of τ = 250 ms, and the peak hold output is attenuated and then compared with the next input level. Therefore, the dynamic range compression recovery time constant is effectively τ = 250 ms. The attack time coefficient of the input signal, to pass through the selected attack time LPF, is determined by the input level. Two attack time low-pass filter characteristics are available, selected by the state of OPT. ■ ■ OPT = HIGH, Attack-1 characteristics, fC = 350 Hz, 2nd-order LPF (Q = 0.5) OPT = LOW, Attack-2 characteristics, fC = 150 Hz, 2nd-order LPF (Q = 0.5) When MUTEN goes HIGH, soft muting is released and the attenuation changes smoothly from −∞ to 0 dB, again taking approximately 23.2 ms. Also, if a MUTEN transition occurs while the attenuation is changing, the attenuation then changes smoothly in the direction specified by the new level of MUTEN. DB/DS, OPT Switching Shock Noise The soft muting function is also activated to eliminate switching shock noise when DB/DS or OPT change state. When DB/DS or OPT change state, the attenuation changes to −∞ dB, the internal circuit settings are activated and then soft muting is released. Therefore, a maximum time of approximately 46.4 ms is required to change the compression mode. Of course, if the attenuation is already −∞ dB after soft muting using MUTEN, then no time is required to change compression mode. Reset Initialization RSTN should be set LOW at power-ON and after reacquiring synchronization. Note that if RSTN is LOW for longer than 1 µs, a through-current flows in the LSI’s internal dynamic circuits because the internal clock is stopped. The through-current has no rated value, so the reset pulse should be kept as short as possible at all times other than at power-ON. When RSTN goes from LOW to HIGH, initialization hold is released and the initialization routine first resets the internal data over an interval of 4fs. During the initialization routine, the output data is forcibly muted so that there is no output signal. The attack time is the time required by the circuit to return to the set value after a sudden increase in the input. The recovery time is the time required by the circuit to return to the set value after a sudden decrease in the input. NIPPON PRECISION CIRCUITS—15 SM5852CS INPUT/OUTPUT TIMING Input Timing LRCI BCKI Lch MSB LSB MSB Rch LSB DI There must be a minimum of 16 BCKI clock cycles to read in a single word of data. Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement format. Output Timing LRCO BCKO DOUT ,, MSB Lch ,, ,, LSB MSB Rch ,, LSB Shaded areas represent intervals of invalid data. NIPPON PRECISION CIRCUITS—16 SM5852CS APPLICATON CIRCUIT X ' lal(16.9344 MHz) XTI XTAI DB/DS LRCI LRCK XTO CKO MOD2 BCKI SONY CXD1125 1130 1135 MOD1 C210 DI OPT SM5852CS DATA SM5871 CLK PSSL RSTN LRCO LRCI TESTN BCKO BCKI MUTEN DOUT DIN SLOB Microcontroler NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9622AE 1997.03 NIPPON PRECISION CIRCUITS—17