SM5852DS Digital Audio Processor LSI NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 DB/DS BCKI 2 15 MOD2 DI 3 14 MOD1 CLK 4 13 OPT VSS 5 12 VDD RSTN 6 11 LRCO TESTN 7 10 BCKO MUTEN 8 9 DOUT PACKAGE DIMENSIONS 16-pin SOP (Unit: mm) 0.17±0.05 SM5852DS 16pin SOP 10.16±0.3 10.5 MAX 8.0±0.3 Package 0 to 15 2.0±0.2 0.1±0.1 Device 5.5±0.3 ORDERING INFOMATION 6.8±0.3 ■ 2-channel processing XBS/LIVE functions XBS/LIVE processing bypass mode ASC function ON/OFF switching Input-level dependent dynamic gain characteristics Serial input/output interface 2s complement, MSB first, 16-bit 384fs system clock 23 × 23-bit multiplier/30-bit high-precision accumulator TTL-compatible input/output 3.2 to 5.5 V operating voltage range 16-pin SOP Molybdenum-gate CMOS 1 8.0±0.3 ■ ■ LRCI SM5852DS The SM5852DS is a digital signal processor IC that performs XBS (extra bass system), LIVE (pseudosound field) and ASC (train position) processing for use in digital audio reproduction equipment. It is designed for use with a 44.1 kHz sampling frequency. 0.635±0.15 1.27±0.15 0.4±0.15 NIPPON PRECISION CIRCUITS—1 SM5852DS BLOCK DIAGRAM LRCI BCKI DI Input data Interface VDD DSP Block CLK RSTN Sequence Control TESTN MUTEN DB/DS OPT MOD1 VSS System Clock Output data Interface LRCO BCKO DOUT Mute Control Mode Control MOD2 NIPPON PRECISION CIRCUITS—2 SM5852DS PIN DESCRIPTION Number Name I/O1 1 LRCI Ip Input data sample rate (fs) clock input 2 BCKI Ip Bit clock input 3 DI Ip Serial data input 4 CLK I Clock input 5 VSS – Ground 6 RSTN Ip System reset initialization. Reset when LOW. 7 TESTN Ip Test mode input. Testing when LOW. 8 MUTEN Ip Mute input. Muting when LOW. 9 DOUT O Serial data output 10 BCKO O Bit clock output 11 LRCO O Output data sample rate (fs) clock output 12 VDD – 3.2 to 5.5 V supply 13 OPT Ip ASC ON/OFF switch control. OFF when HIGH, and ON when LOW. 14 MOD1 Ip 15 MOD2 Ip XBS/LIVE low-pass gain select inputs. The XBS/LIVE function is bypassed when both MOD1 and MOD2 are HIGH. 16 DB/DS Ip Description LIVE ON/OFF switch control. OFF when HIGH, and ON when LOW. The LIVE function is bypassed when both MOD1 and MOD2 are HIGH. 1. Ip = Input pin with pull-up resistor. Accordingly, they can be left open for HIGH-level input. NIPPON PRECISION CIRCUITS—3 SM5852DS SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Symbol Condition Rating Unit Supply voltage V DD −0.3 to 7.0 V Input voltage V IN V SS − 0.3 to V DD + 0.3 V Storage temperature T stg −55 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Rating Unit Recommended Operating Conditions VSS = 0 V Parameter Symbol Condition Supply voltage V DD 3.2 to 5.5 V Operating temperature Topr −20 to 80 °C DC Characteristics Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Current consumption1 Input voltage for all inputs2 Output voltage for all outputs3 Symbol Condition Unit min typ max – 16 23 mA V IH 2.4 – – V V IL – – 0.5 V 2.5 – – V IDD V DD = 5.0 V VOH IOH = −0.4 mA VOL IOL = 1.6 mA – – 0.4 V Input leakage current for all inputs1 ILH V IN = V DD – – 1.0 µA CLK input leakage current ILL V IN = 0 V – – 1.0 µA Input current for all inputs except CLK IIL V IN = 0 V – – 20 µA 1. fCLK = 384fs = 16.9344 MHz, no output load, input data conformance with NPC test pattern 2. LRCI, BCKI, DI,RSTN, TESTN, MUTEN, OPT, MOD1, MOD2, DB / DS 3. LRCO, BCKO, DOUT Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Current consumption1 Input voltage for all inputs2 Symbol Condition Unit min typ max – 7 10 mA V IH 2.4 – – V V IL – – 0.5 V 2.5 – – V IDD V DD = 3.4 V VOH IOH = −0.2 mA VOL IOL = 0.8 mA – – 0.4 V Input leakage current for all inputs ILH V IN = V DD – – 1.0 µA CLK input leakage current ILL V IN = 0 V – – 1.0 µA Input current for all inputs except CLK IIL V IN = 0 V – – 12 µA Output voltage for all outputs3 1. 2. 3. fCLK = 384fs = 16.9344 MHz, no output load, input data conformance with NPC test pattern LRCI, BCKI, DI,RSTN, TESTN, MUTEN, OPT, MOD1, MOD2, DB / DS LRCO, BCKO, DOUT NIPPON PRECISION CIRCUITS—4 SM5852DS AC Characteristics Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 70 °C CLK (384fs) Rating Parameter Symbol Condition Unit min typ max Clock pulsewidth tCW 24 – 500 ns Clock cycle time tCY 55 59 1000 ns tcy VIH CLK 1.5V DD tCW VIL tCW RSTN Rating Parameter Symbol Reset LOW-level pulsewidth tRST Condition Unit min typ max At power-ON 1 – – µs At all other times 50 – 1000 ns 3.2V VDD tRST 1µsec tRST RSTN 1.5V RSTN should be set LOW at power-ON and after reacquiring synchronization. Note that if RSTN is LOW for longer than 1 µs, a through-current flows in the internal dynamic circuits because the internal clock is stopped. The through-current has no rated value, so the reset pulse should be kept as short as possible at all times other than at power-ON. NIPPON PRECISION CIRCUITS—5 SM5852DS Serial input timing Rating Parameter Symbol Condition Unit min typ max BCKI pulsewidth tBCIW 100 – – ns BCKI cycle time tBCIY 200 – – ns DI setup time tDIS 75 – – ns DI hold time tDIH 75 – – ns LRCI setup time tLIS 75 – – ns LRCI hold time tLIH 75 – – ns BCKI 1.5V tBCIW tBCIW tBCIY DI 1.5V tDIS tDIH 1.5V LRCI tLIS tLIH DB/DS, OPT Rating Parameter Minimum pulsewidth Symbol Condition tW Unit min typ max 2/fs – – ns When DB/DS or OPT change state, the input level must be constant for a minimum of 2/fs (2 × LRCI cycle time). Input levels of duration less than 2/fs may be ignored. NIPPON PRECISION CIRCUITS—6 SM5852DS Serial output timing Rating Parameter Symbol Condition Unit min typ max BCKO pulsewidth tBCOW 15 pF load 180 1/96fs – ns BCKO cycle time tBCOY 15 pF load 400 1/48fs – ns tDHL 15 pF load −20 – 60 ns tDLH 15 pF load −20 – 60 ns DOUT, LRCO output delay time 1.5V BCKO tBCOW DOUT LRCO tBCOW tBCOY 1.5V tDHL tDLH NIPPON PRECISION CIRCUITS—7 SM5852DS Filter Characteristics ASC filter frequency response (theoretical) +3 0 -3 Attenuation (dB) -6 -9 -12 -15 -18 -21 -24 -27 -30 1K 2K 5K 7K 10k 20K 50K 100K Frequency (Hz) NIPPON PRECISION CIRCUITS—8 SM5852DS XBS Gain Characteristics DB/DS = HIGH L ch. = R ch. = -35dB same phase data input 20 10 Attenuation (dB) 0 MOD1=L,MOD2=H MOD1=L,MOD2=L MOD1=H,MOD2=L MOD1=H,MOD2=H -10 -20 -30 -40 -50 -60 10 20 50 100 200 500 1K 2K 5K 10K 20K Frequency (Hz) DB/DS = LOW L ch. = R ch. = -35dB same phase data input 20 10 Attenuation (dB) 0 MOD1=L,MOD2=L MOD1=H,MOD2=H MOD1=H,MOD2=L MOD1=L,MOD2=H -10 -20 -30 -40 -50 -60 10 20 50 100 200 500 1K 2K 5K 10K 20K Frequency (Hz) NIPPON PRECISION CIRCUITS—9 SM5852DS XBS frequency response (DB/DS = HIGH) 0 -10 Ooutput (dB) -20 MOD1=L,MOD2=H MOD1=L,MOD2=L -30 -40 -50 -60 MOD1=H,MOD2=H MOD1=H,MOD2=L -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -20 -10 0 Input (dB) XBS + LIVE frequency response (DB/DS = LOW) 0 -10 Ooutput (dB) -20 MOD1=H,MOD2=L MOD1=L,MOD2=L -30 -40 -50 -60 MOD1=H,MOD2=H MOD1=L,MOD2=H -70 -80 -90 -90 -80 -70 -60 -50 -40 -30 Input (dB) NIPPON PRECISION CIRCUITS—10 SM5852DS FUNCTIONAL DESCRIPTION Signal Flow Lch. IN ASC LIVE Lch. OUT Soft Mute Rch. OUT XBS ASC Rch. IN Soft Mute ASC Function Soft Muting The ASC (train position) function uses a 7 kHz bandlimited filter to cut-off sound leakage from headphones. The ASC function is OFF when OPT is HIGH, and ON when OPT is LOW. Soft muting is active when MUTEN is LOW. When MUTEN is LOW, the attenuation changes smoothly from 0 to −∞ dB in 1024/fs, or approximately 23.2 ms. LIVE Function When MUTEN goes HIGH, soft muting is released and the attenuation changes smoothly from −∞ to 0 dB, again taking approximately 23.2 ms. The LIVE (pseudo-sound field) function emphasizes the extent of the sound field by adding an inverse phase component from the opposite channel of the input signal. When used with the XBS function, lowfrequency components of the spectrum are further emphasized. The LIVE function is OFF when DB/DS is HIGH, and ON when DB/DS is LOW. Note that the function is also OFF when both MOD1 and MOD2 are HIGH. XBS Function The XBS (extra bass system) function emphasizes the low-frequency end of the spectrum by changing the gain for low-frequency components of the input signal. The XBS gain is set by the states of MOD1 and MOD2. Note that the gain changes when the XBS function is used together with the LIVE function. DB/DS MOD1 MOD2 Maximum gain Mode LOW LOW LOW +13 dB XBS + LIVE LOW LOW HIGH 0 dB LIVE LOW HIGH LOW +4 dB XBS + LIVE LOW HIGH HIGH 0 dB Off HIGH LOW LOW +10 dB XBS HIGH LOW HIGH +13 dB XBS HIGH HIGH LOW +6 dB XBS HIGH HIGH HIGH 0 dB Off Also, if a MUTEN transition occurs while the attenuation is changing, the attenuation then changes smoothly in the direction specified by the new level of MUTEN. DB/DS, OPT Switching Shock Noise The soft muting function is also activated to eliminate switching shock noise when DB/DS or OPT change state. When DB/DS or OPT change state, the attenuation changes to −∞ dB, the internal circuit settings are activated and then soft muting is released. Therefore, a maximum time of approximately 46.4 ms is required to change the compression mode. Of course, if the attenuation is already −∞ dB after soft muting using MUTEN, then no time is required to change compression mode. Reset Initialization RSTN should be set LOW at power-ON and after reacquiring synchronization. Note that if RSTN is LOW for longer than 1 µs, a through-current flows in the LSI’s internal dynamic circuits because the internal clock is stopped. The through-current has no rated value, so the reset pulse should be kept as short as possible at all times other than at power-ON. When RSTN goes from LOW to HIGH, initialization hold is released and the initialization routine first resets the internal data over an interval of 4fs. During the initialization routine, the output data is forcibly muted so that there is no output signal. NIPPON PRECISION CIRCUITS—11 SM5852DS INPUT/OUTPUT TIMING Input Timing LRCI BCKI MSB Lch MSB LSB Rch LSB DI There must be a minimum of 16 BCKI clock cycles to read in a single word of data. Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement format. Output Timing LRCO BCKO DOUT ,, , MSB Lch ,, ,, ,, LSB MSB Rch ,, , LSB Shaded areas represent intervals of invalid data. NIPPON PRECISION CIRCUITS—12 SM5852DS APPLICATON CIRCUIT X'tal(16.9344 MHz) XTI X1 LRCI DB/DS R/L XTO CKO MOD2 BCKI MOD1 SRCK Matsushita MN6617 DI OPT SM5852DS SRDATA SM5840 CLK SEL RSTN LRCO LRCI TESTN BCKO BCKI MUTEN DOUT DIN IPSEL Microcontroller NIPPON PRECISION CIRCUITS—13 SM5852DS NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9624AE 1997.03 NIPPON PRECISION CIRCUITS—14