NTE3094 Optoisolator Dual, High Speed, Open Collector NAND Gate Description: The NTE3094 consists of a pair of inverting optically coupled gates each with a GaAsP emitting diode and a unique integrated detector. The photons are collected in the detector by a photodiode and then amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. each circuit is temperature, current and voltage compensated. This unique isolator design provides maximum DC and AC circuit isolation between input and output while achieving LSTTL/TTL circuit compatibility. The isolator operational parameters are guaranteed from 0° to +70°C, such that a minimum input current of 5mA will sink an eight gate fan–out (13mA) at the output with 5 volt VCC applied to the detector. This isolation and coupling is achieved with a typical propagation delay of 57ns. Features: D LSTTL/TTL Compatible: 5V Supply D Ultra High Speed D Low Input Current Required D High Common Mode Rejection D 3000V DC Withstand Test Voltage D Typical Data Rate 10M/Bit(s) Absolute Maximum Ratings: (TA = +25°C unless otherwise specified) Input Diode (Each Channel) Reverse Voltage, VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Forward Current, IF Average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Peak (≤ 1ms Duration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Output Transistor (Each Channel) Supply Voltage (1 Minute Maximum), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Output Current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16mA Collector Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mW Total Device Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +125°C Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), TL . . . . . . +260°C Recommended Operating Conditions: Parameter Symbol Test Conditions Min Typ Max Unit 0 – 250 µA 6.3 – 15 mA VCC 4.5 – 5.5 V Fan Out (TTL Load) N – – 8 Operating Temperature TA 0 – 70 Input Current, Low Level (Each Channel) IFL Input Current, High Level (Each Channel) IFH Supply Voltage, Output Note 1 °C Note 1. 6.3mA condition permits at least 20% CTR degradation guardband. Initial switching threshold is 5mA or less. Electrical Characteristics: (TA = 0° to +70°C, Note 2 unless otherwise specified) Parameter Symbol High Level Output Current IOH Low Level Output Voltage Test Conditions Min Typ Max Unit VCC = 5.V, VO = 5.5V, IF = 250µA, Note 3 – 40 250 µA VOL VCC = 5.5V, IF = 5mA, IOL(sinking) = 13mA, Note 3 – 0.4 0.6 V High Level Supply Current ICCH VCC = 5.V, IF = 0, (Both Channels) – 15 30 mA Low Level Supply Current ICCL VCC = 5.V, IF = 10mA, (Both Channels) – 27 36 mA Input–Output Insulation Leakage Current IIO Relative Humidity = 45%, TA = +25°C, t = 5s, VIO = 3000V DC, Note 4 – – 1.0 µA Resistance RIO VIO = 500V, TA = +25°C, Note 4 – 1012 – Ω Capacitance CIO f = 1MHz, TA = +25°C, Note 4 – 0.6 – pF Input Forward Voltage VF IF = 10mA, TA = +25°C, Note 3, Note 5 – 1.5 1.75 V IR = 10µA, TA = +25°C 5 – – V Input Reverse Breakdown Voltage V(BR)R Input Capacitance CIN VF = 0, f = 1MHz, Note 3 – 60 – pF Current Transfer Ratio CTR IF = 5mA, RL = 100Ω, Note 6 – 700 – % Resistance (Input–Input) RII VII = 500V, Note 7 – 1011 – Ω Capacitance (Input–Input) CII f = 1MHz, Note 7 – 0.27 – pF Note 2. All typicals at TA = +25°C, VCC = 5V unless otherwise specified. Note 3. Each channel. Note 4. Measured between Pin1, Pin2, Pin3 and Pin4 shorted together and Pin5, Pin6, Pin7 and Pin8 shorted together. Note 5. At 10mA, VF decreases with increasing temperature at the rate of 1.6mV/°C. Note 6. DC Current Transfer Ratio is defined as the ratio of the output collector current to the forward bias input current times 100%. Note 7. Measured between Pin1 and Pin2 shorted together and Pin3 and Pin4 shorted together. Switching Characteristics: (TA = +25°C, VCC = 5V unless otherwise specified) Parameter Symbol Propagation Delay Time tPLH tPHL Output Rise Time (10% to 90%) tr Output Fall Time (90% to 10%) tf Common Mode Transient Immunity Test Conditions IF = 7.5mA, RL = 350Ω, CL = 15pF Min Typ Note 8 – 57 75 ns Note 9 – 45 75 ns – 25 – ns – 35 – ns – 500 – V/µs – –500 – V/µs IF = 7.5mA, RL = 350Ω, CL = 15pF, Note 3 CMH IF = 0mA, VO(min) = 2V CML IF = 7.5mA, VO(max) = 0.8V VCM = 10VP–P, RL = 350Ω Ω Max Unit Note 3. Each channel. Note 8. The tPLH propagation delay is measured from the 3.75mA point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse. Note 9. The tPHL propagation delay is measured from the 3.75mA point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse. Note10. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dv cm/dt on the leading edge of the common mode pulse (VCM) to assure that the output will remain in a Logic High state (i.e. VO 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode pulse signal (VCM) to assure that the output will remain in a Logic Low state (i.e. VO 0.8V). Pin Connection Diagram 1 8 VCC 2 7 VO 1 Cathode 2 3 6 VO 2 Anode 2 4 5 GND Anode 1 Cathode 1 8 5 .250 (6.35) 1 4 .390 (9.9) Max .020 (.508) Min Seating Plane .100 (2.54) .185 (4.7) Max .115 (2.94) Min