SN74BCT756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS056B – OCTOBER 1990 – REVISED JULY 1997 D D DW OR N PACKAGE (TOP VIEW) BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers Package Options Include Plastic Small-Outline Packages (DW) and Standard Plastic 300-mil DIPs (N) D D 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND description This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74BCT756, SN74BCT757, and SN74BCT760 provide the choice of selected combinations of inverting outputs, symmetrical output-enable (OE) inputs, and complementary OE and OE inputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 The SN74BCT756 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OE A OUTPUT Y H X H L L H L H L logic symbol† 1OE 1A1 1A2 1A3 1A4 1 EN 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 1Y4 2A3 2A4 19 EN 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74BCT756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS056B – OCTOBER 1990 – REVISED JULY 1997 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 18 2 16 4 14 6 12 8 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 19 9 11 7 13 5 15 3 17 2A4 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions 2 MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VOH Low-level input voltage High-level output voltage 5.5 V IIK IOL Input clamp current –18 mA 64 mA TA Operating free-air temperature 70 °C High-level input voltage 2 V 0.8 Low-level output current 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V SN74BCT756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS056B – OCTOBER 1990 – REVISED JULY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK IOH VCC = 4.5 V, VCC = 4.5 V, II = –18 mA VOH = 5.5 V VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 64 mA VI = 7 V IIH IIL VCC = 5.5 V, VCC = 5.5 V, VI = 2.7 V VI = 0.5 V ICC VCC = 5.5 V, Outputs open Ci Co VCC = 5 V, VCC = 5 V, MIN TYP† 0.42 MAX UNIT –1.2 V 0.1 mA 0.55 V 0.1 mA 20 µA –1 mA Outputs high 21 33 Outputs low 55 86 OE disable 6 10 VI = 2.5 V or 0.5 V VI = 2.5 V or 0.5 V mA 6 pF 10 pF † All typical values are at VCC = 5 V, TA = 25°C. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPLH tPHL OE Y VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C MIN TYP MAX VCC = 4.5 to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX‡ MIN MAX 6.2 8.5 10.5 6.2 11.3 0.5 2 4.1 0.5 4.2 8.2 12.5 14.8 8.2 16.5 3.4 6.8 9.2 3.4 10.3 UNIT ns ns ‡ For conditions as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74BCT756 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS056B – OCTOBER 1990 – REVISED JULY 1997 PARAMETER MEASUREMENT INFORMATION 7V (tPZL, tPLZ, O.C.) S1 Open (all others) R1 Test Point From Output Under Test CL (see Note A) R2 RL = R1 = R2 LOAD CIRCUIT 3V 1.5 V Timing Input 0V 1.5 V tw 3V 1.5 V 1.5 V 0V 3V Low-Level Pulse 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V VOL Out-of-Phase Output tPLZ 3.5 V 1.5 V tPHZ tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0V Output Waveform 1 (see Note B) tPLH tPHL 3V 1.5 V tPZL VOH In-Phase Output Output Control (low-level enable) tPHL tPLH 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V th tsu Data Input 3V High-Level Pulse Output Waveform 2 (see Note B) VOL 0.3 V 0.3 V VOH 1.5 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated