SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 D D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE description 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE This 16-bit buffer/driver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC162244 is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. The outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVC162244 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 logic symbol† 1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1 48 25 24 47 logic diagram (positive logic) 1OE EN1 EN2 1A1 EN3 EN4 1A2 1 1 2 46 3 44 5 43 6 41 8 1 2 40 9 38 11 37 12 36 13 1 3 35 14 33 16 32 17 30 19 1 4 29 20 27 22 26 23 1Y1 1Y2 1A3 1Y3 1Y4 1A4 47 2 46 3 44 5 43 6 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2OE 48 2Y3 2Y4 2A1 41 8 40 9 38 11 37 12 2Y1 3Y1 3Y2 2A2 2Y2 3Y3 3Y4 2A3 2Y3 4Y1 4Y2 2A4 2Y4 4Y3 4Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 3OE 3A1 3A2 3A3 3A4 4OE 4A1 4A2 4A3 4A4 2 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO Output voltage 0 High-level input voltage VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V IOH High level output current High-level VCC = 2.7 V VCC = 3 V IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆V Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 UNIT V V 0.8 V VCC VCC V –8 – 12 8 12 V mA mA 0 10 ns / V – 40 85 °C 3 SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = – 100 µA IOH = – 6 mA, VOH IOH = – 8 mA, IOH = – 12 mA, IOL = 100 µA IOL = 6 mA, VOL 3 2 VIH = 2 V 3 2 nICC 0.55 2.7 0.6 3 0.8 ±5 3.6 One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND UNIT 0.2 3 VIL = 0.8 V VO = VCC or GND VI = VCC or GND, MAX V MIN to MAX VI = 2 V VI = 0 to 3.6 V IOZ ICC TYP‡ VCC – 0.2 2.4 2.7 VI = VCC or GND VI = 0.8 V II(hold) ( ) MIN VIH = 2 V VIH = 2 V VIL = 0.8 V VIL = 0.8 V IOL = 8 mA, IOL = 12 mA, II VCC† MIN to MAX TEST CONDITIONS 3 75 3 – 75 V µA µA 3.6 ± 500 3.6 ± 10 µA 3.6 20 µA 2.7 V to 3.6 V 500 µA Ci Control inputs VI = VCC or GND 3.3 Co A or B ports VO = VCC or GND 3.3 † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 2.5 pF 3.5 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN MAX FROM (INPUT) TO (OUTPUT) tpd A Y 1.5 7 1.5 8 ns ten OE Y 1.5 9 1.5 10 ns tdis OE Y 1.5 7 1.5 8 ns PARAMETER UNIT operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d 4 Power dissipation capacitance per buffer/driver TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 50 pF, pF f = 10 MHz TYP 20 2 UNIT pF SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545 – OCTOBER 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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