SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 D D D D Compatible With IEEE Std 1194.1-1991 (BTL) TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Minimizes Signal Distortion During Live Insertion or Withdrawal D D D D High-Impedance State During Power Up and Power Down B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage TTL-Input Structures Incorporate Active Clamping to Aid in Line Termination Packaged in Plastic High-Power Low-Profile Quad Flatpack 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1AI5 1AO5 1AI4 1AO4 GND 1AI3 1AO3 1AI2 1AO2 GND 1AI1 1AO1 VCC 1OEA 1OEA 1LEBA 1CLKBA 1CLKAB 1LEAB 1OEB 1OEB BG GND BG VCC GND 1B1 PCA PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1B2 GND 1B3 1B4 GND 1B5 1B6 GND 1B7 1B8 GND 1B9 NC 2CLKAB GND 2B2 2B3 GND 2B4 2B5 GND 2B6 2B7 GND 2B8 2AO5 2AI5 2AO6 2AI6 GND 2AO7 2AI7 2AO8 2AI8 GND 2AO9 2AI9 VCC 2OEA 2OEA 2LEBA 2CLKBA 2CLKAB 2LEAB 2OEB 2OEB BIAS VCC NC GND 2B9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VCC GND 1AO6 1AI6 1AO7 1AI7 GND 1AO8 1AI8 1AO9 1AI9 GND 2CLK NC 2AO2 2AI2 GND 2AO3 2AI3 2AO4 2AI4 GND VCC NC NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 description The SN74FB1651 device contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and the transceivers are designed to translate signals between TTL and backplane transceiver-logic (BTL) environments. It is designed specifically to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V, the B port is turned off. The A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the high-impedance state. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. BG VCC and BG GND are the supply inputs for the bias generator. The SN74FB1651 is characterized for operation from 0°C to 70°C. Function Tables TRANSCEIVER INPUTS OEA FUNCTION OEA OEB OEB X X H L A data to B bus L H X X B data to A bus A data to B bus, B data to A bus L H H L X X L X X X X H H X X X X L X X B bus isolation B-bus A bus isolation A-bus STORAGE MODE INPUTS 2 FUNCTION LE CLK H X Transparent L ↑ Store data L L Storage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 functional block diagram 81 1OEB 80 1OEB 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEA 1OEA 1AI1 83 82 85 84 87 86 Transceiver 90 1D C2 76 1B1 C1 89 1AO1 1D C2 C1 To Eight Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 functional block diagram (continued) 45 2OEB 2OEB 2CLKAB 2LEAB 2LEBA 2CLKBA 2OEA 2OEA 46 43 44 41 42 39 40 62 Delay 2CLK 14 2CLKAB Delay Transceiver 2AI2 17 1D C2 C1 2AO2 16 1D C2 C1 To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 2B2 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) VCC, BG VCC, BIAS VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current IOL Low level output current Low-level B port Except B port B port Except B port High-level output current A port MIN NOM MAX 4.5 5 5.5 1.62 2.3 2 0.75 1.47 0.8 UNIT V V V –18 mA –3 mA A port 24 B port 100 mA TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK VOH VOL II IIH‡ IIL‡ B port Except B port AO port VCC = 4 4.5 5V IOH = –1 mA IOH = –3 mA 2.5 AO port VCC = 4.5 V, IOL = 24 mA IOL = 80 mA 0.75 B port 5V VCC = 4 4.5 Except B port VCC = 5.5 V, VCC = 5.5 V, Except B port Except B port B port AO port IOZPU IOZPD AO port IOH IOS§ B port AO port A port A port to B port B port to A port AO ports –0.5 0.35 V 0.5 1.1 V 1.15 50 µA 50 µA –50 –100 µA 50 µA VO = 0.5 V VO = 0.5 V to 2.7 V –50 µA 50 µA VO = 0.5 V to 2.7 V VO = 2.1 V –50 µA VO = 0 VCC = 5 5.5 5V V, UNIT V 3.3 VI = 0.75 V VO = 2.7 V VCC = 0 to 5.5 V, VCC = 5.5 V, Control inputs Co VCC = 5.5 V, VCC = 5.5 V, MAX –1.2 VI = 2.7 V VI = 0.5 V VCC = 0 to 2.1 V, VCC = 2.1 V to 0, AO port TYP† IOL = 100 mA VI = 5.5 V VCC = 5.5 V, VCC = 5.5 V, AI port Ci MIN II = –18 mA II = –40 mA IOZH IOZL ICC TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, –30 100 µA –150 mA 100 IO = 0 120 5.5 VI = 0.5 0 5 V or 2.5 25V pF 5.5 VO = 0.5 V or 2.5 V 5.5 VCC = 0 to 5.5 V Cio B port per IEEE Std 1194.1-1991 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. mA pF 5.5 pF live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO 6 B port B port TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V VB = 0 to 2 V, V VI (BIAS VCC) = 4.5 4 5 V to 5.5 55V VCC = 0, VCC = 0 , VI (BIAS VCC) = 5 V VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MIN MAX 450 10 µA 2.1 V OEB = 0 to 0.8 V 100 µA OEB = 0 to 5 V 100 POST OFFICE BOX 655303 1.62 UNIT • DALLAS, TEXAS 75265 –1 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN fclock tw Clock frequency 150 Pulse duration tsu Setup time th Hold time MIN POST OFFICE BOX 655303 CLK or LE 3.3 3.3 Data before LE 4.8 4.8 Data before CLK↑ 4.9 4.6 Data after LE 1.8 1.8 Data after CLK↑ 1.1 1.1 • DALLAS, TEXAS 75265 MAX UNIT 150 MHz MAX ns ns ns 7 SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tsk(p)† tsk(p)‡ tsk(o)‡ tt Transition time† FROM (INPUT) TO (OUTPUT) MIN TYP MIN AI B LEAB B CLKAB B 2CLKAB 2CLKAB B AO LEBA AO CLKBA AO 2CLKAB 2CLK OEB B OEB B OEA AO OEA AO OEA AO OEA AO MAX UNIT MAX 150 150 MHz 1.8 3.7 5.3 1.8 6.2 2.9 4.4 6 2.9 6.6 2.7 4.2 5.8 2.7 6.4 3.5 5 6.5 3.5 7.3 2.3 3.9 5.5 2.3 6 2.9 4.5 6.1 2.9 6.7 4.6 6.9 8.8 4.6 9.9 4.9 6.5 8.1 4.9 8.8 3.5 5.9 7.9 3.5 8 2.2 3.7 5.3 2.2 5.7 1.8 3.2 4.6 1.8 5.1 1.7 3 4.4 1.7 4.7 1.8 3.1 4.6 1.8 5.1 1.7 3.1 4.6 1.7 4.9 6.4 9.7 11.8 6.4 13.4 4.1 6.9 8.9 4.1 10.3 2.7 4.6 6.4 2.7 6.7 2.9 4.1 5.9 2.9 6.6 2.6 4.3 6.2 2.6 6.6 3.4 4.6 6.4 3.4 7 1.4 2.9 4.4 1.4 4.9 1.4 2.6 4 1.4 4.6 1.7 3.4 5.1 1.7 5.8 2.2 3.6 5 2.2 5.5 1.7 3.3 4.7 1.7 5.5 1.7 3.1 4.4 1.7 5.1 1.5 2.9 4.5 1.5 5.1 2 3.1 4.6 2 4.8 Pulse skew, CLK to B and 2CLKAB ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Pulse skew, CLK to B Pulse skew, AI to B or B to AO 1 ns Pulse skew, AI to B or B to AO 0.5 ns B outputs (1.3 V to 1.8 V) 0.9 1.7 0.5 4.6 AO outputs (10% to 90%) 0.5 2 0.4 4.2 B-port input pulse rejection † Skew values are applicable for CLK mode only. ‡ Skew values are applicable for through mode only. 8 VCC = 5 V, TA = 25°C POST OFFICE BOX 655303 1 • DALLAS, TEXAS 75265 1 ns ns SN74FB1651 17-BIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE SCBS177L – OCTOBER 1993 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) Test Point From Output Under Test CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR B OUTPUTS tw 3V 1.5 V Input 1.5 V 3V 1.5 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th 3V 3V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V tPHL tPLH 1.55 V 1.55 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOH Output VOL 3V Output Control tPZL 2V 1.55 V 1.55 V 1V tPHL 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPLH VOH Output 1.5 V 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A TO B) Input 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B TO A) Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A PORT) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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