OKI MSC2323258A

¡ Semiconductor
MSC2323258A-xxBS4/DS4
¡ Semiconductor
MSC2323258A-xxBS4/DS4
2,097,152-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
1
DESCRIPTION
The Oki MSC2323258A-xxBS4/DS4 is a fully decoded 2,097,152-word ¥ 32-bit CMOS dynamic
random access memory composed of two 16-Mb (1M ¥ 16) DRAMs in SOJ. The mounting of two
DRAMs together with decoupling capacitors on a 72-pin glass epoxy SIMM Package supports
any application where high density and large capacity of storage memory are required.
FEATURES
• 2,097,152-word ¥ 32-bit organization
• 72-pin SIMM
MSC2323258A-xxBS4 : Gold tab
MSC2323258A-xxDS4 : Solder tab
• Single 5 V supply ±10% tolerance
• Input
: TTL compatible
• Output : TTL compatible, 3-state, nonlatch
• Refresh : 1024 cycles/16 ms
• CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
• Fast Page Mode with EDO capability
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
Power Dissipation
Cycle Time
Operating (Max.) Standby (Max.)
(Min.)
MSC2323258A-60BS4/DS4
60 ns
30 ns
15 ns
110 ns
2475 mW
MSC2323258A-70BS4/DS4
70 ns
35 ns
20 ns
130 ns
2255 mW
22 mW
77
MSC2323258A-xxBS4/DS4
¡ Semiconductor
PIN CONFIGURATION
MSC2323258A-xxBS4/DS4
(Unit : mm)
*1
107.95 ±0.2
101.19 Typ.
3.38 Typ.
9.3 Max.
f 3.18
19.0 ±0.2
Typ. Typ.
10.16 6.35
72
1
2.03 Typ.
6.0 Min.
R1.57
6.35
1.27 ±0.2
6.35 Typ.
+0.1
1.27 –0.08
1.04 Typ.
95.25
*1 The common size difference of the board width 12.5 mm of its height is
specified as ±0.2. The value above 12.5 mm is specified as ±0.5.
Pin No. Pin Name
Pin No. Pin Name
Pin No. Pin Name
Pin No. Pin Name
Pin No. Pin Name
1
VSS
16
A4
31
A8
46
NC
61
DQ13
2
DQ0
17
A5
32
A9
47
WE
62
DQ30
3
DQ16
18
A6
33
RAS3
48
NC
63
DQ14
4
DQ1
19
NC
34
RAS2
49
DQ8
64
DQ31
5
DQ17
20
DQ4
35
NC
50
DQ24
65
DQ15
6
DQ2
21
DQ20
36
NC
51
DQ9
66
NC
7
DQ18
22
DQ5
37
NC
52
DQ25
67
PD1
8
DQ3
23
DQ21
38
NC
53
DQ10
68
PD2
9
DQ19
24
DQ6
39
VSS
54
DQ26
69
PD3
10
VCC
25
DQ22
40
CAS0
55
DQ11
70
PD4
11
NC
26
DQ7
41
CAS2
56
DQ27
71
NC
12
A0
27
DQ23
42
CAS3
57
DQ12
72
VSS
13
A1
28
A7
43
CAS1
58
DQ28
14
A2
29
NC
44
RAS0
59
VCC
15
A3
30
Vcc
45
RAS1
60
DQ29
Presence Detect Pins
Pin No.
78
Pin Name
MSC2323258A
MSC2323258A
-60BS4/DS4
-70BS4/DS4
67
PD1
NC
NC
68
PD2
NC
NC
69
PD3
NC
VSS
70
PD4
NC
NC
¡ Semiconductor
MSC2323258A-xxBS4/DS4
BLOCK DIAGRAM
1
A0 - A9
CAS0
CAS1
WE
RAS0
A0 - A9
DQ0
DQ0
DQ0
A0 - A9
RAS
DQ1
DQ1
DQ1
RAS
LCAS
DQ2
DQ2
DQ2
LCAS
UCAS
UCAS
WE
WE
OE
DQ15
DQ15
VSS VCC
RAS2
OE
DQ15
VCC VSS
A0 - A9
DQ0
DQ16
DQ0
A0 - A9
RAS
DQ1
DQ17
DQ1
RAS
LCAS
DQ2
DQ18
DQ2
LCAS
UCAS
RAS3
UCAS
WE
OE
RAS1
WE
DQ15
VSS VCC
DQ31
DQ15
OE
VCC VSS
CAS2
CAS3
VCC
C1
C8
VSS
79
MSC2323258A-xxBS4/DS4
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
–1.0 to 7.0
V
Voltage VCC Supply Relative to VSS
VCC
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
4
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–40 to 125
°C
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
(Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
—
27
pF
Input Capacitance (WE)
CIN2
—
35
pF
Input Capacitance (RAS0 - RAS3)
CIN3
—
13
pF
Input Capacitance (CAS0 - CAS3)
CIN4
—
20
pF
I/O Capacitance (DQ0 - DQ31)
CDQ
—
20
pF
Parameter
Input Capacitance (A0 - A9)
Note :
80
Capacitance measured with Boonton Meter.
¡ Semiconductor
MSC2323258A-xxBS4/DS4
DC Characteristics
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
MSC2323258A
Parameter
Symbol
Condition
MSC2323258A
-70BS4/DS4
-60BS4/DS4
ILI
All other pins not
1
Max.
Min.
Max.
–40
40
–40
40
µA
–20
20
–20
20
µA
0 V £ VI £ 6.5 V;
Input Leakage Current
Unit Note
Min.
under test = 0 V
DOUT disable
Output Leakage Current
ILO
Output High Voltage
VOH
IOH = –5.0 mA
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL
IOL = 4.2 mA
0
0.4
0
0.4
V
—
450
—
410
mA
1, 2
—
8
—
8
mA
1
—
4
—
4
mA
1
—
450
—
410
mA
1, 2
—
450
—
410
mA
1, 2
—
450
—
410
mA
1, 3
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current (Standby)
ICC2
tRC = Min.
RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3
CAS = VIH,
tRC = Min.
(RAS-only Refresh)
RAS cycling,
Average Power
Supply Current
RAS, CAS cycling,
RAS, CAS = VIH
Average Power
Supply Current
0 V £ VO £ 5.5 V
ICC6
CAS before RAS,
(CAS before RAS Refresh)
tRC = Min.
Average Power
RAS = VIL,
Supply Current
(Fast Page Mode)
Notes:
ICC7
CAS cycling,
tHPC = Min.
1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
81
MSC2323258A-xxBS4/DS4
¡ Semiconductor
AC Characteristics (1/2)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
MSC2323258A
MSC2323258A
-60BS4/DS4
Min.
Max.
-70BS4/DS4
Min.
Max.
Note 1,2,3
Unit Note
Random Read or Write Cycle Time
tRC
110
—
130
—
ns
Fast Page Mode Cycle Time
tHPC
25
—
30
—
ns
Access Time from RAS
tRAC
—
60
—
70
ns
4, 5, 6
Access Time from CAS
tCAC
—
15
—
20
ns
4, 5
Access Time from Column Address
tAA
—
30
—
35
ns
4, 6
Access Time from CAS Precharge
tCPA
—
35
—
40
ns
4
4
Output Low Impedance Time from CAS
tCLZ
0
—
0
—
ns
Output Hold Time from CAS Low
tDOH
5
—
5
—
ns
CAS to Data Output Buffer Turn-off Delay Time
tCEZ
0
15
0
15
ns
7, 8
RAS to Data Output Buffer Turn-off Delay Time
tREZ
0
15
0
15
ns
7, 8
WE to Data Output Buffer Turn-off Delay Time
tWEZ
0
15
0
15
ns
7
Transition Time
tT
3
50
3
50
ns
3
Refresh Period
tREF
—
16
—
16
ms
RAS Precharge Time
tRP
40
—
50
—
ns
RAS Pulse Width
tRAS
60
10k
70
10k
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100k
70
100k
ns
RAS Hold Time
tRSH
15
—
20
—
ns
CAS Precharge Time
tCP
10
—
10
—
ns
CAS Pulse Width
tCAS
10
10k
10
10k
ns
RAS Low to CAS High Delay Time
tCSH
40
—
45
—
ns
CAS High to RAS Low Delay Time
tCRP
5
—
5
—
ns
RAS Hold Time from CAS Precharge
tRHCP
35
—
40
—
ns
RAS to CAS Delay Time
tRCD
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
ns
6
RAS to Second CAS Delay Time
tRSCD
60
—
70
—
ns
Row Address Set-up Time
tASR
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
ns
Column Address Hold Time
tCAH
15
—
15
—
ns
Column Address Hold Time from RAS
tAR
40
—
45
—
ns
Column Address to RAS Lead Time
tRAL
30
—
35
—
ns
82
¡ Semiconductor
MSC2323258A-xxBS4/DS4
AC Characteristics (2/2)
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
MSC2323258A
MSC2323258A
-60BS4/DS4
Min.
Max.
-70BS4/DS4
Min.
Max.
Note 1,2,3
Unit Note
1
Read Command Set-up Time
tRCS
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
ns
9
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
ns
9
Write Command Set-up Time
tWCS
0
—
0
—
ns
Write Command Hold Time
tWCH
10
—
15
—
ns
Write Command Hold Time from RAS
tWCR
40
—
45
—
ns
Write Command Pulse Width
tWP
10
—
15
—
ns
Write Command Pulse Width (Output Disable) tWPE
5
—
10
—
ns
Write Command to RAS Lead Time
tRWL
15
—
20
—
ns
Write Command to CAS Lead Time
tCWL
15
—
20
—
ns
Data-in Set-up Time
tDS
0
—
0
—
ns
Data-in Hold Time
tDH
15
—
15
—
ns
Data-in Hold Time from RAS
tDHR
40
—
45
—
ns
CAS Active Delay Time from RAS Precharge tRPC
5
—
5
—
ns
RAS to CAS Set-up Time (CAS before RAS) tCSR
5
—
5
—
ns
RAS to CAS Hold Time (CAS before RAS)
10
—
15
—
ns
tCHR
83
MSC2323258A-xxBS4/DS4
Notes:
¡ Semiconductor
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.) and tWEZ (Max.) define the time at which the output achieves
the open circuit condition and are not referenced to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
See ADDENDUM H for AC Timing Waveforms
84