This version: Mar. 6. 2000 Semiconductor MSC23Q836D-xxBS18/DS18 8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23Q836D-xxBS18/DS18 is an 8,388,608-word x 36-bit CMOS dynamic random access memory module which is composed of sixteen 16Mb DRAMs (4Mx4) in SOJ packages and two 16Mb DRAMs (4/CAS 4Mx4) in SOJ packages mounted with eighteen decoupling capacitors. This is a 72-pin single in-line memory module. This module supports any application where high density and large capacity of storage memory are required. FEATURES • 8,388,608-word x 36-bit organization • 72-pin Single In-Line Memory Module MSC23Q836D-xxBS18 : Gold tab MSC23Q836D-xxDS18 : Solder tab • Single 5V power supply, ±10% tolerance • Input : TTL compatible • Output : TTL compatible, 3-state • Refresh : 2048cycles/32ms • Fast page mode capability • /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability • Multi-bit test mode capability PRODUCT FAMILY Access Time (Max.) Power Dissipation (Max.) tRAC tAA tCAC Cycle Time (Min.) MSC23Q836D-60BS18/DS18 60ns 30ns 15ns 110ns 4703mW MSC23Q836D-70BS18/DS18 70ns 35ns 20ns 130ns 4455mW Family Operating Standby 99mW 1/9 Semiconductor MSC23Q836D MODULE OUTLINE (Unit : mm) MSC23Q836D-xxBS18/DS18 9.30Max. 107.95±0.2*1 101.19Typ. 3.38Typ. 2.03Typ. 72 1.27±0.1 R1.57 6.35Typ. 6.35 95.25 1.04Typ. 5.71Min. 1 3.17Min. 6.35Typ. 25.4±0.2 10.16Typ. φ3.18 +0.1 1.27 −0.08 Note: 1. Tolerance over 12.5mm from board edge is ±0.5. 2/9 Semiconductor MSC23Q836D PIN CONFIGURATION Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 19 A10 37 DQ17 55 DQ12 2 DQ0 20 DQ4 38 DQ35 56 DQ30 3 DQ18 21 DQ22 39 VSS 57 DQ13 4 DQ1 22 DQ5 40 /CAS0 58 DQ31 5 DQ19 23 DQ23 41 /CAS2 59 VCC 6 DQ2 24 DQ6 42 /CAS3 60 DQ32 7 DQ20 25 DQ24 43 /CAS1 61 DQ14 8 DQ3 26 DQ7 44 /RAS0 62 DQ33 9 DQ21 27 DQ25 45 /RAS1 63 DQ15 10 VCC 28 A7 46 NC 64 DQ34 11 NC 29 NC 47 /WE 65 DQ16 12 A0 30 VCC 48 NC 66 NC 13 A1 31 A8 49 DQ9 67 PD1 14 A2 32 A9 50 DQ27 68 PD2 15 A3 33 /RAS3 51 DQ10 69 PD3 16 A4 34 /RAS2 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQ11 71 NC 18 A6 36 DQ8 54 DQ29 72 VSS Presence Detect Pins Pin No. Pin Name -60 -70 67 PD1 NC NC 68 PD2 VSS VSS 69 PD3 NC VSS 70 PD4 NC NC 3/9 Semiconductor MSC23Q836D BLOCK DIAGRAM /RAS0 /CAS0 /RAS1 /RAS /CAS DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ DQ DQ DQ DQ DQ DQ DQ DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ DQ9 DQ10 DQ11 DQ12 DQ DQ DQ DQ DQ DQ DQ DQ DQ13 DQ14 DQ15 DQ16 DQ DQ DQ DQ /RAS /CAS0 DQ0 /CAS1 D8 DQ1 /CAS2 DQ2 /CAS3 DQ3 DQ8 DQ17 DQ26 DQ35 /RAS DQ0 /CAS0 DQ1 D17 /CAS1 DQ2 /CAS2 DQ3 /CAS3 DQ DQ DQ DQ DQ18 DQ19 DQ20 DQ21 DQ DQ DQ DQ DQ DQ DQ DQ DQ22 DQ23 DQ24 DQ25 DQ DQ DQ DQ DQ DQ DQ DQ DQ27 DQ28 DQ29 DQ30 DQ DQ DQ DQ DQ DQ DQ DQ DQ31 DQ32 DQ33 DQ34 DQ DQ DQ DQ D0 /RAS /CAS D1 /RAS /CAS D9 /RAS /CAS D10 /CAS1 /RAS /CAS D2 /RAS /CAS D3 /RAS /CAS D4 /RAS /CAS D5 /RAS /CAS D11 /RAS /CAS D12 /RAS /CAS D13 /RAS /CAS D14 /CAS2 /RAS /CAS D6 /RAS /CAS D7 /CAS3 /RAS2 D15 /RAS /CAS D16 /RAS3 A0-A10 /WE A0-A10 : D0-D17 /WE : D0-D17 VCC VSS /RAS /CAS VCC : D0-D17 C0-C17 VSS & /OE : D0-D17 4/9 Semiconductor MSC23Q836D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VT −0.5 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD * 18 W Operating Temperature TOPR 0 to 70 °C Storage Temperature TSTG −40 to 125 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 VCC + 0.5 V Input Low Voltage VIL −0.5 0.8 V Power Supply Voltage Capacitance (VCC = 5V ±10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A10) CIN1 125 pF Input Capacitance (/WE) CIN2 140 pF Input Capacitance (/RAS0 - /RAS3) CIN3 43 pF Input Capacitance (/CAS0 - /CAS3) CIN4 50 pF I/O Capacitance (DQ0 - DQ35) CI/O 26 pF 5/9 Semiconductor MSC23Q836D DC Characteristics (VCC = 5V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition -60 -70 Unit Min. Max. Min. Max. 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 V Note Output High Voltage VOH IOH = −5.0mA Output Low Voltage VOL IOL = 4.2mA Input Leakage Current ILI 0V ≤ VIN ≤ 6.5V; All other pins not under test = 0V −180 180 −180 180 µA Output Leakage Current ILO DQ disable 0V ≤ VOUT ≤ VCC −20 20 −20 20 µA Average Power Supply Current (Operating) ICC1 /RAS, /CAS cycling, tRC = Min. 855 810 mA 1, 2 /RAS, /CAS = VIH 36 36 /RAS, /CAS ≥ VCC − 0.2V 18 18 mA 1 Power supply current (Standby) ICC2 Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = Min. 855 810 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 /RAS cycling, /CAS before /RAS 855 810 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, tPC = Min. 675 630 mA 1, 3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH. 6/9 Semiconductor MSC23Q836D AC Characteristics (1/2) (VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 9, 10 Parameter Symbol -60 -70 Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time tRC 110 130 ns Fast Page Mode Cycle Time tPC 40 45 ns Access Time from /RAS tRAC 60 70 ns 4, 5, 6 Access Time from /CAS tCAC 15 20 ns 4, 5 Access Time from Column Address tAA 30 35 ns 4, 6 Access Time from /CAS Precharge tCPA 35 40 ns 4 Output Low Impedance Time from /CAS tCLZ 0 0 ns 4 /CAS to Data Output Buffer Turn-off Delay Time tOFF 0 15 0 20 ns 7 Transition Time tT 3 50 3 50 ns 3 Refresh Period tREF 32 32 ms /RAS Precharge Time tRP 40 50 ns /RAS Pulse Width tRAS 60 10K 70 10K ns /RAS Pulse Width (Fast Page Mode) tRASP 60 100K 70 100K ns /RAS Hold Time tRSH 15 20 ns /CAS Precharge Time (Fast Page Mode) tCP 10 10 ns /CAS Pulse Width tCAS 15 10K 20 10K ns /CAS Hold Time tCSH 60 70 ns /CAS to /RAS Precharge Time tCRP 5 5 ns /RAS Hold Time from /CAS Precharge tRHCP 35 40 ns /RAS to /CAS Delay Time tRCD 20 45 20 50 ns 5 /RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6 Row Address Set-up Time tASR 0 0 ns Row Address Hold Time tRAH 10 10 ns Column Address Set-up Time tASC 0 0 ns Column Address Hold Time tCAH 10 15 ns Column Address to /RAS Lead Time tRAL 30 35 ns Read Command Set-up Time tRCS 0 0 ns Read Command Hold Time tRCH 0 0 ns 8 Read Command Hold Time referenced to /RAS tRRH 0 0 ns 8 7/9 Semiconductor MSC23Q836D AC Characteristics (2/2) (VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 9, 10 Parameter Symbol -60 -70 Min. Max. Min. Max. Unit Write Command Set-up Time tWCS 0 0 ns Write Command Hold Time tWCH 10 15 ns Write Command Pulse Width tWP 10 10 ns Write Command to /RAS Lead Time tRWL 15 20 ns Write Command to /CAS Lead Time tCWL 15 20 ns Data-in Set-up Time tDS 0 0 ns Data-in Hold Time tDH 10 15 ns /CAS Active Delay Time from /RAS Precharge tRPC 5 5 ns /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR 10 10 ns /RAS to /CAS Hold Time (/CAS before /RAS) tCHR 10 10 ns /WE to /RAS Precharge Time (/CAS before /RAS) tWRP 10 10 ns /WE Hold Time from /RAS (/CAS before /RAS) tWRH 10 10 ns /RAS to /WE Set-up Time (Test Mode) tWTS 10 10 ns /RAS to /WE Hold Time (Test Mode) tWTH 10 10 ns Note 8/9 Semiconductor MSC23Q836D Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 5ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tOFF(Max.) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS only refresh or /CAS before /RAS refresh cycle. 10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 9/9