OKI MSM54V25632A

E2L0068-19-61
¡ Semiconductor
MSM54V25632A
¡ Semiconductor
This version:
Jun. 1999
MSM54V25632A
Previous version: Sep. 1998
131,072-Word ¥ 32-Bit ¥ 2-Bank Synchronous Graphics RAM
DESCRIPTION
The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words
¥ 32 bits ¥ 2 banks.
This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column
Block Write function and Write per bit function which improves performance in graphics
systems.
FEATURES
• 131,072 words ¥ 32 bits ¥ 2 banks memory
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible inputs and outputs
• All input signals are latched at rising edge of system clock
• Auto precharge and controlled precharge
• Internal pipelined operation: column address can be changed every clock cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Independent byte operation via DQM0 to DQM3
• 8-column Block Write function
• Persistent write per bit function
• Programmable burst sequence (Sequential/Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (1, 2 and 3)
• Burst stop function (full-page burst)
• Power Down operation and Clock Suspend operation
• Auto refresh and self refresh capability
• 1,024 refresh cycles/16 ms
• Package:
100-pin plastic QFP
(QFP100-P-1420-0.65-BK4)
(Product : MSM54V25632A-xxAGBK4)
xx indicates speed rank.
PRODUCT FAMILY
Family
Clock Frequency
MHz (Max.)
MSM54V25632A-10
100
MSM54V25632A-12
83
Package
100-pin Plastic QFP (14 ¥ 20 mm)
1/66
¡ Semiconductor
MSM54V25632A
82 VSSQ
81 DQ29
84 DQ31
83 DQ30
86 NC
85 VSS
88 NC
87 NC
90 NC
89 NC
92 NC
91 NC
96 VCC
95 NC
94 NC
93 NC
80 DQ28
79 VCCQ
1
2
78 DQ27
77 DQ26
3
4
76 VSSQ
75 DQ25
5
6
74 DQ24
73 VCCQ
7
8
72 DQ15
71 DQ14
9
10
70 VSSQ
69 DQ13
11
12
68 DQ12
67 VCCQ
13
14
66 VSS
65 VCC
15
16
18
64 DQ11
63 DQ10
19
20
62 VSSQ
61 DQ9
21
60 DQ8
59 VCCQ
17
22
58 NC
57 DQM3
23
24
56 DQM1
55 CLK
25
26
54 CKE
53 DSF
27
28
52 NC
51 A8
29
49
50
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A0
A1
A2
A3
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
A4
A5
A6
A7
32
30
31
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VCCQ
VCC
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VCCQ
DQM0
DQM2
WE
CAS
RAS
CS
BA (A9)
NC
98 DQ1
97 DQ0
100 DQ2
99 VSSQ
PIN CONFIGURATION (TOP VIEW)
100-Pin Plastic QFP
Pin Name
Function
Pin Name
Address Inputs
A0 - A8
Row Address Inputs
DSF
Special Function Enable
A0 - A7
Column Address Inputs
CKE
Clock Enable
Bank Address
CLK
System Clock Input
Data Inputs/Outputs
VCC
Supply Voltage
A9
DQ0 - DQ31
CS
Note:
Function
A0 - A9
Chip Select
DQM0 - DQM3
VSS
DQ Mask Enable
Ground
RAS
Row Address Strobe
VCCQ
Supply Voltage for DQ
CAS
Column Address Strobe
VSSQ
Ground for DQ
WE
Write Enable
NC
No Connection
The same power supply voltage must be provided to every VCC pin and VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
2/66
¡ Semiconductor
MSM54V25632A
BLOCK DIAGRAM
A9
Row Decoders
Timing
Generator
4Mb
Memory Cells
Bank - A
VCC
VSS
Sense Amplifiers
32
Column Decoders
Row Decoders
A0
A1
A2
Address Buffers
Refresh
Counter
I/O Buffers
4Mb
Memory Cells
Bank - B
Sense Amplifiers
Column Decoders
CLK
CKE
CS
RAS
CAS
WE
DSF
32
32
DQ0 to 31
DQM0 to 3
Color
Register
(32 bits)
Mask
Register
(32 bits)
3/66
¡ Semiconductor
MSM54V25632A
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA8
Column address: CA0 – CA7
BA (A9)
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9 = "L" : Bank A, A9 = "H" : Bank B
RAS
CAS
Functionality depends on the combination. For details, see the function truth table.
WE
DSF
DSF is part of the inputs of graphics command of the MSM54V25632A.
If DSF is inactive (Low level), MSM54V25632A operates just like SDRAM.
DQM0 -
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
DQM3
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
DQi
Data inputs/outputs are multiplexed on the same pin.
*Notes:
1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0,
DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by A9.
A9
Active, read or write
0
Bank A
1
Bank B
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is
issued.
A8
A9
Operation
0
0
After the end of burst, bank A holds the active status.
1
0
After the end of burst, bank A is precharged automatically.
0
1
After the end of burst, bank B holds the active status.
1
1
After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8
A9
Operation
0
0
Bank A is precharged.
0
1
Bank B is precharged.
1
X
Both banks A and B are precharged.
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¡ Semiconductor
MSM54V25632A
COMMAND OPERATION
Mode Register Set Command (CS, RAS, CAS, WE, DSF = "Low")
The MSM54V25632A has the mode register that defines the operation mode "CAS Latency,
Burst Length, Burst Sequence". The mode register is composed of ten bits of memories
corresponding to address inputs A0 - A8 and BA. The Mode Register Set command should be
executed just after the MSM54V25632A is powered on. Before entering this command, all banks
must be precharged. Next command can be issued after tRSC.
Special Mode Register Set Command (CS, RAS, CAS, WE = "Low", DSF = "High")
The MSM54V25632A has the 32-bit color register for block write operation and the 32-bit mask
register for write per bit operation. The Special Mode Register Set command performs loading
mask register or color register. When A5 is "high", The mask data presented on the DQ0 - DQ31
is latched into the mask register. When A6 is "high", The color data presented on the DQ0 - DQ31
is latched into the color register. The Special Mode Register Set command must be executed
before Masked Block Write and Write Per Bit operations. Next command can be issued after
tRSC.
Auto Refresh Command (CS, RAS, CAS, DSF = "Low", WE, CKE = "High")
The Auto Refresh command performs refresh automatically by the address counter. The refresh
operation must be performed 1024 times within 16 ms and the next command can be issued after
tRC from last Auto Refresh command. Before entering this command, all banks must be
precharged.
Self Refresh Entry/Exit Command (CS, RAS, CAS, DSF, CKE = "Low", WE = "High")
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE
level left "low". This operation terminates by making CKE level "high". The self refresh
operation is performed automatically by the internal address counter on the MSM54V25632A
chip. In self refresh mode, no external refresh control is required. Before entering self refresh
mode, all banks must be precharged. Next command can be issued after tRC.
Single Bank Precharge Command (CS, RAS, WE, DSF, A8 = "Low", CAS = "High")
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is
selected by BA.
All Banks Precharge Command (CS, RAS, WE, DSF = "Low", CAS, A8 = "High")
The All Bank Precharge command triggers precharge of both bank A and bank B.
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¡ Semiconductor
MSM54V25632A
Bank Active and Masked Write Disable Command (CS, RAS, DSF = "Low", CAS, WE =
"High")
The Bank Active command activates the bank selected by BA. The Bank Active command
corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"
are strobed. After this command, the write command and block write command for that bank
works as the no write per bit operation.
Bank Active and Masked Write Enable Command (CS, RAS = "Low", CAS, WE, DSF =
"High")
The Bank Active command activates the bank selected by BA. The Bank Active command
corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"
are strobed. After this command, the write command and block write command for that bank
works as the write per bit operation.
Write Command (CS, CAS, WE, DSF, A8 = "Low", RAS = "High")
The Write command is required to begin burst write operation. Then burst access initial bit
column address is strobed.
Write with Auto Precharge Command (CS, CAS, WE, DSF = "Low", RAS, A8 = "High")
The Write with Auto Precharge command is required to begin burst write operation with
automatic precharge after the burst write. Any command that interrupts this operation cannot
be issued.
Masked Block Write Command (CS, CAS, WE, A8 = "Low", RAS, DSF = "High")
The Masked Block Write command is required to begin block write operation with column
mask. The masked block write operation performs writing in the 8 memory cells selected by
column addresses "A3 - A7". In this operation, data in color register is written to memory cells
with the column mask functions. At the same time, this command can perform write per bit
operation. The block write operation is not bursted.
6/66
¡ Semiconductor
MSM54V25632A
Block Write Function
Color Register
11001110
I/O Mask
11111010
Column Mask
10010011
Column 7
1
1
0
0
1
*
1
*
Column 6
1
1
0
0
1
*
1
*
Column 5
*
*
*
*
*
*
*
*
Column 4
*
*
*
*
*
*
*
*
Column 3
1
1
0
0
1
*
1
*
Column 2
*
*
*
*
*
*
*
*
Column 1
*
*
*
*
*
*
*
*
Column 0
1
1
0
0
1
*
1
*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8 Column ¥ 8 DQ
Note : Location "*" can not be loaded.
Remark: 1. This diagram shows only for DQ0 - 7. The other DQ is similar as this.
Column Mask
DQ0 - 7 : Column Mask for DQ0 - 7
DQ8 - 15 : Column Mask for DQ8 - 15
DQ16 - 23 : Column Mask for DQ16 - 23
DQ24 - 31 : Column Mask for DQ24 - 31
Write per Bit
Mask data = Mask Register + DQMi
DQMi is prior to data of Mask Register.
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¡ Semiconductor
MSM54V25632A
Masked Block Write with Auto Precharge Command (CS, CAS, WE = "Low", RAS, DSF,
A8 = "High")
The Masked Block Write with Auto Precharge command performs precharging at the bank
selected by BA automatically after Masked Block Write.
Read Command (CS, CAS, DSF, A8 = "Low", RAS, WE = "High")
The Read command is required to begin burst read operation. Then burst access initial bit
column address is strobed.
Read with Auto Prechaege Command (CS, CAS, DSF = "Low", RAS, WE, A8 = "High")
The Read with Auto Precharge command is required to begin burst read operation with auto
precharge after the burst read. Any command that interrupts this operation cannot be issued.
No Operation Command (CS, DSF = "Low", RAS, CAS, WE = "High")
The No Operation command does not trigger any operation.
Device Deselect Command (CS = "High")
The Device Deselect command disables the RAS, CAS, WE, DSF and Address input. This
command does not trigger any operation.
Data Write/Output Enable Command (DQMi = "Low")
The Data Write/Output Enable command enables DQ0 - DQ31 in read or write.
The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24
- DQ31 respectively.
Data Mask/Output Disable Command (DQMi = "High")
The Data Mask/Output Disable command disables DQ0 - DQ31. In read cycle output buffers
are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each
DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31
respectively.
Burst Stop Command (CS, WE, DSF = "Low", RAS, CAS = "High")
The Burst Stop command stops burst access when the access is in full page. After the Burst Stop
command is entered, the output buffer goes into high impedance state.
8/66
¡ Semiconductor
MSM54V25632A
TRUTH TABLE
Command Truth Table
Function
CS
RAS
CAS
WE
DSF
Address
A9
A8
A7 - A0
Device Deselect
H
¥
¥
¥
¥
¥
¥
¥
No Operation
L
H
H
H
L
¥
¥
¥
Burst Stop in Full Page
L
H
H
L
L
¥
¥
¥
Read
L
H
L
H
L
BA
L
CA
Read with Auto Precharge
L
H
L
H
L
BA
H
CA
Write
L
H
L
L
L
BA
L
CA
Write with Auto Precharge
L
H
L
L
L
BA
H
CA
Masked Block Write
L
H
L
L
H
BA
L
CA
Masked Block Write with Auto
L
H
L
L
H
BA
H
CA
L
L
H
H
L
BA
RA
Precharge
Bank Activate
Bank Activate with WPB Enable
L
L
H
H
H
BA
RA
Precharge Select Bank
L
L
H
L
L
BA
L
¥
Precharge All Banks
L
L
H
L
L
¥
H
¥
Mode Register Set
L
L
L
L
L
OP. CODE
Special Register Set
L
L
L
L
H
OP. CODE
DQM Truth Table
Function
DQMi
Data Write/Output Enable
L
Data Mask/Output Disable
H
9/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (1/5)
Note 1
Current State CS RAS CAS WE DSF Address
Idle
Row Active
(ACT)
Action
Note
H
¥
¥
¥
¥
¥
NOP or Power Down
L
H
H
H
¥
¥
NOP or Power Down
L
H
H
L
H
¥
ILLEGAL
2
L
H
H
L
L
¥
ILLEGAL
2
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
2
L
H
L
L
H
BA, CA, A8
ILLEGAL
2
L
H
L
L
L
BA, CA, A8
ILLEGAL
2
L
L
H
H
H
BA, RA
Row Active with WPB
L
L
H
H
L
BA, RA
Row Active
L
L
H
L
H
¥
L
L
H
L
L
BA, A8
L
L
L
H
H
¥
ILLEGAL
NOP
3
ILLEGAL
L
L
L
H
L
¥
L
L
L
L
H
Op-Code
Special Register Write
Mode Register Write
Auto Refresh/Self refresh
4
L
L
L
L
L
Op-Code
H
¥
¥
¥
¥
¥
NOP
L
H
H
H
¥
¥
NOP
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
Read
L
H
L
L
H
BA, CA, A8
Block Write
L
H
L
L
L
BA, CA, A8
Write
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
Precharge
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
Special Register Write
L
L
L
L
L
Op-Code
ILLEGAL
2
10/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (2/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
H
¥
¥
¥
¥
¥
NOP (Continue Row Active after Burst ends)
L
H
H
H
¥
¥
NOP (Continue Row Active after Burst ends)
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
1, 2, 4, 8 Burst Length; ILLEGAL
L
H
L
H
H
¥
L
H
L
H
L
BA, CA, A8
L
H
L
L
H
BA, CA, A8
Term Burst, start Block Write
L
H
L
L
L
BA, CA, A8
Term Burst, start Write
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
L
L
H
L
L
BA, A8
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
ILLEGAL
L
L
L
L
L
Op-Code
ILLEGAL
Write/Block Write H
(WT/BW)
L
¥
¥
¥
¥
¥
NOP (Continue Row Active after Burst ends)
H
H
H
¥
¥
NOP (Continue Row Active after Burst ends)
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
1, 2, 4, 8 Burst Length; ILLEGAL
Read
(RD)
Full Page Burst; Burst Stop Æ Bank Active
ILLEGAL
Term Burst, new Read
ILLEGAL
Term Burst, execute Row Precharge
Full Page Burst; Burst Stop Æ Row Active
L
H
L
H
H
¥
L
H
L
H
L
BA, CA, A8
Term Burst, start Read
L
H
L
L
H
BA, CA, A8
Term Burst, new Block Write
L
H
L
L
L
BA, CA, A8
Term Burst, new Write
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
L
L
L
H
H
¥
ILLEGAL
ILLEGAL
Term Burst, execute Row Precharge
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
ILLEGAL
L
L
L
L
L
Op-Code
ILLEGAL
11/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (3/5)
Note 1
Current State CS RAS CAS WE DSF Address
Read with Auto
Precharge
(RAP)
Write/Block
Write with Auto
Precharge
(WAP/BWAP)
Action
Note
H
¥
¥
¥
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
H
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
L
H
L
L
H
BA, CA, A8
ILLEGAL
L
H
L
L
L
BA, CA, A8
ILLEGAL
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
ILLEGAL
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op- Code
ILLEGAL
ILLEGAL
2
L
L
L
L
L
Op- Code
H
¥
¥
¥
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
H
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
L
H
L
L
H
BA, CA, A8
ILLEGAL
L
H
L
L
L
BA, CA, A8
ILLEGAL
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
ILLEGAL
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op- Code
ILLEGAL
L
L
L
L
L
Op- Code
ILLEGAL
2
12/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (4/5)
Note 1
Current State CS RAS CAS WE DSF Address
Precharging
(PRE)
Refreshing
(REF)
Action
Note
H
¥
¥
¥
¥
¥
NOP Æ Idle after tRP
L
H
H
H
¥
¥
NOP Æ Idle after tRP
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
2
L
H
L
L
H
BA, CA, A8
ILLEGAL
2
L
H
L
L
L
BA, CA, A8
ILLEGAL
2
L
L
H
H
H
BA, RA
ILLEGAL
2
L
L
H
H
L
BA, RA
ILLEGAL
2
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
L
L
L
H
H
¥
ILLEGAL
ILLEGAL
L
L
L
H
L
¥
L
L
L
L
H
Op-Code
NOP Æ Idle after tRP
2
3
Special Register Write
ILLEGAL
L
L
L
L
L
Op-Code
H
¥
¥
¥
¥
¥
NOP Æ Idle after tRC
L
H
H
H
¥
¥
NOP Æ Idle after tRC
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
L
H
L
L
H
BA, CA, A8
ILLEGAL
L
H
L
L
L
BA, CA, A8
ILLEGAL
L
L
H
H
H
BA, RA
ILLEGAL
L
L
H
H
L
BA, RA
ILLEGAL
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
ILLEGAL
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
ILLEGAL
L
L
L
L
L
Op-Code
ILLEGAL
13/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (5/5)
Note 1
Current State CS RAS CAS WE DSF Address
Mode Register
Access
(MRA)
Special Mode
Register
Access
(SMRA)
H
¥
¥
¥
¥
¥
NOP
L
H
H
H
¥
¥
NOP
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
L
H
L
L
H
BA, CA, A8
ILLEGAL
L
H
L
L
L
BA, CA, A8
ILLEGAL
L
L
H
H
H
BA, RA
ILLEGAL
L
L
H
H
L
BA, RA
ILLEGAL
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
ILLEGAL
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
ILLEGAL
ILLEGAL
L
L
L
L
L
Op-Code
H
¥
¥
¥
¥
¥
NOP
L
H
H
H
¥
¥
NOP
L
H
H
L
H
¥
ILLEGAL
L
H
H
L
L
¥
ILLEGAL
L
H
L
H
H
¥
ILLEGAL
L
H
L
H
L
BA, CA, A8
ILLEGAL
L
H
L
L
H
BA, CA, A8
ILLEGAL
L
H
L
L
L
BA, CA, A8
ILLEGAL
L
L
H
H
H
BA, RA
ILLEGAL
L
L
H
H
L
BA, RA
ILLEGAL
L
L
H
L
H
¥
ILLEGAL
L
L
H
L
L
BA, A8
ILLEGAL
L
L
L
H
H
¥
ILLEGAL
L
L
L
H
L
¥
ILLEGAL
L
L
L
L
H
Op-Code
ILLEGAL
L
L
L
L
L
Op-Code
ILLEGAL
ABBREVIATIONS
RA = Row Address
CA = Column Address
Notes:
Action
BA = Bank Address
AP = Auto Precharge
Note
NOP = No OPeration command
¥ = High or Low level (Don't care)
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8.
4. Illegal if any bank is not idle.
14/66
¡ Semiconductor
MSM54V25632A
Function Truth Table for CKE
Current State (n) CKEn-1 CKEn CS RAS CAS WE DSF Address
Self Refresh
(SREF)
Power Down
(PD)
Action
Note
H
¥
¥
¥
¥
¥
¥
¥
INVALID
5
L
H
H
¥
¥
¥
¥
¥
Exit Self Refresh Æ ABI
5
L
H
L
H
H
H
¥
¥
Exit Self Refresh Æ ABI
5
L
H
L
H
H
L
¥
¥
ILLEGAL
5
L
H
L
H
L
¥
¥
¥
ILLEGAL
5
L
H
L
L
¥
¥
¥
¥
ILLEGAL
5
L
L
¥
¥
¥
¥
¥
¥
NOP (Maintain Self Refresh)
5
H
¥
¥
¥
¥
¥
¥
¥
INVALID
5
L
H
H
¥
¥
¥
¥
¥
Exit Power Down Æ ABI
5
L
H
L
H
H
H
¥
¥
Exit Power Down Æ ABI
5
L
H
L
H
H
L
¥
¥
ILLEGAL
5
L
H
L
H
L
¥
¥
¥
ILLEGAL
5
L
H
L
L
¥
¥
¥
¥
ILLEGAL
5
L
L
¥
¥
¥
¥
¥
¥
NOP (Continue power down mode)
5
All Banks Idle
H
H
¥
¥
¥
¥
¥
¥
Refer to Table
6
(ABI)
H
L
H
¥
¥
¥
¥
¥
Enter Power Down
6
H
L
L
H
H
H
¥
¥
Enter Power Down
6
H
L
L
H
H
L
¥
¥
ILLEGAL
6
H
L
L
H
L
¥
¥
¥
ILLEGAL
6
H
L
L
L
H
L
¥
¥
ILLEGAL
6
H
L
L
L
L
H
L
¥
Enter Self Refresh
6
H
L
L
L
L
L
¥
¥
ILLEGAL
6
6
L
L
¥
¥
¥
¥
¥
¥
NOP
Any State Other
H
H
¥
¥
¥
¥
¥
¥
Refer to Operations in Table
than Listed Above
H
L
¥
¥
¥
¥
¥
¥
Begin Clock Suspend Next Cycle
L
H
¥
¥
¥
¥
¥
¥
Enable Clock of Next Cycle
L
L
¥
¥
¥
¥
¥
¥
Continue Clock Suspension
Notes:
5. If the minimum set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE
operates asynchronously so that a command can be input in the same internal clock cycle.
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
15/66
¡ Semiconductor
MSM54V25632A
Mode Set Address Keys
CAS Latency (CL)
Operation Code
Burst Type (BT)
Burst Length (BL)
A8
A7
TM
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Setting
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
Reserved
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
1
Write Burst Length
A9
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
Special Mode Set Address Keys
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
LC
LM
0
0
0
0
0
Load Color (LC)
Note :
Load Mask (LM)
A6
Function
A5
Function
0
Disable
0
Disable
1
Enable
1
Enable
If LC and LM are both high (1), data of Mask and Color register will be unknown.
POWER ON SEQUENCE
1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power
supply and start the system clock.
2. After the VCC voltage has reached the specified level, pause for 200 ms or more with
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply an Auto-refresh eight or more times.
5. Enter the mode register setting command.
16/66
¡ Semiconductor
MSM54V25632A
Burst Length and Sequence
BL = 2
Starting Address
Sequential Type
Interleave Type
0
0, 1
Not supported
1
1, 0
Not supported
Sequential Type
Interleave Type
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Sequential Type
Interleave Type
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4 ,5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
(column address A0, binary)
BL = 4
Starting Address
(column address A1 - A0, binary)
BL = 8
Starting Address
(column address A2 - A0, binary)
BL = Full : Sequential only
17/66
¡ Semiconductor
MSM54V25632A
PRECHARGE
Read Interrupted by Precharge
CL = 1
CL = 2 or 3
: At the same clock as the last read data.
: One clock earlier than the last read data.
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
RD
DQ
CL = 2
Q1
DQ
Q2
Q3
RD
DQ
CL = 3
PRE
Hi-Z
Q4
PRE
Q1
Q2
Q3
RD
Hi-Z
Q4
PRE
Q1
Q2
Q3
Q4
Hi-Z
(tRAS is satisfied)
18/66
¡ Semiconductor
MSM54V25632A
AUTO PRECHARGE
Read with Auto Precharge
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
RAP
DQ
CL = 2
Q1
DQ
Q2
RAP
DQ
CL = 3
Auto precharge starts
Q3
Hi-Z
Q4
Auto precharge starts
Q1
Q2
RAP
Q3
Hi-Z
Q4
Auto precharge starts
Q1
Q2
Q3
Q4
Hi-Z
(tRAS is satisfied)
19/66
¡ Semiconductor
MSM54V25632A
Write with Auto Precharge
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
WAP
DQ
D1
CL = 2
Auto precharge starts
D2
D3
WAP
DQ
D1
CL = 3
Hi-Z
D4
Auto precharge starts
D2
D3
Hi-Z
D4
WAP
DQ
D1
Auto precharge starts
D2
D3
Hi-Z
D4
(tRAS is satisfied)
Block Write with Auto Precharge
0
1
2
3
4
5
CLK
tBWC
CL = 1
DQ
CL = 2
DQ
CL = 3
DQ
BWAP Auto precharge starts
DB
Hi-Z
BWAP Auto precharge starts
DB
BWAP
DB
Hi-Z
Auto precharge starts
Hi-Z
(tRAS is satisfied)
20/66
¡ Semiconductor
MSM54V25632A
READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
RD-B
RD-A
DQ
QA1
QB1
QB2
QB3
Hi-Z
QB4
1 cycle
Write to Write Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
DQ
WT-A
WT-B
DA1
DB1
DB2
DB3
DB4
Hi-Z
1 cycle
21/66
¡ Semiconductor
MSM54V25632A
Write to Read Command Interval
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
DQ
WT-A
DA1
RD-B
Hi-Z
QB1
QB2
QB3
QB4
QB1
QB2
QB3
QB4
QB1
QB2
QB3
1 cycle
CL = 2
DQ
CL = 3
DQ
WT-A
DA1
WT-A
DA1
RD-B
Hi-Z
RD-B
Hi-Z
QB4
22/66
¡ Semiconductor
MSM54V25632A
Block Write to Write/Block Write Command Interval
0
1
2
3
4
5
6
7
8
7
8
CLK
tBWC
DQ
BW-A
BW-B
DA
DB
CL = 2
Hi-Z
tBWC
DQ
BW-A
WT-B
DA
DB1
BL = 4, CL = 2
DB2
DB3
DB4
Block Write to Read Command Interval
0
1
2
3
4
5
6
CLK
tBWC
CL = 1
DQ
BW-A
DA
RD-B
Hi-Z
QB1
QB2
QB3
QB4
QB1
QB2
QB3
QB4
QB1
QB2
QB3
tBWC
CL = 2
DQ
BW-A
DA
RD-B
Hi-Z
tBWC
CL = 3
DQ
BW-A
DA
RD-B
Hi-Z
QB4
23/66
¡ Semiconductor
MSM54V25632A
Read to Write/Block Write Command Interval
CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
RD-A
WT-B
DQM
DQ
Hi-Z
DB1
DB2
DB3
DB4
1 cycle
BL = 8, CL = 1, 2
0
1
2
3
4
5
6
7
8
9
CLK
CL = 1
RD-A
WT-B
DQM
DQ
CL = 2
QA1
QA2
QA3
QA4
RD-A
DB1
Hi-Z is
necessary
DB2
DB3
DB2
DB3
WT-B
DQM
DQ
QA1
QA2
QA3
DB1
Hi-Z is
necessary
24/66
¡ Semiconductor
MSM54V25632A
ex.) CL = 3, BL = 4
0
1
2
3
4
5
6
7
8
CLK
RD-A
WT-B
DQM
DQ
QA1
DB1
Hi-Z is
necessary
DB2
DB3
|
ex.) CL = 1, BL = 4
0
1
2
3
CLK
WT-A
DA1
5
6
7
8
9
RD-B
DQM
DQ
4
DA2
DA3
Hi-Z
QB2
QB3
QB4
Note
Note : DQM can mask both data-in and data-out in this special case.
25/66
¡ Semiconductor
MSM54V25632A
BURST TERMINATION
Burst Stop Command in Full Page
BL = Full Page, CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
RD
BST
CL = 1
DQ
Q1
CL = 2
DQ
Hi-Z
Q2
Q3
Q1
Q2
Q3
Q1
Q2
CL = 3
DQ
Hi-Z
Hi-Z
Q3
BL = Full Page, CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
WT
CL = 1, 2, 3
DQ
D1
BST
D2
D3
D4
Hi-Z
26/66
¡ Semiconductor
MSM54V25632A
Precharge Termination in READ Cycle
BL = X, CL = 1
0
1
2
3
4
5
6
7
8
CLK
RD
PRE
DQ
Q1
Q2
Q3
ACT
Hi-Z
Q4
tRP
BL = X, CL = 2
0
1
2
3
4
5
6
7
8
CLK
RD
PRE
DQ
Q1
Q2
ACT
Q3
Hi-Z
Q4
tRP
BL = X, CL = 3
0
1
2
3
4
5
6
7
8
CLK
RD
DQ
PRE
Q1
Q2
ACT
Hi-Z
Q3
tRP
27/66
¡ Semiconductor
MSM54V25632A
Precharge Termination in WRITE Cycle
BL = X, CL = 1, 2
0
1
2
3
4
5
6
7
8
CLK
WT
DQ
PRE
D1
D2
D3
D4
ACT
Hi-Z
D5
tRP
Note : D5 data will not be written
BL = X, CL = 3
0
1
2
3
4
5
6
7
8
CLK
WT
DQ
D1
PRE
D2
D3
D4
D5
ACT
Hi-Z
tRP
Note : D5 data will not be written
28/66
¡ Semiconductor
MSM54V25632A
ELECTRICAL CHARACTERISTICS
Note :
All voltages are referenced to VSS.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
VCC, VCCQ
—
–1.0 to 4.6
V
Voltage on Input Pin Relative to GND
VT
—
–1.0 to VCC + 0.5 £ 4.6
V
Short Circuit Output Current
IOS
—
50
mA
Voltage on Power Supply Pin
Relative to GND
Power Dissipation
PD
Ta = 25°C
1
W
Operating Temperature
Topr
—
0 to 70
°C
Storage Temperature
Tstg
—
–55 to 150
°C
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions
outside the limits described in the operational section of this specification. Exposure to
Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VCC + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Parameter
Capacitance
(VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (A0 - A9)
Input Capacitance
(CLK, CKE, CS, RAS, CAS, WE, DSF, DQM)
Input/Output Capacitance
(DQ0 - DQ31)
Symbol
Min.
Max.
Unit
CI1
—
6
pF
CI2
—
6
pF
CI/O
—
7
pF
DC Characteristics 1
Parameter
Symbol
Test Condition
Min.
Max.
Unit
Output High Voltage
VOH
IOH = –2 mA
2.4
—
V
Output Low Voltage
VOL
IOL = 2 mA
—
0.4
V
–10
10
mA
–10
10
mA
Input Leakage Current
ILI
Output Leakage Current
ILO
0 V £ VI £ 3.6 V;
All other pins not under test = 0 V
DOUT is disabled, 0 V £ VO £ 3.6 V
29/66
¡ Semiconductor
MSM54V25632A
DC Characteristics 2
Parameter
Operating Current
Test Condition
Symbol
ICC1
Burst length = 1, tRAS ≥ tRAS (MIN.),
tRP ≥ tRP (MIN.), IO = 0 mA
Precharge Standby Current ICC2P CKE £ VIL (MAX.), tCK = 15 ns
in Power Down Mode
ICC2PS CKE £ VIL (MAX.), tCK = •
-10
-12
Max.
Max.
175
155
4
4
3
3
60
60
Unit Note
mA
1
mA
CKE ≥ VIH (MIN.), tCK = 15 ns,
Precharge Standby Current
ICC2N CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
in Non Power Down Mode
ICC2NS
CKE ≥ VIH (MIN.), tCK = •,
Input signals are stable.
mA
30
30
Active Standby Current
ICC3P CKE £ VIL (MAX.), tCK = 15 ns
4
4
in Power Down Mode
ICC3PS CKE £ VIL (MAX.), tCK = •
3
3
70
70
mA
CKE ≥ VIH (MIN.), tCK = 15 ns,
Active Standby Current
ICC3N CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
in Non Power Down Mode
ICC3NS
Operating Current
(Burst Mode)
ICC4
CKE ≥ VIH (MIN.), tCK = •,
IO = 0 mA
Refresh Current
ICC5 tRC ≥ tRC (MIN.)
Self Refresh Current
ICC6 CKE £ 0.2 V
Operating Current
(Block Write Mode)
Notes 1.
2.
3.
ICC7
35
35
CAS Latency = 1
130
120
CAS Latency = 2
180
170
CAS Latency = 3
240
230
165
3
240
Input signals are stable.
tCK ≥ tCK (MIN.),
tCK ≥ tCK (MIN.), IO = 0 mA,
CAS cycle = 20 ns
mA
mA
2
145
mA
3
3
mA
240
mA
ICC1 depends on output loading and cycle rates. Specified values are obtained with the
output open. In addition to this, ICC1 is measured on condition that addresses are
changed only one time during tCK (MIN.).
ICC4 depends on output loading and cycle rates. Specified values are obtained with the
output open. In addition to this, ICC4 is measured on condition that addresses are
changed only one time during tCK (MIN.).
ICC5 is measured on condition that addresses are changed only one time during tCK
(MIN.).
30/66
¡ Semiconductor
MSM54V25632A
AC Characteristics
Test conditions
• AC measurements assume tT = 1 ns.
• Reference level for measuring timing of input signals is 1.4 V. Transition times are measured
between VIH and VIL.
• If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL
(MAX).
• An access time is measured at 1.4 V.
tCK
tCH
2.8 V
CLK 1.4 V
VSS
tCL
tSetup tHold
2.8 V
Input 1.4 V
VSS
tAC
tOH
Output
1.4 V
1.4 V
31/66
¡ Semiconductor
MSM54V25632A
Synchronous Characteristics
MSM54V25632A
Parameter
MSM54V25632A
-10
Symbol
-12
Unit Note
Min.
Max.
Min.
Max.
CAS Latency = 3 tCK3
10
(100 MHz)
12
(83 MHz)
ns
CAS Latency = 2 tCK2
15
(66 MHz)
18
(55 MHz)
ns
CAS Latency = 1 tCK1
30
(33 MHz)
36
(28 MHz)
ns
CAS Latency = 3 tAC3
—
9
—
10
ns
1
Access Time from CLK CAS Latency = 2 tAC2
—
13
—
15
ns
1
CAS Latency = 1 tAC1
—
27
—
32
ns
1
tCH
3.5
—
4
—
ns
CLK Low Level Width
tCL
3.5
—
4
—
ns
Data-out Hold Time
tOH
3
—
3
—
ns
Clock Cycle Time
CLK High Level Width
Data-out Low-impedance Time
Data-out
tLZ
0
—
0
—
ns
CAS Latency = 3 tHZ3
3
8
3
8
ns
CAS Latency = 2 tHZ2
3
12
3
12
ns
CAS Latency = 1 tHZ1
3
26
3
26
ns
Data-in Setup Time
tDS
3
—
3.5
—
ns
Data-in Hold Time
tDH
1
—
1.5
—
ns
Address Setup Time
tAS
3
—
3.5
—
ns
Address Hold Time
tAH
1
—
1.5
—
ns
CKE Setup Time
tCKS
3
—
3.5
—
ns
CKE Hold Time
tCKH
1
—
1.5
—
ns
tCMS
3
—
3.5
—
ns
tCMH
1
—
1.5
—
ns
High-impedance Time
Command (CS, RAS, CAS, WE, DSF,
DQM) Setup Time
Command (CS, RAS, CAS, WE, DSF,
DQM) Hold Time
Note
1.
Output load.
1.4 V
Z = 50 W
50 W
Output
30 pF
32/66
¡ Semiconductor
MSM54V25632A
Asynchronous Characteristics
MSM54V25632A
Parameter
MSM54V25632A
-10
Symbol
Min.
-12
Max.
Min.
Unit Note
Max.
REF to REF/ACT Command Period
tRC
90
—
108
—
ns
ACT to PRE Command Period
tRAS
60
120,000
72
120,000
ns
PRE to ACT Command Period
tRP
30
—
36
—
ns
Delay Time ACT to READ/WRITE Command
tRCD
30
—
36
—
ns
ACT (0) to ACT (1) Command Period
Data-in to PRE
Command Period
tRRD
20
—
24
—
ns
CAS Latency = 3 tDPL3
20
—
24
—
ns
CAS Latency = 2 tDPL2
20
—
24
—
ns
CAS Latency = 1 tDPL1
20
—
24
—
ns
Data-in to ACT (REF) CAS Latency = 3 tDAL3
5
—
5
—
CLK
Command Period
CAS Latency = 2 tDAL2
3
—
3
—
CLK
(Auto Precharge)
CAS Latency = 1 tDAL1
2
—
2
—
CLK
Block Write Cycle Time
tBWC
20
—
24
—
ns
Block Write Data-in
CAS Latency = 3 tBPL3
30
—
36
—
ns
to PRE Command
CAS Latency = 2 tBPL2
30
—
36
—
ns
Period
CAS Latency = 1 tBPL1
30
—
36
—
ns
Block Write Data-in
Active (REF)
Command Period
(Auto Precharge)
CAS Latency = 3 tBAL3
6
—
6
—
CLK
CAS Latency = 2 tBAL2
4
—
4
—
CLK
CAS Latency = 1 tBAL1
Mode Register Set Cycle Time
CKE Setup Time
(Precharge Power Down Exit)
Transition Time
Refresh Time
2
—
2
—
CLK
tRSC
20
—
20
—
ns
tPDE
8
—
10
—
ns
tT
1
30
1
30
ns
tREF
—
16
—
16
ms
33/66
¡ Semiconductor
MSM54V25632A
|y,|y,z}{~,yz|}{~
|y,z}€{~|€z{}~,y
TIMING WAVEFORM
AC Parameters for Read Timing (BL = 2, CL = 2)
0
tCK
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
tCH tCL
tCKS
tCMS tCMH
CKE
Auto Precharge
Start for Bank B
tCKH
CS
RAS
CAS
WE
z
}€z
DSF
A9
(BA)
A8
ADD
tAS
tAH
DQM
0-3
DQ
tCMS
tCMH
tAC
Hi-Z
tRCD
tRRD
tLZ
tAC
tHZ
tOH
tRAS
tOH
tRP
tRC
ACT-A
RD-A
ACT-B
RAP-B
PRE-A
ACT-A
34/66
¡ Semiconductor
MSM54V25632A
y,}€|{~}€|y,z~{z}€
|y,~{|y,z}€~{z€
AC Parameters for Write Timing (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
Auto Precharge
Start for Bank A
tCKS
tCMS tCMH
Auto Precharge
Start for Bank B
tCKH
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
tAS
tAH
DQM
0-3
DQ
tDS
Hi-Z
tCMH
tCMS
tDH
tRCD
tRRD
tDAL
tDPL
tRP
tRC
ACT-A
WAP-A ACT-B
WAP-B
ACT-A
WAP-A
PRE-A
ACT-A
35/66
¡ Semiconductor
MSM54V25632A
Relationship between Frequency and Latency
Rate
MSM54V25632A-10
MSM54V25632A-12
Clock Cycle Time [ns]
10
15
30
12
18
36
Frequency [MHz]
100
66
33
83
55
28
CAS Latency
3
2
1
3
2
1
[tRCD]
3
2
1
3
2
1
6
4
2
6
4
2
[tRC]
9
6
3
9
6
3
[tRAS]
6
4
2
6
4
2
[tRRD]
2
2
1
2
2
1
[tRP]
3
2
1
3
2
1
[tDPL]
2
2
1
2
2
1
[tDAL]
5
3
2
5
3
2
RAS Latency
(CAS Latency + [tRCD])
36/66
¡ Semiconductor
MSM54V25632A
Power on Sequence and Auto Refresh (Initialization)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
High level is necessary
8 refresh cycles are necessary
|,yz}{~z{}~
|,yz}€{~}~€{z
CKE
ADDRESS KEY
ADD
DQM
0-3
DQ
High level is necessary
Hi-Z
REF
REF
MRA
PRE
(All Banks)
tRC
tRC
37/66
¡ Semiconductor
MSM54V25632A
Mode Register Set (BL = 4, CL = 2)
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
|y,€}z~{€}|yz,~{
|,yz}€{~,yz|}€~{
1
CLK
CKE
tRSC (20 ns)
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADDRESS KEY
ADD
DQM
0-3
DQ
Hi-Z
PRE
MRA
(All Banks)
ACT
tRP
38/66
¡ Semiconductor
MSM54V25632A
Auto Refresh (CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
|y,€}z~{}|zy,€
|y,z}€{~€}|zy,
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
L
DQ
Q1
PRE
REF
tRP
REF
tRC
ACT
RD
tRC
39/66
|{y,z}z}{~
y,|{,yz}~€}€z~{
¡ Semiconductor
MSM54V25632A
Self Refresh (Entry and Exit)
0
CLK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
DQ
1
2
3
4
7
8
9
10 11 12
17 18 19 20 21
L
PRE
SREF
entry
tRP
SREF
Exit
SREF
entry
or
(ACT)
Next
clock
enable
tRC
SREF
Exit
ACT
Next clock
enable
tRC
40/66
¡ Semiconductor
MSM54V25632A
Auto Precharge after Read Burst (BL = 4, CL = 3)
0
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
DQ
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
|,yz}{~|y,z}
|,yz}€}~€z{|y,
CLK
1
H
RAa
RAa
RBb
RBa
CAa RBa
CBa
CAb
RBb
CBb
L
Hi-Z
ACT-A
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBa3 QBa4 QAb1 QAb2 QAb3 QAb4
ACT-B
RD-A
RAP-A
QBb1 QBb2
RAP-B
AP-A
RAP-B
AP-B
ACT-B
41/66
¡ Semiconductor
MSM54V25632A
|y,~{z}€y,|~{
|y,~{}€z|,y~{
Auto Precharge after Write Burst (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
H
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
L
DQ
Hi-Z
ACT-A
RBb
RBa
CAa RBa
CBa
CAb
RBb
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBa3 DBa4 DAb1 DAb2 DAb3 DAb4
ACT-B
WT-A
WAP-A
CBb
DBb1 DBb2 DBb3 DBb4
ACT-B
WAP-B
WAP-B
AP-B
AP-A
42/66
¡ Semiconductor
MSM54V25632A
Full Page READ Cycle (CL = 3)
y,{y,z{
|y,~{|y,z}€~{
|y,~{|}y,z€~{
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
L
DQ
RBa
CAa
RBa
Hi-Z
ACT-A
RBb
CBa
RBb
QAa QAa+1 QAa–3 QAa–2 QAa–1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
RD-A
ACT-B
RD-B
Burst cannot
end in Full
Page mode Burst stop
Command
PRE-B
ACT-B
tRP
43/66
¡ Semiconductor
MSM54V25632A
Full Page WRITE Cycle (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
H
|y,z}€{~{z€}~
|,yz}{~€{}~€z
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
L
DQ
Hi-Z
ACT-A
RBa
CAa
RBb
RBa
CBa
RBb
DAa DAa+1 DAa+2 DAa+3 DAa–1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4
WT-A
ACT-B
Burst cannot
end in Full
Page mode
WT-B
PRE-B
ACT-B
Burst stop
Command
tRP
44/66
¡ Semiconductor
MSM54V25632A
PRE (Precharge) Termination of Burst (BL = 2, 4, 8, Full, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
z{}~,y|{~
€}z{~,y|{~
€
}
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
L
DQ
RAb
CAa
RAb
RAc
CAb
DAa1 DAa2
ACT-A
QAb1 QAb2 QAb3
WT-A
Hi-Z
RD-A
PRE-A
PRE Command
Termination
tRCD
RAc
tDPL
ACT-A
tRP
PRE-A
PRE Command
Termination
tRAS
ACT-A
tRP
45/66
¡ Semiconductor
MSM54V25632A
Clock Suspension during Burst Read (using CKE Function) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CS
RAS
CAS
WE
DSF
A9
(BA)
|y,}z~{}|zy,
|y€,}z~{€}|zy,
CKE
A8
RAa
ADD
RAa
DQM
0-3
L
CAa
QAa1
DQ
ACT-A
RD-A
QAa2
QAa3
1-CLOCK
2-CLOCK
SUSPENDED SUSPENDED
QAa4
3-CLOCK
SUSPENDED
Hi-Z
(turn off)
at end of burst
46/66
¡ Semiconductor
MSM54V25632A
Clock Suspension during Burst Write (using CKE Function) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
€}|zy,~{~{€}z
yz,€}|{~{,y|~€}z
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
CAa
L
DQ
DAa1
ACT-A
DAa2
DAa3
DAa4
1-CLOCK
2-CLOCK
SUSPENDED SUSPENDED
3-CLOCK
SUSPENDED
WT-A
47/66
¡ Semiconductor
MSM54V25632A
y,||y,}z~{€~{
|,y|z{}~,y€{~
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
tCKS
tPDE
CKE
VALID
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
CAa
L
DQ
QAa1 QAa2
ACT-A
QAa3
RD-A
PD Entry
PD Exit
ACTIVE STANDBY
QAa4
PRE-A
Clock Mask
Start
Clock Mask
End
PD
PD
PRECHARGE STANDBY
48/66
¡ Semiconductor
MSM54V25632A
CLOCK Suspend Exit & Power Down Exit
,
1) Clock Suspend (= Active Power Down) Exit
2) Power Down (= Precharge Power Down) Exit
CLK
CLK
CKE
(CASE 1)
CKE
Internal
CLK
tCKS
Internal
CLK
Note 1
Command
RD
Command
4.
≥ tPDE
Note 2
ACT
Command
(CASE 2)
CKE
Internal
CLK
Notes: 1.
2.
3.
Note 3
Note 4
< tPDE
Note 2
NOP
ACT
Active power down: one or both bank active state.
Precharge power down: both bank precharge state.
tPDE: Asynchronous AC parameter. Time for Power Down Exit Setup Time. Only
valid at precharge power down exit.
tCKS < tPDE, NOP should be issued. And new command can be issued after 1 Clock.
49/66
¡ Semiconductor
MSM54V25632A
|y,{~|y,z}€{~}€
|y,~{|y,z}€~{}€z
Byte Read/Write Operation (by DQM) (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
ADD
RBa
CBa
CBb
CBc
DQM
DQM0
DQM1
DQ
0-7
QBa1 QBa2 QBa3
DQ
8 - 15
DBb2 DBb3
QBa2 QBa3 QBa4
ACT-B
RD-B
Byte of
DQ8 - 15
not Read
Byte of
DQ0 - 7
not Read
DBb1 DBb2
QBc2 QBc3
DBb4
Byte of RD-B
DQ8 - 15
not Write
QBc1 QBc2 QBc3 QBc4
Byte of
DQ0 - 7
not Read
Byte of
DQ0 - 7
not Read
Byte of DQ0 - 7
not Write
Byte of DQ0 - 7
not Write
WT-B
50/66
¡ Semiconductor
MSM54V25632A
Burst Read and Single Write (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
|~y{,}€z~}€,y|z{
|y{~,z}€{~z,y}€|
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
ADD
RBa
CBb
CBa
CBc
CBd
CBe
DQM0
DQM1
DQ
0-7
DQ
8 - 15
QBa1 QBa2 QBa3 QBa4
DBb
Write
Masking
DBc
ACT-B
RD-B
Single
WT
Single
WT
DBe
QBd1
RD
Single
WT
51/66
¡ Semiconductor
MSM54V25632A
Special Mode Register Set (BL = 4, CL = 2)
0
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
|y,}z|y,}z~{
|y,€}z,y|€z}~{
CLK
1
H
tRSC (20 ns)
ADDRESS KEY
ADD
DQM
0-3
Color or Mask data
DQ
PRE
SMRA
(All Banks)
Hi-Z
ACT
is valid
tRP
Remark Special Register Set command can be input at any state.
52/66
¡ Semiconductor
MSM54V25632A
Random Row Write with WPB (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
,yz{y,z
|,y€z}~{,y|}z€
|}€y,z~{,y|z}€
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
RBa
CAa
RBa
RAb
CBa
RAb
CAb
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3
DQ
ACT-A
WT-A
with WPB WPB is enabled.
tRCD
ACT-B
WT-B
PRE-A
WPB is disabled.
tDPL
ACT-A
tRP
WT-A
PRE-B
WPB is disabled.
tDPL
53/66
¡ Semiconductor
MSM54V25632A
Block Write (Page at Same Bank) (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
18
19
CLK
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
DQ
H
|}~zy,{~{|y,z}
|,yz{}~€~{z}€,y|
CKE
RBb
RBa
RBa
RBb
CBc
CBa
CBb
CBc
CBd
I/O Mask
I/O Mask
I/O Mask
I/O Mask
I/O Mask
CM
CM
CM
CM
CM
BW-B
BW-B
BW-B
BW-B
L = No I/O Mask
ACT-B
tRCD
tBWC
tBWC
tBWC
PRE-B
tBPL
ACT-B
BW-B
with WPB WPB is enabled.
tRP
tRCD
54/66
¡ Semiconductor
MSM54V25632A
y,,y{zz{
|y,,y|z}€{~}€z~{
|y,,y|}€z{~€{~z}
Block Write (Page at Same Bank) Changing Color and Mask Data (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
ADD
RBa
RBb
CBa
20h
I/O Mask
DQM
0-3
CM
DQ
ACT-B
with WPB
BW-B
tRCD
CBb
40h
I/O Mask
Mask
CM
Color
CBc
CBd
I/O Mask
I/O Mask
CM
CM
SMRA
BW-B
SMRA
BW-B
(Mask data)
(Color data)
tBWC
tRSC (20 ns)
tBWC
tRSC (20 ns)
RBb
BW-B
tBWC
PRE-B
tBPL
ACT-B
tRCD
55/66
¡ Semiconductor
MSM54V25632A
Interleaved Block Write (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
H
CS
yz,{yz,{
|,yz}€{~|}€,yz{~
,yz|}€~{€,yz|}{~
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RBa
ADD
RAa
CAa RBa
DQM
0-3
RBb
CBa
CAb
CBb
CM
CM
CM
RBb
L
Column Mask
CM
DQ
ACT-A
ACT-B
PRE-B
BW-A
tRCD
BW-B
tRCD
BW-A
tBWC
ACT-B
BW-B
tBWC
tBPL
tRP
56/66
¡ Semiconductor
MSM54V25632A
|y,|,y€}~{z~{
|y,,y|€}~z{~{
Random Column Read (Page with Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
RAa
CAa
CAb
CAc
RAa
CAa
ACT-A
RD-A
L
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
DQ
ACT-A
RD-A
RD-A
PRE-A
RD-A
tRP
57/66
¡ Semiconductor
MSM54V25632A
Random Column Write (Page with Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
,yzz{y,
,y|€z}€z{}~|y,
€|},yz€z{}~|y,
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
ADD
RBa
DQM
0-3
RBd
CBa
CBb
CBc
RBd
CBd
L
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
DQ
ACT-B
WT-B
WT-B
DBd1
ACT-B
PRE-B
WT-B
WT-B
tRP
58/66
¡ Semiconductor
MSM54V25632A
Random Row Read (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CS
RAS
CAS
WE
DSF
A9
(BA)
|}y,zz{~}|y,
€,y|}z€z}{~|y,
CKE
H
A8
RBa
ADD
RBa
DQM
0-3
RAa
CBa
RAa
RBb
CAa
RBb
CBb
L
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8
DQ
ACT-B
RD-B
tRCD
ACT-A
CL
RD-A
PRE-B
ACT-B
RD-B
PRE-A
tRP
59/66
¡ Semiconductor
MSM54V25632A
Random Row Write (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
CAS
WE
DSF
A9
(BA)
}~,y|{z{~
y|€{~}z,{~
RAS
A8
RAa
ADD
RAa
DQM
0-3
DQ
RBa
CAa
RBa
RAb
CBa
RAb
CAb
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3
ACT-A
WT-A
tRCD
ACT-B
WT-B
tDPL
PRE-A
ACT-A
tRP
WT-A
PRE-B
tDPL
60/66
¡ Semiconductor
MSM54V25632A
READ and WRITE (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
z}€|y,}~€z{|y,
€|},yz}€~|z{,y
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
CAa
CAb
CAc
Write latency = 0
DQM
0-3
Write Masking
QAa1 QAa2 QAa3 QAa4
DQ
ACT-A
RD-A
DAb1 DAb2
WT-A
DAb4
QAc1 QAc2
Hi-Z
RD-A
0-clock latency
Hi-Z at the end of Burst function
2-clock latency
61/66
¡ Semiconductor
MSM54V25632A
y,|{~zy,|}€~{
|y,~{|y,€}z~{
Interleaved Column READ Cycle (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RBa
ADD
RAa
CAa RBa
DQM
0-3
CBa
CBb
CBc
CAb
L
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBb2 QBc1 QBc2 QAb1 QAb2 QAb3 QAb4
DQ
ACT-A
RD-A
RD-B
RD-B
RD-B
RD-A
PRE-B
PRE-A
ACT-B
tRCD
CL
tRRD
62/66
¡ Semiconductor
MSM54V25632A
Interleaved Column WRITE Cycle (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
DQ
H
|z}y,~{~z{}
}~€z,y{|z{~}€
CKE
RAa
RBa
RAa
CAa RBa
CBa
CBb
CBc
CAb
CBd
L
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DBc1 DBc2 DAb1 DAb2 DBd1 DBd2 DBd3 DBd4
ACT-A
WT-A
ACT-B
tRCD
WT-B
WT-B
WT-B
WT-A
WT-B
PRE-B
PRE-A
tDPL
tDPL
tRRD
63/66
¡ Semiconductor
MSM54V25632A
Full Page Random Column Read (BL = Full Page, CL = 2)
0
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
y|,z}z}y|,{~
€,yz|}€,yz|}{~
CLK
1
H
RAa
RAa
L
RBa
RBa CAa CBa CAb
tRCD
tRRD
tRCD
CBb
CAc
CBc
QAa1 QBa1 QAb1 QAb2 QBb1 QBb2 QAc1 QAc2 QAc3 QBc1 QBc2 QBc3
DQ
Hi-Z
ACT-A
ACT-B
RD-B
RD-A
RD-A
RD-B
RD-A
RD-B
PRE-B
(PRE Termination)
64/66
¡ Semiconductor
MSM54V25632A
Full Page Random Column Write (BL = Full Page, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
yz,{z
|,y€z}~€z}{
€

€|}€}~
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
ADD
RAa
DQM
0-3
L
RBa
RBa CAa CBa CAb
tRCD
tRRD
tRCD
CBb
CAc
CBc
DAa1 DBa1 DAb1 DAb2 DBb1 DBb2 DAc1 DAc2 DAc3 DBc1 DBc2 DBc3
DQ
ACT-A
ACT-B
WT-B
WT-A
WT-B
WT-A
WT-B
PRE-B
(PRE Termination)
WT-A
65/66
¡ Semiconductor
MSM54V25632A
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK4
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
66/66
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan