FUJITSU MB81ES653225-12L

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11411-2E
MEMORY
CMOS
2 × 1 M × 32-BIT
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES653225-12/-12L
CMOS 2-Bank × 1,048,576-Word × 32-Bit
Fast Cycle Random Access Memory (FCRAM) with Single Data Rate for SiP
■ DESCRIPTION
The Fujitsu MB81ES653225 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 67,108,864 memory cells accessible in a 32-bit format. The MB81ES653225 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES653225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES653225 is dedicated for SiP (System in a package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINE
MB81ES653225
Parameter
Clock Frequency (Max)
Burst Mode Cycle Time (Min)
Access Time from Clock (Max)
12
12L
CL = 2
54.0 MHz
CL = 3
85.0 MHz
CL = 2
18.5 ns
CL = 3
11.7 ns
CL = 2
12 ns
CL = 3
8.7 ns
Operating Current (Max) (32 page length)
35 mA
Power Down Mode Current (Max)
0.5 mA
0.1 mA
Self Refresh Current (Max) (Ta = +85 °C)
1000 µA
450 µA
MB81ES653225-12/-12L
■ FEATURES
• 1 M word × 32 bit × 2 banks organization
• Low power supply
- VDD : + 1.8 V ± 0.15 V
- VDDQ : + 1.8 V ± 0.15 V
• 1.8 V-CMOS I/O interface
• 8 K refresh cycles every 32 ms
• Auto-and Self-refresh
• Two banks operation
• Burst read/write operation and burst read/single write operation capability
• Programmable burst type, burst length, and CAS Latency
• Programmable page length function
• Programmable Partial Array Self Refresh (PASR)
• Programmable Temperature Compensated Self Refresh (TCSR)
• Deep power down mode
• Extended temperature operation
- MB81ES653225-12 : From 0 °C to +85 °C (Ta)
- MB81ES653225-12L : From −25 °C to +85 °C (Ta)
• CKE power down mode
• Output enable and input data mask
• Disable function for TEST
• Self burnin function for TEST
• Built In Self Test (BIST) function for TEST
2
MB81ES653225-12/-12L
■ PAD LAYOUT
⎯
VDD
VSS
A9
A12
⎯
A13
TBST
A14
⎯
BME
⎯
⎯
⎯
⎯
⎯
DQM1
DQM3
⎯
⎯
VDDQ
DSE
VSSQ
DQ8
DQ9
DQ10
DQ11
VDDQ
VSSQ
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
VDDQ
VSSQ
DQ28
DQ29
DQ30
DQ31
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VDD
VSS
Pad No. 137
Pad No. 1
Pad No. 72
Pad No. 71
VDD
VSS
CKE
CLK
CSB
RASB
CASB
WEB
BA
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
DQM0
DQM2
⎯
⎯
VDDQ
VSSQ
DQ0
DQ1
DQ2
DQ3
VDDQ
VSSQ
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
VDDQ
VSSQ
DQ20
DQ21
DQ22
DQ23
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VDD
VSS
⎯
⎯
3
MB81ES653225-12/-12L
■ PAD DESCRIPTIONS
Symbol
VDDQ, VDD
Function
Supply Voltage
DQ31 to DQ0
Data I/O
VSSQ, VSS
Ground
WE (WEB)
Write Enable
CAS (CASB)
Column Address Strobe
RAS (RASB)
Row Address Strobe
CS (CSB)
Chip Select
BA
Bank Select (Bank Address)
AP
Auto Precharge Enable
A14 to A0 *
Address Input
CKE
Clock Enable
CLK
Clock Input
DQM3 to DQM0
Row
Column
128 page
A12 to A0
A6 to A0
64 page
A13 to A0
A5 to A0
32 page
A14 to A0
A4 to A0
Input Mask/Output Enable
DSE
Disable Mode Entry (apply VSS except Disable Mode)
BME
Self Burn-in Mode Entry (apply VSS except Self Burn-in Mode)
TBST
BIST Mode Entry (apply VSS except BIST Mode)
⎯
Don’t Bond
* : A13 must be connected to VSS in 128 page length mode. A14 must be connected to VSS in 128 page length
mode and 64 page length mode.
4
MB81ES653225-12/-12L
■ BLOCK DIAGRAM
To each block
CLK
CLOCK
BUFFER
BANK-1
CKE
BANK-0
RAS
CS
CONTROL
SIGNAL
LATCH
RAS
CAS
COMMAND
DECODER
WE
CAS
WE
DSE
BME
TBST
MODE
REGISTER
A9 to A0,
A10/AP,
A14 to A11
BA
ROW
ADDRESS
ADDRESS
BUFFER/
REGISTER
COL.
ADDRESS
COLUMN
ADDRESS
COUNTER
DQM3
to
DQM0
DQ31
to
DQ0
FCRAM
CORE
(1,048,576 × 32)
I/O DATA
BUFFER/
REGISTER
I/O
VDDQ
VDD
VSS
VSSQ
5
MB81ES653225-12/-12L
■ FUNCTIONAL TRUTH TABLE *1
1. COMMAND TRUTH TABLE *2, *3, *4
CKE
BA
A10
(AP)
Address
(Except for A10)
X
X
X
X
H
H
X
X
X
H
H
L
X
X
X
L
H
L
H
V
L
Column Address
X
L
H
L
H
V
H
Column Address
H
X
L
H
L
L
V
L
Column Address
WRITA
H
X
L
H
L
L
V
H
Column Address
ACTV
H
X
L
L
H
H
V
Precharge Single Bank
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
H
X
MRS
H
X
L
L
L
L
V
V
V
Function
Symbol
Device Deselect *5
No Operation *
5
6, 7
Burst Stop * *
Read *7
Read with Auto-precharge *7
Write *
7
Write with Auto-precharge *
Bank Active *8
9, 10
Mode Register Set * *
7
CS
RAS CAS WE
n-1
n
DESL
H
X
H
X
X
NOP
H
X
L
H
BST
H
X
L
READ
H
X
READA
H
WRIT
Row Address
*1 : V = Valid, L = Logic Low, H = Logic High, X = either L or H.
Row Address
128 page length : A12 to A0
64 page length : A13 to A0
32 page length : A14 to A0
Column Address
128 page length : A6 to A0
64 page length : A5 to A0
32 page length : A4 to A0
*2 : All commands assume no CSUS command on previous rising edge of clock.
*3 : All commands are assumed to be valid state transitions.
*4 : All inputs are latched on the rising edge of clock.
*5 : NOP and DESL commands have the same effect. Unless specifically noted, NOP will represent both NOP and
DESL command in later description.
*6 : When the current state is idle and CKE = L, BST command will represent Deep Power Down command.
Refer to “3. CKE TRUTH TABLE” in section “■FUNCTION TRUTH TABLE”.
*7 : READ, READA, WRIT, WRITA and BST commands should only be issued after the corresponding bank has
been activated (ACTV command) . Refer to “■STATE DIAGRAM”.
*8 : ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL command) .
*9 : Required after power up. Refer to “22. POWER-UP INITIALIZATION” in section “■FUNCTIONAL
DESCRIPTION”.
*10 : MRS command should only be issued after all banks have been precharged (PRE or PALL command) .
Refer to “■STATE DIAGRAM”.
6
MB81ES653225-12/-12L
2. DQM TRUTH TABLE
Function
CKE
Symbol
n-1
n
DQMi *1, *2
Data Write/Output Enable
ENBi *1
H
X
L
Data Mask/Output Disable
MASKi *1
H
X
H
*1 : i = 0, 1, 2, 3
*2 : DQM0 for DQ7 to DQ0, DQM1 for DQ15 to DQ8, DQM2 for DQ23 to DQ16, DQM3 for DQ31 to DQ24
3. CKE TRUTH TABLE *1
CKE
Current State
Function
Command
n-1
n
CS
RAS CAS WE
BA
A10
(AP)
Address
(Except
for A10)
Bank Active
Clock Suspend
Mode Entry *2
CSUS
H
L
X
X
X
X
X
X
X
Any
(Except Idle)
Clock Suspend
Continue *2
⎯
L
L
X
X
X
X
X
X
X
Clock Suspend
Clock Suspend
Mode Exit
⎯
L
H
X
X
X
X
X
X
X
Idle
Auto-refresh
Command *3
REF
H
H
L
L
L
H
X
X
X
Idle
Self-refresh Entry
*3, *4
SELF
H
L
L
L
L
H
X
X
X
Self Refresh
Self-refresh Exit *5
SELFX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
Idle
Power Down Entry
*3, *4
PD
H
L
L
H
H
H
X
X
X
H
L
H
X
X
X
X
X
X
Power Down
Power Down Exit
PDX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
Idle
Deep Power Down
Entry *3, *4
DPD
H
L
L
H
H
L
X
X
X
Deep Power
Down
Deep Power Down
Exit
DPDX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
*1 : Address : A12 to A0 @128 page length mode
: A13 to A0 @64 page length mode
: A14 to A0 @32 page length mode
*2 : The CSUS command requires that at least one bank is active. Refer to “■STATE DIAGRAM”.
*3 : REF, SELF, DP and DPD commands should only be issued after all banks have been precharged
(PRE or PALL command) . Refer to “■STATE DIAGRAM”.
*4 : SELF, PD and DPD commands should only be issued after the last read data have been appeared on DQ.
*5 : CKE should be held high within one tRC period after tCKSP.
7
MB81ES653225-12/-12L
4. OPERATION COMMAND TABLE (single bank operation) *1
Current
State
Idle
Bank Active
Read
CS
RAS
CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
NOP *5
L
L
L
H
X
REF/SELF
Auto-refresh or Self-refresh *3, *6
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA Begin Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, New Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, Start Write;
Determine AP *4
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
NOP
Illegal *2
Bank Active after tRCD
Mode Register Set
(Idle after tRSC) *3, *7
NOP
Begin Write; Determine AP
Illegal *2
Precharge; Determine Precharge
Type
Illegal
Illegal *2
Terminate Burst, Precharge →
Idle
Illegal
(Continued)
8
MB81ES653225-12/-12L
Current
State
Write
Read with
Autoprecharge
Write with
Autoprecharge
CS
RAS
CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, Start Read;
Determine AP *4
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, New Write;
Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
Illegal *2
Terminate Burst, Precharge →
Idle
Illegal
Illegal *2
Illegal
Illegal *2
Illegal
(Continued)
9
MB81ES653225-12/-12L
(Continued)
Current
State
Precharging
Bank
Activating
CS
RAS
CAS
WE
Address
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
X
X
NOP/BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
L
L
H
X
X
ACTV/
PRE/PALL
L
L
L
X
X
REF/SELF/
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
X
ACTV/PRE/
PALL/REF/
SELF/MRS
Refreshing
Mode
Register
Setting
L
L
X
X
RA = Row Address
BA = Bank Address
CA = Column Address AP = Auto Precharge
10
Function
NOP (Idle after tRP)
NOP (Idle after tRP) *8
Illegal *2
NOP (PALL may affect other
bank) *5
Illegal
NOP (Bank Active after tRCD)
Illegal *2
Illegal
NOP (Idle after tRC)
NOP (Idle after tRC) *8
Illegal
NOP (Idle after tRSC)
Illegal
MB81ES653225-12/-12L
*1 : All command entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
After illegal commands are asserted, following command function and data could not be guaranteed.
If used, power up sequence be asserted after power shout down.
*2 : Illegal to bank in the specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*3 : Illegal if any bank is not idle.
*4 : Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “11. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4) ” and “12. WRITE
TO READ TIMING (EXAMPLE @ CL = 2, BL = 4) ” in section “■TIMING DIAGRAMS”.
*5 : NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP) .
*6 : SELF command should only be issued after the last read data have been appeared on DQ.
*7 : MRS command should only be issued on condition that all DQ are in Hi-Z.
*8 : BST command should only be issued with CKE = “H”.
11
MB81ES653225-12/-12L
5. COMMAND TRUTH TABLE FOR CKE *1
Current State
Selfrefresh
Selfrefresh
Recovery
Power
Down
Deep Power
Down
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
Exit Self-refresh
(Self-refresh Recovery
→ Idle after tRC)
L
H
L
H
H
L
X
L
H
L
H
L
X
X
L
H
L
L
X
X
X
L
L
X
X
X
X
X
NOP (Maintain Self-refresh)
L
X
X
X
X
X
X
Invalid
H
H
H
X
X
X
X
H
H
L
H
H
H
X
H
H
L
H
H
L
X
H
H
L
H
L
X
X
H
H
L
L
X
X
X
H
H
X
X
X
X
X
H
L
X
X
X
X
X
Illegal *2
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
L
L
X
X
X
X
X
L
H
L
L
X
X
X
L
H
L
H
L
X
X
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
Exit Deep Power Down Mode →
Idle *3
L
L
X
X
X
X
X
L
H
L
L
X
X
X
L
H
L
H
L
X
X
Function
Illegal
Idle after tRC
Illegal
Exit Power Down Mode → Idle
NOP
(Maintain Power Down Mode)
Illegal
NOP (Maintain Deep Power Down
Mode)
Illegal
(Continued)
12
MB81ES653225-12/-12L
(Continued)
Current State
Bank Active
Bank
Activating
Read/Write
All Banks Idle
Precharging
Refreshing
Clock
Suspend
Any State
Other Than
Listed Above
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
X
X
X
X
X
Refer to “4. Operation Command
table”. Start Clock Suspend next
cycle
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
L
H
H
L
X
Illegal
H
L
H
X
X
X
X
H
L
L
L
X
X
X
H
L
L
H
L
X
X
H
L
L
H
H
H
X
L
X
X
X
X
X
X
Invalid
H
X
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
X
X
X
X
X
Illegal
Function
Refer to “4. Operation Command
Table”.
*1 : All entries are specified at CKE (n) state. CKE input must satisfy corresponding set up and hold time for CKE.
*2 : CKE should be held High for tRC period after tCKSP.
*3 : After deep power down exit, it requires “19. DEEP POWER DOWN EXIT TIMINIG” procedure in section
“■TIMING DIAGRAMS”.
13
MB81ES653225-12/-12L
■ FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM BASIC FUNCTION
Three major differences between this SDR I/F FCRAMs and conventional DRAMs are : synchronized operation,
burst mode, and mode register.
The synchronized operation is the fundamental difference. An SDR I/F FCRAM uses a clock input for the
synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks,
RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation
of SDR I/F FCRAM is determined by commands and all operations are referenced to a positive clock edge.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to justify the SDR I/F FCRAM operation and function into desired system conditions. Refer
to “■MODE REGISTER TABLE”.
2. FCRAMTM
The MB81ES653225 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. A CLK is used as a trigger for the
register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are
validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during
active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the
Power Down mode (standby) is entered with CKE = Low and this will make low standby current. The standby
current of the Deep Power Down mode is lower than that of the Power Down mode. This mode is entered with
CKE = Low, RAS = CAS = High and WE = Low.
4. CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals
are negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS
can be tied to ground level.
5. COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDR I/F FCRAM operation, such as Row
address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at
a rising edge of the CLK determines SDR I/F FCRAM operation. Refer to “1. COMMAND TRUTH TABLE” in
section “■FUNCTIONAL TRUTH TABLE.”
6. ADDRESS INPUT (A14 to A0)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Address
field is defined for selected page length by the Programmable Page Length mode : 128 page length = A12 to A0,
64 page length = A13 to A0, 32 page length = A14 to A0. A total of twenty address input signals are required to
decode such a matrix. SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the
address line. At a Bank Active command (ACTV) , Row addresses are initially latched and the remainder of
Column addresses are then latched by a Column address strobe command of either a Read command (READ
or READA) or Write command (WRIT or WRITA) .
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MB81ES653225-12/-12L
7. BANK SELECT (BA)
This SDR I/F FCRAM has two banks in one part and each bank is organized as 1 Mwords by 32-bit. Bank
selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or
WRITA) , and precharge command (PRE) .
8. DATA INPUT AND OUTPUT (DQ31 to DQ0)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input :
tRAC; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.)
tCAC; from the read command when tRCD is greater than tRCD (Min) . (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH) .
9. DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked
at the second clock later while internal burst counter will increment by one or will go to the next stage depending
on burst type. DQM0, DQM1, DQM2, DQM3, controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, DQ31 to DQ24,
respectively.
10. BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same row
address and by automatic strobing column address. Access time and cycle time of burst mode is specified as
tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which
defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary or full column. In order to terminate or
to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following
combinations will be required.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Burst Read
Burst Write
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
Read Command
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after lOWD
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential
mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns
+ 1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least
significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A2 and A0. If the first access
of column address is even (0) , the next address will be odd (1) , or vice-versa. When the full column burst
operation is executed at single write mode, Auto-precharge command is valid only at write operation.
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MB81ES653225-12/-12L
Burst
Length
2
4
8
Starting Column
Address
A2 A1 A0
Sequential Mode
Interleave Mode
X X 0
0−1
0−1
X X 1
1−0
1−0
X 0 0
0−1−2−3
0−1−2−3
X 0 1
1−2−3−0
1−0−3−2
X 1 0
2−3−0−1
2−3−0−1
X 1 1
3−0−1−2
3−2−1−0
0 0 0
0−1−2−3−4−5−6−7
0−1−2−3−4−5−6−7
0 0 1
1−2−3−4−5−6−7−0
1−0−3−2−5−4−7−6
0 1 0
2−3−4−5−6−7−0−1
2−3−0−1−6−7−4−5
0 1 1
3−4−5−6−7−0−1−2
3−2−1−0−7−6−5−4
1 0 0
4−5−6−7−0−1−2−3
4−5−6−7−0−1−2−3
1 0 1
5−6−7−0−1−2−3−4
5−4−7−6−1−0−3−2
1 1 0
6−7−0−1−2−3−4−5
6−7−4−5−2−3−0−1
1 1 1
7−0−1−2−3−4−5−6
7−6−5−4−3−2−1−0
11. FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full
column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address,
then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read
(READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge
option is illegal during the full column burst operation.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the
burst mode, its operation is terminated immediately and the internal state moves to Bank Active.
When a read mode is interrupted by the BST command, the output will be in High-Z. For the detailed rule, please
refer to “8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 2, BL = Full Column” in section “■TIMING DIAGRAMS”. When a write mode is interrupted by the BST command, the data to be applied at the same
time with the BST command will be ignored.
12. BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
13. PROGRAMMABLE PAGE LENGTH FUNCTION
The programmable page length function provides lower operation current than regular SDRAM. Page length is
selected by Mode Register Set, and row address field and column address field are defined for selected page
length as below.
128 page length
64 page length
32 page length
16
Row address
A12 to A0
A13 to A0
A14 to A0
Column address
A6 to A0
A5 to A0
A4 to A0
MB81ES653225-12/-12L
Row/column address allocation at each page length is shown as the following table. For example, A14 (row
address) at 32 page length mode is corresponded to A5 (column address) at 64 page length mode.
32 page
64 page
128 page
Row : A14 to A0
0
1
2
Column : A4 to A0
3
4
5
6
7
8
9
10
11
12
13
14
4
Row : A13 to A0
0
1
2
1
2
2
1
0
Column : A0 to A5
3
4
5
6
7
8
9
10
11
12
13
5
4
Row : A12 to A0
0
3
3
2
1
0
Column : A6 to A0
3
4
5
6
7
8
9
10
11
12
6
5
4
3
2
1
0
14. PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDR I/F FCRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations.
Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge
command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby state after
precharge time (tRP) . The precharged bank is selected by combination of AP and BA when Precharge command
is asserted. If AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected
by BA is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or
write without Precharge command assertion. This auto precharge is entered by AP = High when a read or write
command is asserted. Refer to “1. COMMAND TRUTH TABLE” in section “■FUNCTIONAL TRUTH TABLE”.
15. AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDR I/F FCRAM Auto-refresh command (REF)
generates Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Autorefresh command. The Auto-refresh command should also be asserted every 3.9 µs or a total 8192 refresh
commands within 32 ms period.
16. SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command
in conjunction with CKE = Low (SELF) . Once SDR I/F FCRAM enters the self-refresh mode, all inputs except
for CKE will be “don’t care” (either logic high or low level state) and outputs will be in a High-Z state. During a
self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data
has been appeared on DQ
Note : When the burst refresh method is used, a total of 8,192 auto-refresh commands within 2 ms must be asserted
prior to the self-refresh mode entry.
17. SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command
(NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High
within one tRC period after tCKSP. Refer to “16. SELF-REFRESH ENTRY AND EXIT TIMING” in section “■TIMING
DIAGRAMS” for the detail. It is recommended to assert an Auto-refresh command just after the tRC period to
avoid the violation of refresh period.
Note : When the burst refresh method is used, a total of 8,192 auto-refresh commands within 2 ms must be asserted
after the self-refresh exit.
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MB81ES653225-12/-12L
18. MODE REGISTER SET (MRS)
The mode register of SDR I/F FCRAM provides a variety of different operations. The register consists of five
operation fields; Burst Length, Burst Type, CAS latency, Operation Code and Page length. Refer to “■MODE
REGISTER TABLE”. The mode register can be programmed by the Mode Register Set command (MRS) . Once
a mode register is programmed, the contents of the register will be held until re-programmed by another MRS
command. MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode
register is undefined after the power-up stage. It is required to set each field after initialization of SDR I/F FCRAM.
Refer to “22. POWER-UP INITIALIZATION”.
19. EXTENDED MODE REGISTER SET (EMRS)
The extended mode register consists of two operation fields; Partial Array Self Refresh (PASR) and Temperature
Compensated Self Refresh (TCSR) . Refer to “■MODE REGISTER TABLE”. The condition of the extended
mode register is undefined after the Power-up stage. It is required to set each field after initialization of SDR I/F
FCRAM. Refer to “22. POWER-UP INITIALIZATION”.
20. PARTIAL ARRAY SELF REFRESH (PASR)
Memory array size to be refreshed during self refresh operation is programmable in order to reduce self refresh
current. Data outside the defined area will not be retained during self refresh.
21. TEMPERATURE COMPENSATED SELF REFRESH (TCSR)
Programmable refresh rate for self refresh mode allows the system to control power as a function of temperature.
22. POWER-UP INITIALIZATION
The SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following
Power On Sequence to execute read or write operation.
1. Apply power (VDD should be applied before or in parallel with VDDQ) and start clock. Attempt to maintain either
NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL) .
4. Assert minimum of 2 Auto-refresh command (REF) .
5. Program the mode register by Mode Register Set command (MRS) .
6. Program the extended mode register by Extended Mode Register Set command (EMRS) .
In addition, it is recommended DQM and CKE track VDD to insure that output is High-Z state. The Mode Register
Set command (MRS) and Extended Mode Register Set command (EMRS) can be set before 2 Auto-refresh
command (REF) .
23. DISABLE MODE
When DSE is applied high level, SDR I/F FCRAM entries Disable mode. Disable mode entry doesn’t require
clock. In Disable mode, SDR I/F FCRAM current consumption is less than IDD2PS and the output is High-Z. Any
command isn’t accepted in this mode. To exit Disable mode, apply Low level to DSE.
24. SELF BURNIN MODE
When BME is applied High level, SDR I/F FCRAM entries Self Burnin mode. Self Burnin mode entry doesn’t
require clock. In SELF BURNIN mode, self refresh command is asserted internally. Any command isn’t accepted
in this mode. To exit Self Burnin mode, apply Low level to BME.
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MB81ES653225-12/-12L
25. BIST MODE
When TBST is applied High level, SDR I/F FCRAM entries BIST mode. BIST mode entry dosen’t require clock.
To exit BIST mode, apply Low level to TBST.
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MB81ES653225-12/-12L
■ STATE DIAGRAM
MRS
MODE
REGISTER
SET
SELF
EMRS
CKE(DPDX)
REF
CKE\
(DPD)
DEEP
POWER
DOWN
AUTO
REFRESH
POWER
DOWN
CKE\ (CSUS)
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
CKE
BST
WRIT
WRITA
WRITE
CKE
CKE\ (CSUS)
WRITE
SUSPEND
POWER
ON
POWER
APPLIED
CKE
WRITE WITH
AUTO
PRECHARGE
CKE\ (CSUS)
READ
WRIT
WRITA
READA
WRITA
PRE
or
PALL
PRE or PALL
READ
READA
READ
PRE or PALL
WRITE
SUSPEND
BST
READ
WRIT
CKE\ (CSUS)
PRE
or
PALL
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
CKE
READ
SUSPEND
READA
READ WITH
AUTO
PRECHARGE
Automatic
Sequence
Note : CKE\ means CKE goes Low-level from High-level.
20
CKE
CKE\
(PD)
ACTV
EXTENDED
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
CKE\ (CSUS)
CKE
READ
SUSPEND
MB81ES653225-12/-12L
■ BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
Second command
(same
*4
*4
bank) MRS ACTV READ READA WRIT WRITA PRE
First command
PALL
REF
SELF
BST
MRS
tRSC
tRSC
⎯
⎯
⎯
⎯
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
⎯
⎯
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
⎯
⎯
1
READ
⎯
⎯
1
1
*5
1
*5
1
*4
1
*4
1
⎯
⎯
1
*1, *2
BL
+ tRP
BL
+ tRP
⎯
⎯
⎯
⎯
*4
BL
+ tRP
*4
BL
+ tRP
*2
BL
+ tRP
*2, *7
BL
+ tRP
⎯
⎯
⎯
tWR
tWR
1
1
*4
*4
tDPL
tDPL
⎯
⎯
1
WRITA
*2
BL−1
+ tDAL
BL−1
+ tDAL
⎯
⎯
⎯
⎯
*4
BL−1
+ tDAL
*4
BL−1
+ tDAL
*2
BL−1
+ tDAL
*2
BL−1
+ tDAL
⎯
PRE
*2, *3
tRP
tRP
⎯
⎯
⎯
⎯
1
*4
1
*2
tRP
*2, *6
tRP
1
PALL
*3
tRP
tRP
⎯
⎯
⎯
⎯
1
1
tRP
*6
tRP
1
REF
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
READA
WRIT
SELFX
⎯ : Illegal Command
*1 : If tRP (Min) < CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2 : Assume all banks are in Idle state.
*3 : Assume output is in High-Z state.
*4 : Assume tRAS (Min) is satisfied.
*5 : Assume no I/O conflict.
*6 : Assume after the last data have been appeared on DQ.
*7 : If tRP (Min) < (CL − 1) × tCK, minimum latency is a sum of (BL + CL − 1) × tCK.
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MB81ES653225-12/-12L
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second command
(other
*5,*6
*5
*5, *6
*5
bank) MRS ACTV READ READA WRIT WRITA PRE PALL
First command
MRS
tRSC
2
⎯
⎯
⎯
⎯
tRSC
7
7
7
7
6, 7
tRSC
7
SELF
BST
tRSC
tRSC
tRSC
ACTV
⎯
*
tRRD
*
1
*
1
*
1
*
1
* *
1
*
tRAS
⎯
⎯
1
READ
⎯
*2, *4
1
1
1
*10
1
*10
1
*6
1
*6
1
⎯
⎯
1
*1, *2
BL +
tRP
*2, *4
1
*6
1
*6
1
*6, *10
1
*6, *10
1
*6
1
*6
BL +
tRP
*2
BL +
tRP
*2, *9
BL +
tRP
⎯
⎯
*2, *4
1
1
1
1
1
*6
1
*6
⎯
⎯
1
WRITA
*2
BL−1
+ tDAL
*2, *4
1
*6
1
*6
1
*6
1
*6
1
*6
1
PRE
*2, *3
tRP
*2, *4
1
*7
1
*7
1
*7
1
*7
1
*6, *7
1
*7
1
*2
tRP
*2, *8
tRP
1
PALL
*3
tRP
tRP
⎯
⎯
⎯
⎯
1
1
tRP
*8
tRP
1
REF
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
READA
WRIT
SELFX
⎯ : Illegal Command
*1
: If tRP (Min) < CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2
: Assume bank of the object is in Idle state.
*3
: Assume output is in High-Z state.
*4
: tRRD (Min) of other bank (second command will be asserted) is satisfied.
*5
: Assume other bank is in active, read or write state.
*6
: Assume tRAS (Min) is satisfied.
*7
: Assume other banks are not in READA/WRITA state.
*8
: Assume after the last data have been appeared on DQ.
*9
: If tRP (Min) < (CL − 1) × tCK, minimum latency is a sum of (BL + CL − 1) × tCK.
*10 : Assume no I/O conflict.
22
tRSC
REF
tDPL
*2
*2
*6
BL−1 BL−1 BL−1
+ tDAL + tDAL + tDAL
⎯
MB81ES653225-12/-12L
■ MODE REGISTER TABLE
MODE REGISTER SET
BA A14*5 A13*4 A12 A11 A10
0
A6
A5
0
A12
PAGE
LENGTH
A6
A5
A4 CAS Latency
0
0
0
Reserved
GND GND
1
128 page
0
0
1
GND
1
0
64 page
0
1
GND
1
1
Reserved
0
1
0
0
32 page
1
0
1
Reserved
1
1
0
1
1
1
1
CL
A3
A2
BT
A1
A0
ADDRESS
MODE
REGISTER
BL
A2
A1
A0
Reserved
0
0
0
2
0
1
1
3
1
0
0
1
0
1
Reserved
1
1
Reserved
1
1
A9
0
0
A4
Opcode
A13
0
A8*3 A7*3
0
A14
PL
A9
Burst Length
BT = 0
BT = 1*2
0
1
Reserved
0
1
2
2
0
1
0
4
4
Reserved
0
1
1
8
8
Reserved
1
0
0
Reserved
Reserved
0
Reserved
1
0
1
Reserved
Reserved
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full
Column
Reserved
Op-code
Burst Read & Burst Write
Burst Read & Single Write
*1
A3
Burst Type
0
Sequential (Wrap round, Binary-up)
1
Interleave (Wrap round, Binary-up)
EXTENDED MODE REGISTER
BA A14*5 A13*4 A12 A11
1
0
0
0
0
A10
A9
A8
A7
A6
A5
0
0
0
0
0
0
A4
A3
A2
A1
A0
ADDRESS
EXTENDED MODE
REGISTER
TCSR
PASR
SELF REFRESH AREA
A4
A3
MAX TEMPERATURE (Ta) *6
A2
A1
A0
0
0
+ 70 °C
0
0
0
64 M bit
0
1
+ 45 °C
0
0
1
32 M bit (RA11 = 0)
1
0
+ 15 °C
0
1
0
16 M bit (RA11 = RA10 = 0)
1
1
+ 85 °C
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
*1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 are reserved for vender test.
*4. A13 exists at operation with 32 and 64 page length mode.
*5. A14 exists at operation with 32 page length mode.
*6. Ta is ambient temperature.
23
MB81ES653225-12/-12L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Storage Temperature
Rating
Symbol
Min
− 0.5
− 0.5
− 50
⎯
− 55
VDD, VDDQ
VIN, VOUT
IOUT
PD
TSTG
Max
+ 3.0
+ 3.0
+ 50
1.0
+ 125
Unit
V
V
mA
W
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Input High Voltage *1
Input Low Voltage *2
Junction
Temperature *3
MB81ES653225-12
MB81ES653225-12L
MB81ES653225-12
MB81ES653225-12L
Ta
Tj
3.0 V
VIH
VIH
VIH Min
VIL
Min
1.65
0
VDDQ × 0.8
−0 .3
0
− 25
0
− 25
VDD, VDDQ
VSS, VSSQ
VIH
VIL
Supply Voltage
Ambient
Temperature
Symbol
50% of pulse amplitude
Pulse width ≤ 5 ns
*1 : Overshoot limit :
VIH (Max) = 3.0 V for pulse width ≤ 5 ns,
pulse width measured at 50% of pulse amplitude.
VIL Max
VIL
Value
Typ
1.8
0
⎯
⎯
⎯
⎯
⎯
⎯
Max
1.95
0
VDDQ + 0.3
VDDQ × 0.2
+ 85
+ 85
+ 100
+ 100
Unit
V
V
V
V
°C
°C
°C
°C
Pulse width ≤ 5 ns
50% of pulse amplitude
−1.0 V
*2 : Undershoot limit :
VIL (Min) = VSSQ − 1.0 V for pulse width ≤ 5 ns,
pulse width measured at 50% of pulse amplitude.
*3 : The maximum junction temperature of FCRAM (Tj) should not be more than 100 °C.
Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI (PD) , the thermal resistance
of the package (θ ja) , and the maximum ambient temperature of the SiP (Tamax) .
Σ pmax[W] = PFCRAM + PD
Tjmax[ °C] = Tamax[ °C] + θ ja[ °C/W] × Σ pmax[W]
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MB81ES653225-12/-12L
■ CAPACITANCE
(Ta = +25 °C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance, Except for CLK
CIN1
1.5
⎯
3.0
pF
Input Capacitance for CLK
CIN2
1.5
⎯
3.0
pF
I/O Capacitance
CI/O
2.0
⎯
4.0
pF
25
MB81ES653225-12/-12L
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
Value
Condition
Output High Voltage
VOH (DC) IOH = −0.1 mA
Output Low Voltage
VOL (DC) IOL = 0.1 mA
Unit
Min
Max
VDDQ − 0.2
⎯
V
⎯
0.2
V
Input Leakage
Current
ILI
0 V ≤ VIN ≤ VDDQ;
All other pins not under test = 0 V
−5
5
µA
Output Leakage
Current
ILO
0 V ≤ VIN ≤ VDDQ;
Data out disabled
−5
5
µA
Operating Current
(Average Power
Supply Current)
IDD1
-12
IDD2P
Burst Length = 1
tRC = Min, tCK = Min
One bank active
128 page length
⎯
50
Output pin open
Address changed up to
1 time during
64 page length
⎯
40
tRC (Min)
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
32 page length
⎯
35
⎯
1
CKE = VIL
All banks idle tCK = Min
Power down mode
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
mA
mA
⎯
0.4
CKE = VIL
All banks idle
CLK = VIH or VIL
⎯
0.5
Power down mode
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
0.1
IDD2N
CKE = VIH
All banks idle, tCK = 20 ns
NOP commands only,
Input signals (except for CMD) are changed
1 time during 2 clocks.
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
8
mA
IDD2NS
CKE = VIH
All banks idle
CLK = VIH or VIL
Input signal are stable.
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
1
mA
-12L
-12
IDD2PS
-12L
Precharge
Standby Current
(Power Supply
Current)
mA
(Continued)
26
MB81ES653225-12/-12L
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
-12
IDD3P
-12L
-12
IDD3PS
Refresh Current#1
(Average Power
Supply Current)
CKE = VIL
Any bank active
tCK = Min
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
Value
Min
Max
⎯
1
Unit
mA
⎯
0.7
⎯
0.7
mA
⎯
0.5
IDD3N
CKE = VIH
Any bank active
tCK = 20 ns
NOP commands only,
Input signals (except for CMD) are changed
1 time during 2 clocks.
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
14
mA
IDD3NS
CKE = VIH
Any bank active
CLK = VIH or VIL
Input signals are stable.
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
1
mA
IDD4
tCK = Min
Burst Length = 4
Output pin open
All-banks active
Gapless data
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
68
mA
IDD5
Auto-refresh;
tCK = Min
tRC = Min
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
⎯
50
mA
-12L
Active Standby
Current
(Power Supply
Current)
Burst mode Current
(Average Power
Supply Current)
Condition
(Continued)
27
MB81ES653225-12/-12L
(Continued)
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
Min
Max
PASR = “000”
(64 Mbit)
⎯
760
⎯
285
TCSR = “00” PASR = “001”
(Ta ≤ +70 °C) (32 Mbit)
⎯
640
⎯
200
PASR = “010”
(16 Mbit)
⎯
580
⎯
155
PASR = “000”
(64 Mbit)
⎯
640
⎯
200
TCSR = “01” PASR = “001”
(Ta ≤ +45 °C) (32 Mbit)
⎯
580
⎯
150
PASR = “010”
(16 Mbit)
⎯
550
⎯
130
PASR = “000”
(64 Mbit)
⎯
560
⎯
130
TCSR = “10” PASR = “001”
(Ta ≤ +15 °C) (32 Mbit)
⎯
540
⎯
115
PASR = “010”
(16 Mbit)
⎯
530
⎯
105
PASR = “000”
(64 Mbit)
⎯
1000
⎯
450
TCSR = “11” PASR = “001”
(Ta ≤ +85 °C) (32 Mbit)
⎯
760
⎯
290
PASR = “010”
(16 Mbit)
⎯
640
⎯
205
⎯
50
-12
-12L
-12
-12L
-12
-12L
-12
-12L
-12
-12L
Refresh Current
#2 *4
(Average Power
Supply Current)
-12
-12L
-12
IDD6
-12L
Self-refresh;
tCK = Min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤
VDDQ
-12
-12L
-12
-12L
-12
-12L
-12
-12L
-12
-12L
Precharge Standby
Current in Deep
Power Down
mode
-12
IDD7
-12L
Value
Condition
CKE ≤ 0.2 V
All banks idle
Deep Power Down mode
0 V ≤ VIN ≤ VIL Max
VIH Min ≤ VIN ≤ VDD
Unit
µA
µA
⎯
10
*1 : All voltages are referenced to VSS.
*2 : DC characteristics are measured after following the “22. POWER-UP INITIALIZATION” procedure in section
“■FUNCTIONAL DESCRIPTION.”
*3 : IDD depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination resistor.
*4 : The measurement conditions of IDD6 is assumed below.
Total power of devices in package (Σ pmax) = 0.75 W
The thermal resistance of the package (θ ja) = 20 °C/W
28
MB81ES653225-12/-12L
■ AC CHARACTERISTICS
1. BASIC AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
Value
Min
Max
Unit
CL = 2
tCK2
18.5
⎯
ns
CL = 3
tCK3
11.7
⎯
ns
Clock High Time *5
tCH
tCK × 0.3
⎯
ns
Clock Low Time *5
tCL
tCK × 0.3
⎯
ns
tSI
2.5
⎯
ns
tHI
1
⎯
ns
CL = 2
tAC2
⎯
12
ns
CL = 3
tAC3
⎯
8.7
ns
tLZ
0
⎯
ns
12
ns
8.7
ns
⎯
ns
Clock Period
Input Setup Time *
Input Hold Time *
5
5
Access Time from Clock
(TCK = Min) *5, *6, *7
Output in Low-Z *
5
CL = 2
Output in High-Z *5, *7, *8
CL = 3
Output Hold Time *4
-12
-12L
-12
-12L
-12
-12L
tHZ2
tHZ3
tOH
2
1.5
2
1.5
2
1.5
Time between Auto-Refresh command interval
tREFI
⎯
3.9
µs
Time between Refresh
tREF
⎯
32
ms
tT
0.5
10
ns
tCKSP
2.5
⎯
ns
Transition Time
CKE Setup Time for Power Down Exit Time *5
*1 : AC characteristics are measured after following the “22. POWER-UP INITIALIZATION” procedure in section
“■FUNCTIONAL DESCRIPTION”.
*2 : AC characteristics assume tT = 1 ns, 10 pF of capacitive load and 50 Ω of terminated load.
Refer to “5. MEASUREMENT CONDITION OF THE AC CHARACTERISTICS”.
*3 : 0.9 V is the reference level for 1.8 V I/O for measuring timing of input/output signals. Transition times are
measured between VIH (Min) and VIL (Max) .
*4 : This value is for reference only.
*5 : If input signal transition time (tT) is longer than 1 ns; [ (tT/2) − 0.5] ns should be added to tAC (Max) , tHZ (Max) ,
and tCKSP (Min) spec values, [ (tT/2) − 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH (Min) spec
values, and (tT − 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values.
*6 : tAC also specifies the access time at burst mode.
*7 : tAC and tOH are measured under output load circuit shown in “5. MEASUREMENT CONDITION OF THE AC
CHARACTERISTICS”.
*8 : Specified where output buffer is no longer driven.
29
MB81ES653225-12/-12L
2. BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter
Value
Symbol
Min
Max
Unit
RAS Cycle Time *
tRC
80
⎯
ns
RAS Precharge Time
tRP
20
⎯
ns
RAS Active Time
tRAS
60
110000
ns
RAS to CAS Delay Time
tRCD
20
⎯
ns
Write Recovery Time
tWR
11.7
⎯
ns
RAS to RAS Bank Active Delay Time
tRRD
20
⎯
ns
Data-in to Precharge Lead Time
tDPL
18.5/20
⎯
ns
⎯
ns
⎯
ns
⎯
ns
CL = 2
Data-in to Active/Refresh Command
Period
CL = 3
-12
-12L
-12
-12L
Mode Register Set Cycle Time
1 cyc + tRP
tDAL2
2 cyc + tRP
2 cyc + tRP
tDAL3
2 cyc + tRP
tRSC
20
* : Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP) .
3. CLOCK COUNT FORMULA
Clock ≥
Base Value
Clock Period
(Round up a whole number)
Note : All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula : clock count equals base value divided
by clock period (round off to a whole number) .
4. LATENCY (The latency values on these parameters are fixed regardless of clock period.)
Parameter
Unit
CKE to Clock Disable
lCKE
1
1
cycle
DQM to Output in High-Z
lDQZ
2
2
cycle
DQM to Input Data Delay
lDQD
0
0
cycle
Last Output to Write Command Delay
lOWD
2
2
cycle
Write Command to Input Data Delay
lDWD
0
0
cycle
CL = 2
lROH2
2
2
cycle
CL = 3
lROH3
3
3
cycle
CL = 2
lBSH2
2
2
cycle
CL = 3
lBSH3
3
3
cycle
CAS to CAS Delay (Min)
lCCD
1
1
cycle
CAS Bank Delay (Min)
lCBD
1
1
cycle
Precharge to Output in High-Z Delay
Burst Stop Command to Output
in High-Z Delay
30
Symbol MB81ES653225-12 MB81ES653225-12L
MB81ES653225-12/-12L
5. MEASUREMENT CONDITION OF AC CHARACTERISTICS
R1 = 50 Ω
0.9 V
Output
CL = 10 pF
6. SETUP, HOLD AND DELAY TIME
tCK
tCH
1.44 V
CLK
tCL
0.9 V
0.36 V
tSI
tHI
1.44 V
Iutput
(Control,
Addr. & Data)
0.9 V
0.36 V
tHZ
tAC
tLZ
Output
tOH
0.9 V
Note : Reference level of input signal is 0.9 V for LVCMOS.
Access time is measured at 0.9 V for LVCMOS.
AC characteristics are also measured in this condition.
31
MB81ES653225-12/-12L
7. DELAY TIME FOR POWER DOWN EXIT
CLK
H or L
tCKSP (Min)
1 clock (Min)
CKE
Command
H or L
NOP
NOP
ACTV
8. PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
Input
(Control)
tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND
COMMAND
Note : These parameters are a limit value of the rising edge of the clock from one command input to next input.
tCKSP is the latency value from the rising edge of CKE.
Measurement reference voltage is 0.9 V.
32
MB81ES653225-12/-12L
9. ACCESS TIME
CLK
Command
READ
tAC
tAC
tAC
(CAS Latency − 1) × tCK
DQ31 to DQ0
(Output)
Q (Valid)
Q (Valid)
Q (Valid)
33
MB81ES653225-12/-12L
■ TIMING DIAGRAMS
1.
CLOCK ENABLE-READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
ICKE
∗1
(1 clock)
lCKE
∗1
(1 clock)
CLK
(Internal)
DQ31 to DQ0
(Read)
Q1
DQ31 to DQ0
(Write)
D1
Q2
(NO CHANGE)
NOT ∗3
WRITTEN
∗2
D2
Q3
∗2
(NO CHANGE)
NOT ∗3
WRITTEN
Q4
D3
D4
*1 : The latency of CKE (lCKE) is one clock.
*2 : During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command.
Output data remain the same data.
*3 : During the write mode, data at the next clock of CSUS command is ignored.
2. POWER DOWN ENTRY AND EXIT
CLK
tCKSP (Min)
1clock (Min)
CKE
Command
∗1
NOP
PD (NOP)∗2
H or L
PDX
NOP
∗3
ACTV
∗4
tREF (Max)
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2 : Precharge command can be posted in conjunction with CKE after the last read data have been appeared
on DQ.
*3 : It is recommended to apply NOP command in conjunction with CKE.
*4 : The ACTV command can be latched after tCKSP (Min) + 1 clock (Min) .
34
MB81ES653225-12/-12L
3.
COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
ICCD
(1 clock)
tRCD (Min)
ICCD
ICCD
ICCD
CAS
Address
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Note : CAS to CAS delay (lCCD) can be one or more clock period.
4. DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (Min)
RAS
ICBD
(1 clock)
tRCD (Min)
ICBD
(1 clock)
CAS
tRCD(Min)
Address
BA
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : CAS Bank delay (lCBD) can be one or more clock period.
35
MB81ES653225-12/-12L
5.
INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM3 to DQM0
(@ Read)
IDQZ (2 clocks)
DQ31 to DQ0
(@ Read)
Q1
Hi-Z
Q2
Q4
End of burst
DQM3 to DQM0
(@ Write)
IDQD (same clock)
DQ31 to DQ0
(@ Write)
D1
MASKED
D3
D4
6. PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (Min)
Command
ACTV
* : PRE means ’PRE’ or ’PALL’.
36
PRE∗
End of burst
MB81ES653225-12/-12L
7. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
PRE∗2
IROH (2 clocks) *1
DQ31 to DQ0
Command
Hi-Z
Q1
PRE∗2
IROH (2 clocks) *1
DQ31 to DQ0
Hi-Z
Q1
Q2
PRE∗2
Command
IROH (2 clocks) *1
DQ31 to DQ0
Hi-Z
Q1
Q2
Q3
PRE∗2
Command
No effect (end of burst)
DQ31 to DQ0
Q1
Q2
Q3
Q4
Hi-Z
*1 : In case of CL = 2, the lROH2 is 2 clocks.
*2 : PRE means ’PRE’ or ’PALL’.
37
MB81ES653225-12/-12L
8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 2, BL = Full Column)
CLK
Command
BST
IBSH (2 clocks)
DQ31 to DQ0
Qn − 2
Qn − 1
Qn + 1
Qn
9. WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
DQ31 to DQ0
38
BST
LAST
DATA-IN
Masked
by BST
COMMAND
Hi-Z
MB81ES653225-12/-12L
10. WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2)
CLK
Command
tDPL (Min)
DQ31 to DQ0
ACTV
PRE
DATA-IN
LAST
DATA-IN
tRP (Min)
MASKED
by Precharge
Note : The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRE means ’PRE’ or ’PALL’.
11. READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
IOWD (2 clocks)
Command
DQM3 to DQM0
READ
WRIT
∗1
∗2
∗3
IDQZ (2 clocks)
IDWD (same clock)
DQ31 to DQ0
Q1
Masked
D1
D2
*1 : First DQM makes high-impedance state High-Z between last output and first input data.
*2 : Second DQM makes internal output data mask to avoid bus contention.
*3 : Third DQM also makes internal output data mask. If burst read ends (final data output) at or after the second
clock of burst write, this third DQM is required to avoid internal bus contention.
39
MB81ES653225-12/-12L
12. WRITE TO READ TIMING (EXAMPLE @ CL = 2, BL = 4)
CLK
tWR (Min)
WRIT
Command
READ
DQM3 to DQM0
(CL − 1) × tCK
DQ31 to DQ0
D1
D2
tAC (Max)
D3
Masked
by READ
Q1
Q2
Q3
Note : Read command should be issued after tWR of final data input is satisfied.
13. READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 2, BL = 2, Applied to same bank)
tRAS (Min)
CLK
tRP (Min)
Command
ACTV
READA∗2
NOP
ACTV
2 clocks *1
(same value as BL)
DQM3 to DQM0
DQ31 to DQ0
Q1
Q2
*1 : Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the
same as Burst Length (BL) after the READA command is asserted.
*2 : Next ACTV command should be issued after BL + tRP (min) from READA command.
40
MB81ES653225-12/-12L
14. WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 2, Applied to same bank) *1, *2, *3
tRAS (Min)
CLK
1 clock *4
tDAL (Min)
BL + tRP (Min) *5
Command
ACTV
WRITA
ACTV
NOP
DQM3 to DQM0
DQ31 to DQ0
D1
D2
*1 : Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2 : Once auto precharge command is asserted, no new command within the same bank can be issued.
*3 : Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4 : Precharge at write with Auto-precharge is started after 1 clock at CL = 2 (-12) , 2 clock at CL = 2 (-12L) and
CL = 3 from the end of burst.
*5 : Next command should be issued after BL + tRP (min) at CL = 2 (-12) , BL + 1 + tRP (min) at CL = 2 (-12L) and
CL = 3 from WRITA command.
15. AUTO-REFRESH TIMING
CLK
Command
REF ∗1
NOP ∗3
REF
tRC (Min)
BA
H or L ∗2
NOP ∗3
COMMAND ∗4
tRC (Min)
H or L ∗2
BA
*1 : All banks should be precharged prior to the first Auto-refresh command (REF) .
*2 : Bank select is ignored at REF command. The refresh address and bank select are selected by internal
refresh counter.
*3 : Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4 : Any activation command such as ACTV or MRS command other than REF command should be asserted
after tRC from the last REF command.
41
MB81ES653225-12/-12L
16. SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tCKSP (Min)
tSI (Min)
CKE
∗5
tRC (Min) *4
Command
H or L
NOP ∗1
SELF
H or L
NOP ∗2
SELFX
NOP ∗3
COMMAND
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry
command (SELF) .
*2 : The Self-refresh Exit command (SELFX) is latched after tCKSP (Min) . It is recommended to apply NOP
command in conjunction with CKE.
*3 : Either NOP or DESL command can be used during tRC period.
*4 : CKE should be held high within one tRC period after tCKSP.
*5 : CKE level should be held less than 0.2 V during self-refresh mode.
17. MODE REGISTER SET TIMING
CLK
tRSC (Min)
Command
Address
MRS
MODE
NOP
ACTV
ROW
ADDRESS
Note : The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
42
MB81ES653225-12/-12L
18. DEEP POWER DOWN ENTRY TIMING
CLK
tSI (Min)
CKE
Command
H or L
NOP
DPD
H or L
Note : Deep Power Down Command (DPD) should only be asserted if all banks have been precharged and all
outputs are in High-Z.
19. DEEP POWER DOWN EXIT TIMING
CLK
tCKSP
(Min)
CKE
200 µs (Min)
Command
H or L
NOP DPDX
NOP
tRP
(Min)
PALL REF
tRC (Min)
tRC (Min)
REF
tRSC tRSC
(Min) (Min)
MRS EMRS ACVT
43
MB81ES653225-12/-12L
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