OKI MSM63P180

E2E0043-38-95
¡ Semiconductor
MSM63P180
¡ Semiconductor
This version:MSM63P180
Sep. 1998
Previous version: Mar. 1996
4-Bit Microcontroller with Built-in 16K Word PROM and 1024-Dot Matrix LCD Drivers
GENERAL DESCRIPTION
The MSM63P180 is an M6318x series one-time-programmable ROM version product of OLMS63K family, which employs Oki's original CPU core nX-4/250.
The MSM63P180 has one-time PROM as internal program memory.
The MSM63188 and other mask ROM-version products have mask ROM as internal program
memory.
The specifications of the MSM63P180 are equal to those of the MSM63188 except for electrical
characteristics, packaging, and some functions.
The MSM63P180 is used for evaluating the software development of M6318x series products.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
16K words (PROM)
Basic instruction length is 16 bits/1 word
• Data memory space
3584 nibbles
• External data memory space
64 Kbytes (expandable by using an I/O port)
1/35
¡ Semiconductor
• Stack level
Call stack level
Register stack level
MSM63P180
: 16 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port
: 2 ports ¥ 4 bits
Output port
: 6 ports ¥ 4 bits
Input-output port
: 8 ports ¥ 4 bits
• Buzzer function
Buzzer output
Buzzer output modes
• Melody output function
Melody sound frequency
Tone length
Tempo
Note data
: 0.946 to 5.461 kHz (adjustable in 15 steps)
: Intermittent sound 1, 2; simple sound; continuous sound
:
:
:
:
529 to 2979 Hz
63 types
15 types
Resides in the program memory
• LCD driver
Number of segments
: 1024 Max. (64 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Multiplier/divider circuits
Multiplier : (8 bits) ¥ (8 bits) Æ Product (16 bits)
Divider
: (16 bits) ÷ (8 bits) Æ Quotient (16 bits), Remainder (8 bits)
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Selectable as 2.2 V or 2.8 V
2/35
¡ Semiconductor
MSM63P180
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 1.45 V minimum
• Timers and counter
8-bit timer ¥ 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Time base capture function
Captures the time base counter output values (32, 64, 128, and 256 Hz) upon the rise (fall) of
P1.0 and P1.1
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
• Shift register
Shift clock
Data length
• Interrupt sources
External interrupt
Internal interrupt
• Operating voltage
When backup used
When backup not used
: UART mode, synchronous mode
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
: 32.768 kHz (internal clock mode), external
clock frequency
: 5 to 8 bits
: 1x or 1/2x system clock, timer 1 overflow,
external clock
: 8 bits
: 6
: 14 (watchdog timer interrupt is a nonmaskable interrupt)
: VDD = 1.45 to 2.7 V
: VDD = 2.7 to 5.5 V
• Package:
176-pin plastic LQFP (LQFP176-P-2424-0.50-BK)
Product name : MSM63P180-xxxGS-BK (written PROM)
MSM63P180-NGS-BK (blanked PROM)
xxx indicates a code number.
3/35
¡ Semiconductor
MSM63P180
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
C
SP
G
ALU
RSP
MIE
STACK
INSTRUCTION
CAL: 16-level
DECODER
PC
Z
PROM
16KW
BUS
VPP
VDDH
D0-7*
EXTMEM
CON-
A0-15*
TROL
RD*
WR*
IR
REG: 16-level
INT
4
RAM
3584N
TIMER
8bit ¥ 4
INT
2
INT0*
INT1*
INT2*
INT3*
INT4*
INT
SIO
(sync/async)
RXC*
TXC*
RXD*
TXD*
SFT
SIN*
SOUT*
SCLK*
INT
1
RST
MULDIV
INT
TST1
TST2
1
TST
TBC
DATA BUS
RESET
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
INT
1
MD
MELODY
MDB
BD
BUZZER
XT0
XT1
OSC0
OSC1
TBCAP0*
TBCAP1*
TBCAPR
OSC
INT5
1
INPUT
PORT
BLD
TBCCLK*
HSCLK*
BDB
P0.0-P0.3
P1.0-P1.3
INT
1
P2.0-P2.3
100HzTC
P3.0-P3.3
INT
1
OUTPUT
PORT
WDT
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
VDDH
P7.0-P7.3
VDD
P8.0-P8.3
BACKUP
CB1
P9.0-P9.3
CB2
PA.0-PA.3
I/O
PORT
PC.0-PC.3
VDD1
PD.0-PD.3
VDD2
INT0-4
VDD3
VDD4
PE.0-PE.3
5
PF.0-PF.3
BIAS
VDD5
C1
C2
PB.0-PB.3
LCLK*
FRAME*
LCD
&
DSPR
COM1-16
SEG0-63
VDDI
VSS
4/35
,
¡ Semiconductor
MSM63P180
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P5.0
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
P8.0
P8.1
P8.2
P8.3
P9.0
P9.1
P9.2
P9.3
PA.0
PA.1
PA.2
PA.3
PB.0
PB.1
PB.2
PB.3
PC.0
PC.1
PC.2
PC.3
PD.0
PD.1
PD.2
PD.3
PE.0
PE.1
PE.2
PE.3
PF.0
PF.1
PF.2
PF.3
(NC)
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
VDD
(NC)
OSC1
OSC0
RESET
XT1
XT0
TST2
TST1
BD
BDB
MD
MDB
VPP
VDDI
(NC)
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
(NC)
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
(NC)
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
(NC)
(NC)
PIN CONFIGURATION (TOP VIEW)
176-Pin Plastic LQFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/35
¡ Semiconductor
MSM63P180
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63P180 are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Power
Supply
Pin
Type
Description
VPP
86
—
Power supply (+12.5 V) for PROM writing
VDD
73
—
Positive power supply
—
Negative power supply
VSS
62
VDD1
63
VDD2
64
VDD3
65
Power supply pins for LCD bias (internally generated).
Capacitors (0.1 mF) should be connected between these pins and
—
VDD4
66
VDD5
67
C1
68
C2
69
VDDI
87
—
VDDH
70
—
CB1
71
—
CB2
72
—
—
VSS.
Capacitor connection pins for LCD bias generation.
A capacitor (0.1 mF) should be connected between C1 and C2.
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Voltage multiplier pin for power
To enable high-speed oscillation, apply
supply backup (internally generated). 2.7 V to VDDH with CB1 and CB2 left open
Pins to connect a capacitor for
(backup OFF).
voltage multiplier.
To disable high-speed oscillation, connect
A capacitor (0.1 mF) should be
a 1 mF capacitor between VDDH and VSS
connected between CB1 and CB2.
and between CB1 and CB2.
Low-speed clock oscillation pins.
XT0
79
I
XT1
78
O
and CG (12 to 30 pF) should be connected between XT0 and VSS.
OSC0
76
I
High-speed clock oscillation pins.
OSC1
75
O
oscillation resistor (ROS) should be connected to these pins.
TST1
81
I
Input pins for testing.
TST2
80
I
A 32.768 kHz crystal should be connected between XT0 and XT1,
Oscillation
A ceramic resonator and capacitors (CL0, CL1) or external
A pull-down resistor is internally connected to these pins.
Test
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Reset
RESET
77
I
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Buzzer
Melody
BD
82
O
Buzzer output pin (non-inverted output)
BDB
83
O
Buzzer output pin (inverted output)
MD
84
O
Melody output pin (non-inverted output)
MDB
85
O
Melody output pin (inverted output)
6/35
¡ Semiconductor
MSM63P180
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P0.0/INT5
154
P0.1/INT5
153
P0.2/INT5
152
P0.3/INT5
151
P1.0/INT5
150
P1.1/INT5
149
P1.2/INT5
148
P1.3/INT5
147
P2.0
146
P2.1
145
P2.2
144
P2.3
143
P3.0
142
P3.1
141
P3.2
140
P3.3
139
P4.0/A0
138
P4.1/A1
137
P4.2/A2
136
P4.3/A3
135
P5.0/A4
132
P5.1/A5
131
P5.2/A6
130
P5.3/A7
129
P6.0/A8
128
P6.1/A9
127
P6.2/A10
126
P6.3/A11
125
P7.0/A12
124
P7.1/A13
123
P7.2/A14
122
P7.3/A15
121
Type
Description
4-bit input ports.
I
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
4-bit output ports.
O
P-channel open drain output, N-channel open drain output,
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
O
O
7/35
¡ Semiconductor
MSM63P180
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P8.0/RD
120
P8.1/WR
119
P8.2
118
P8.3/INT4
117
In output mode, P-channel open drain output, N-channel open
P9.0/D0
116
drain output, CMOS output, or high-impedance output is
P9.1/D1
115
P9.2/D2
114
P9.3/D3
113
PA.0/D4
112
PA.1/D5
111
PA.2/D6
110
PA.3/D7
109
PB.0/INT0/
TM0CAP/
TM0OVF
PB.1/INT0/
TM1CAP/
TM1OVF
PB.2/INT0/T02CK
Type
Description
4-bit input-output ports.
I/O
In input mode, pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for each bit.
selectable for each bit.
I/O
I/O
108
107
I/O
106
PB.3/INT0/T13CK
105
PC.0/INT1/RXD
104
PC.1/INT1/TXC
103
PC.2/INT1/RXC
102
PC.3/INT1/TXD
101
PD.0/FRAME
100
PD.1/LCLK
99
PD.2/TBCCLK
98
PD.3/HSCLK
97
PE.0/SIN
96
PE.1/SOUT
95
PE.2/SCLK
94
PE.3/INT2
93
PF.0/INT3
92
PF.1/INT3
91
PF.2/INT3
90
PF.3/INT3
89
I/O
I/O
I/O
I/O
8/35
¡ Semiconductor
MSM63P180
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
COM1
61
COM2
60
COM3
59
COM4
58
COM5
57
COM6
56
COM7
55
COM8
54
COM9
53
COM10
52
COM11
51
COM12
50
COM13
49
COM14
48
COM15
47
COM16
46
SEG0
44
SEG1
43
SEG2
42
SEG3
41
SEG4
40
SEG5
39
SEG6
38
SEG7
37
SEG8
36
SEG9
35
SEG10
34
SEG11
33
SEG12
32
SEG13
31
SEG14
30
SEG15
29
SEG16
28
SEG17
27
SEG18
26
SEG19
25
SEG20
24
SEG21
23
SEG22
22
SEG23
21
SEG24
20
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
O
9/35
¡ Semiconductor
MSM63P180
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
SEG25
19
SEG26
18
SEG27
17
SEG28
16
SEG29
15
SEG30
14
SEG31
13
SEG32
12
SEG33
11
SEG34
10
SEG35
9
SEG36
8
SEG37
7
SEG38
6
SEG39
5
SEG40
4
SEG41
3
SEG42
2
SEG43
1
SEG44
175
SEG45
174
SEG46
173
SEG47
172
SEG48
171
SEG49
170
SEG50
169
SEG51
168
SEG52
167
SEG53
166
SEG54
165
SEG55
164
SEG56
163
SEG57
162
SEG58
161
SEG59
160
SEG60
159
SEG61
158
SEG62
157
SEG63
156
Type
Description
LCD segment signal output pins
O
10/35
¡ Semiconductor
MSM63P180
Table 2 shows the secondary functions of each pin of the MSM63P180.
Table 2 Pin Descriptions (Secondary Functions)
Symbol
Pin
PB.0/INT0
108
PB.1/INT0
107
PB.2/INT0
106
PB.3/INT0
105
an interrupt for each bit.
PC.0/INT1
104
External 1 interrupt input pins.
PC.1/INT1
103
PC.2/INT1
102
PC.3/INT1
101
PE.3/INT2
93
External
PF.0/INT3
92
Interrupt
PF.1/INT3
91
PF.2/INT3
90
PF.3/INT3
89
P8.3/INT4
117
P0.0/INT5
154
External 5 interrupt input pins.
P0.1/INT5
153
The change of input signal level causes an interrupt to occur.
P0.2/INT5
152
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
P0.3/INT5
151
P1.0/INT5
150
P1.1/INT5
149
P1.2/INT5
148
P1.3/INT5
147
P1.0/TBCAP0
150
P1.1/TBCAP1
149
PB.0/TM0CAP
PB.1/TM1CAP
Function
Capture
Type
Description
External 0 interrupt input pins.
I
I
The change of input signal level causes an interrupt to occur.
The Port B Interrupt Enable register (PBIE) enables or disables
The change of input signal level causes an interrupt to occur.
The Port C Interrupt Enable register (PCIE) enables or disables
an interrupt for each bit.
I
External 2 interrupt input pin.
The change of input signal level causes an interrupt to occur.
External 3 interrupt input pins.
I
The change of input signal level causes an interrupt to occur.
The Port F Interrupt Enable register (PFIE) enables or disables
an interrupt for each bit.
I
I
External 4 interrupt input pin.
The change of input signal level causes an interrupt to occur.
Enable register (P1IE) enable or disable an interrupt for each bit.
I
Time base counter capture trigger input pins
108
I
Timer 0 capture trigger input pin
107
I
Timer 1 capture trigger input pin
11/35
¡ Semiconductor
MSM63P180
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Timer
Symbol
Pin
Type
Description
PB.0/TM0OVF
108
O
Timer 0 overflow flag output pin.
PB.1/TM1OVF
107
O
Timer 1 overflow flag output pin.
PB.2/T02CK
106
I
External clock input pin for timer 0 and timer 2.
PB.3/T13CK
105
I
External clock input pin for timer 1 and timer 3.
PD.0/FRAME
100
O
Frame output pin for LCD driver expansion
Expansion
PD.1/LCLK
99
O
Clock output pin for LCD driver expansion
Oscillation
PD.2/TBCCLK
98
O
Low-speed oscillation clock output pin
Output
PD.3/HSCLK
97
O
High-speed oscillation clock output pin
PC.0/RXD
104
I
Serial port receive data input pin
LCD
External
Sync serial port clock input-output pin.
PC.1/TXC
103
I/O
Serial
Transmit clock output when this device is used as a master processor.
Transmit clock input when this device is used as a slave processor.
Port
Sync serial port clock input-output pin.
PC.2/RXC
102
I/O
PC.3/TXD
101
O
Serial port transmit data output pin.
PE.0/SIN
96
I
Shift register receive data input pin
PE.1/SOUT
95
O
Shift register transmit data output pin
Receive clock output when this device is used as a master processor.
Receive clock input when this device is used as a slave processor.
Shift
Register
Shift register clock input-output pin.
PE.2/SCLK
94
I/O
Clock output when this device is used as a master processor.
Clock input when this device is used as a slave processor.
12/35
¡ Semiconductor
MSM63P180
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
External
Memory
Symbol
Pin
P4.0/A0
138
P4.1/A1
137
P4.2/A2
136
P4.3/A3
135
P5.0/A4
132
P5.1/A5
131
P5.2/A6
130
P5.3/A7
129
P6.0/A8
128
Type
Description
Address output bus for external memory
O
P6.1/A9
127
P6.2/A10
126
P6.3/A11
125
P7.0/A12
124
P7.1/A13
123
P7.2/A14
122
P7.3/A15
121
P9.0/D0
116
P9.1/D1
115
P9.2/D2
114
P9.3/D3
113
PA.0/D4
112
PA.1/D5
111
PA.2/D6
110
PA.3/D7
109
P8.0/RD
120
O
Read signal output pin for external memory (negative logic)
P8.1/WR
119
O
Write signal output pin for external memory (negative logic)
Data bus for external memory
I/O
13/35
¡ Semiconductor
MSM63P180
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.6
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.9
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +4.2
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +6.8
V
Power Supply Voltage 6
VDD
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 7
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 8
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 9
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 Output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 Output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 Output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 Output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 Output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 7
VOUT7
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 8
VOUT8
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
14/35
¡ Semiconductor
MSM63P180
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Symbol
Condition
Range
Unit
Top
—
0 to +65
°C
VDD
—
1.45 to 2.7
V
VDDI
—
1.5 to 5.5
V
Crystal Oscillation Frequency
fXT
—
30 to 35
kHz
Ceramic Oscillation Frequency
fCM
VDD = 1.45 to 2.7 V (*1)
200k to 1M
Hz
External RC Oscillator Resistance
ROS
VDD = 1.45 to 2.7 V (*1)
50 to 300
kW
*1 A voltage of 2.7 V or more must be applied to VDDH.
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Symbol
Condition
Range
Unit
Top
—
0 to +65
°C
VDD
—
2.7 to 5.5
V
VDDI
—
1.8 to 5.5
V
Crystal Oscillation Frequency
fXT
—
30 to 35
kHz
Ceramic Oscillation Frequency
fCM
VDD = 2.7 to 5.5 V
300k to 1M
VDD = 2.9 to 5.5 V
200k to 2M
External RC Oscillator Resistance
ROS
VDD = 2.7 to 5.5 V
50 to 300
VDD = 2.9 to 5.5 V
30 to 300
Hz
kW
15/35
¡ Semiconductor
MSM63P180
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
VDD2 Voltage
(VDD = VDDI = 1.45 to 5.5 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified)
MeaSymbol
Condition
Min.
Typ.
Max. Unit suring
Circuit
1/5 bias, 1/4 bias
V
VDD2
1.7
1.8
1.9
(Ta = 25°C)
DVDD2
—
VDD1 Voltage
VDD1
1/5 bias, 1/4 bias
Typ.– 0.2 1/2 ¥ VDD2 Typ.+ 0.2
1/5 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.2
VDD3 Voltage
VDD3
1/4 bias (connect
VDD2 Voltage Temperature Deviation
VDD3 and VDD2)
VDD4 Voltage
VDD4
VDD5 Voltage
VDD5
VDD2
—
Typ.+ 0.2
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.2
1/4 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.2
1/5 bias
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.2
1/4 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.2
Crystal Oscillation Start Voltage
VSTA
(backup used)
VDDH
Typ.– 0.2
–4
1/5 bias
High-speed clock oscillation
stopped
VDD = 1.5 V
Oscillation start time:
within 5 seconds
VDDH Voltage
—
2.8
—
3.0
mV/°C
V
V
V
V
V
1
1.40
—
—
V
Crystal Oscillation Hold Voltage
VHOLD
—
1.35
—
—
V
Crystal Oscillation Stop Detect Time
TSTOP
—
0.1
—
5.0
ms
External Crystal Oscillator Capacitance
CG
—
12
—
30
pF
Internal Crystal Oscillator Capacitance
CD
—
12
15
20
pF
—
30
—
pF
8
12
16
pF
0.0
—
0.4
V
External Ceramic Oscillator
Capacitance
Internal RC Oscillator Capacitance
POR Voltage
Non-POR Voltage
CL0, 1
COS
VPOR1
VPOR2
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
—
VDD = 1.5 V
—
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
—
2.0
—
3.0
V
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
16/35
¡ Semiconductor
MSM63P180
DC Characteristics
• When backup is used
Parameter
Supply Current 1
(VDD = VDDI = 1.5 V, VDDH = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified)
MeaSymbol
Condition
Min.
Typ.
Max. Unit suring
Circuit
CPU is in HALT state.
mA
IDD1 (High-speed clock oscillation —
10
20
stopped)
IDD2
CPU is in HALT state.
LCD is in Power Down mode.
(High-speed clock oscillation
stopped)
—
Supply Current 3
IDD3
CPU is in operating state.
(High-speed clock oscillation
stopped)
—
100
140
mA
Supply Current 4
IDD4
CPU is in operation at
high-speed oscillation
(RC oscillation, ROS = 51 kW)
—
1.5
2
mA
Supply Current 5
IDD5
CPU is in operation at
high-speed oscillation
(Ceramic oscillation, 1 MHz)
—
2
3
mA
Supply Current 2
8
16
mA
1
• When backup is not used
Parameter
Supply Current 1
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified)
MeaSymbol
Condition
Min.
Typ.
Max. Unit suring
Circuit
CPU is in HALT state.
5
10
mA
IDD1 (High-speed clock oscillation —
stopped)
Supply Current 2
IDD2
CPU is in HALT state.
LCD is in Power Down mode.
(High-speed clock oscillation
stopped)
Supply Current 3
IDD3
CPU is in operating state.
(High-speed clock oscillation
stopped)
—
60
120
mA
Supply Current 4
IDD4
CPU is in operation at
high-speed oscillation
(RC oscillation, ROS = 51 kW)
—
1.5
2
mA
Supply Current 5
IDD5
CPU is in operation at
high-speed oscillation
(Ceramic oscillation, 2 MHz)
—
3.5
5
mA
—
4
7
mA
1
17/35
¡ Semiconductor
MSM63P180
DC Characteristics (continued)
Parameter
Output Current 1
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
Symbol
IOH1
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = 0 to +65°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
–2.1
–1.0
–0.2
mA
–5.0
–2.5
–1.0
mA
VDDI = 5.0 V
–8.0
–4.0
–2.0
mA
VDDI = 1.5 V
0.2
1.0
2.1
mA
VDDI = 3.0 V
1.0
2.5
5.0
mA
···
VDDI = 1.5 V
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
(PF.0 to PF.3)
Output Current 2
(BD, BDB)
(MD, MDB)
Output Current 3
(SEG0 to SEG63)
(COM1 to COM16)
IOL1
IOH2
2.0
4.0
8.0
mA
VDD = 1.5 V
–1.8
–1.0
–0.2
mA
VDD = 3.0 V
–5.0
–3.0
–1.0
mA
VDD = VDDH = 5.0 V
–9.0
–5.5
–4.0
mA
VDD = 1.5 V
0.2
1.0
1.8
mA
VDD = 3.0 V
1.0
3.0
5.0
mA
VDD = VDDH = 5.0 V
4.0
5.5
9.0
mA
—
—
–4
mA
VOL2 = 0.7 V
IOH3
VOH3 = VDD5 – 0.2 V (VDD5 level)
IOHM3
VOHM3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
mA
IOHM3S
VOHM3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
mA
IOMH3
VOMH3 = VDD3 + 0.2 V (VDD3 level)
4
—
—
mA
IOMH3S
VOMH3S = VDD3 – 0.2 V (VDD3 level)
—
—
–4
mA
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
mA
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
mA
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
mA
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
mA
VOL3 = VSS + 0.2 V (VSS level)
4
—
—
mA
IOL3
IOH4R
IOL4R
IOH4C
IOL4C
Output Leakage
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
VOH2 = VDD – 0.7 V
VDDI = 5.0 V
IOL2
IOLM3S
Output Current 4
(OSC1)
VOL1 = 0.5 V
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
–2.0
–1.2
–0.6
mA
(RC oscillation)
–3.5
–2.0
–1.0
mA
VDD = VDDH = 5.0 V
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.6
1.2
2.0
mA
(RC oscillation)
VDD = VDDH = 5.0 V
1.0
2.0
3.5
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–200
–100
–50
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
–400
–200
–100
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
50
100
200
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
100
200
400
mA
···
IOOH
VOH = VDDI
—
—
0.3
mA
IOOL
VOL = VSS
–0.3
—
—
mA
2
(PF.0 to PF.3)
18/35
¡ Semiconductor
MSM63P180
DC Characteristics (continued)
Parameter
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
Symbol
IIH1
···
IIL1
(PF.0 to PF.3)
Input Current 2
(OSC0)
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
VDDI = 1.5 V
2
10
30
mA
VDDI = 3.0 V
30
90
180
mA
VDDI = 5.0 V
100
250
500
mA
VDDI = 1.5 V
–30
–10
–2
mA
VDDI = 3.0 V
–180
–90
–30
mA
VDDI = 5.0 V
–500
–250
–100
mA
0.0
—
1.0
mA
IIH1Z
VIH1 = VDDI (in a high impedance state)
IIL1Z
VIL1 = VSS (in a high impedance state)
–1.0
—
0.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–200
–110
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
IIL2
–600
–350
–150
mA
IIH2R
VIH2 = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL2R
VIL2 = VSS (RC oscillation)
–1.0
—
0.0
mA
VDD = VDDH = 3.0 V
0.1
0.5
1.0
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
0.75
1.5
3.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–1.0
–0.5
–0.1
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–3.0
–1.5
–0.75
mA
IIH2C
IIL2C
Input Current 3
(RESET)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = 0 to +65°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
VIH2 = VDDH
IIH3
VIH3 = VDD
IIL3
VIL3 = VSS
IIH4
VIH4 = VDD
IIL4
VIL4 = VSS
VDD = 1.5 V
10
40
80
mA
VDD = 3.0 V
150
350
600
mA
0.5
1.0
2.0
mA
–1.0
—
0.0
mA
VDD = VDDH = 5.0 V
Input Current 4
(TST1, TST2)
VDD = 1.5 V
30
120
300
mA
VDD = 3.0 V
0.3
0.75
1.5
mA
VDD = VDDH = 5.0 V
1.25
2.5
4.0
mA
–1.0
—
0.0
mA
3
19/35
¡ Semiconductor
MSM63P180
DC Characteristics (continued)
Parameter
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = 0 to +65°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
VIH1
···
VIL1
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
VDDI = 3.0 V
0.0
—
0.6
V
(PF.0 to PF.3)
VDDI = 5.0 V
0.0
—
1.0
V
Input Voltage 2
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
(OSC0)
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VIH3
VDD = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
(PF.0 to PF.3)
VDDI = 5.0 V
0.25
1.0
1.5
V
Hysteresis Width 2
VDD = 1.5 V
0.05
0.1
0.3
V
VIL3
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
DVT1
4
···
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
DVT2
CIN
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = VDDH = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
1
···
(PF.0 to PF.3)
20/35
¡ Semiconductor
MSM63P180
Measuring circuit 1
(Open) CB1
CG
XT0
(Open) CB2
C1
C12
XT1
C2
q
OSC0
w
OSC1
32.768 kHz
Crystal
*1
VSS
VDD
VDDI VDD1
Ca
A
Ca, Cb, Cc, Cd, Ce, C12
CG
CL0
CL1
Ceramic Resonator
VDD2
Cb
V
: 0.1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
VDD3
VDD4 VDD5 VDDH
Cc
V
Cd
V
Ce
V
V
*1 RC Oscillator
q
ROS
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
*2
VIL
INPUT
VSS
OUTPUT
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
A
VDDH
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
21/35
¡ Semiconductor
MSM63P180
Measuring circuit 3
*4
A
INPUT
VSS
OUTPUT
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
VDDH
Measuring circuit 4
VIH
Waveform
Monitoring
*4
VIL
INPUT
VSS
OUTPUT
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
VDDH
*4 Measured at the specified input pins.
22/35
¡ Semiconductor
MSM63P180
AC Characteristics (Serial Interface, Serial Port)
(VDD = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = 0 to +65°C unless otherwise
specified)
(1) Synchronous Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
tf
—
—
—
1.0
ms
TXC/RXC Input Rise Time
tr
—
—
—
1.0
ms
TXC/RXC Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
TXC/RXC Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
TXC/RXC Input Cycle Time
tCYC
—
2.0
—
—
ms
tCYC1(O)
CPU in operation state at 32 kHz
—
30.5
—
ms
—
0.5
—
ms
TXC/RXC Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 2.9 V to 5.5 V
TXD Output Delay Time
tDDR
Output load capacitance 10 pF
—
—
0.4
ms
RXD Input Setup Time
tDS
—
0.5
—
—
ms
RXD Input Hold Time
tDH
—
0.8
—
—
ms
Synchronous communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
TXC (PC.1)/
RXC (PC.2)
5 V (VDDI)
tr
0 V (VSS)
tf
tCWH
tCWL
tDDR
tDDR
TXD (PC.3)
5 V (VDDI)
0 V (VSS)
tDS
RXD (PC.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
23/35
¡ Semiconductor
MSM63P180
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transmit Baud Rate
TBRT
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT–TCR
TBRT
TBRT+TCR
s
Receive Baud Rate
RBRT
RBRT = 1/fBRT
RBRT¥0.97
RBRT
RBRT¥1.03
s
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
TBRT
5 V (VDDI)
TXD (PC.3)
0 V (VSS)
RBRT
RXD (PC.0)
5 V (VDDI)
0 V (VSS)
24/35
¡ Semiconductor
MSM63P180
AC Characteristics (Serial Interface, Shift Register)
(VDD = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = 0 to +65°C unless otherwise
specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SCLK Input Fall Time
tf
—
—
—
1.0
ms
SCLK Input Rise Time
tr
—
—
—
1.0
ms
SCLK Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
SCLK Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
tCYC
—
2.0
—
—
ms
tCYC1(O)
CPU in operation state at 32 kHz
—
30.5
—
ms
—
0.5
—
ms
SCLK Input Cycle Time
SCLK Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 2.9 V to 5.5 V
SOUT Output Delay Time
tDDR
Cl = 10 pF
—
—
0.4
ms
SIN Input Setup Time
tDS
—
0.5
—
—
ms
SIN Input Hold Time
tDH
—
0.8
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
SCLK (PE.2)
5 V (VDDI)
tr
0 V (VSS)
tf
tCWH
tCWL
tDDR
tDDR
5 V (VDDI)
SOUT (PE.3)
0 V (VSS)
tDS
SIN (PE.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
25/35
¡ Semiconductor
MSM63P180
AC Characteristics (External Memory Interface)
(VDD = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = 0 to +65°C unless otherwise
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Symbol
Condition
Min.
Typ.
Read Cycle Time
Parameter
Max.
Unit
tRC
—
—
RD Output Delay Time
tOE
—
—
61.0
—
ms
—
5.0
ms
Output Valid Time
tOHA
—
External Memory Output Delay Time
tDO
—
—
—
5.0
ms
—
—
5.0
ms
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
RD Output Delay Time
tRC
—
1.0
—
—
ms
tOE
—
—
—
100
ns
Output Valid Time
tOHA
—
—
—
100
ns
External Memory Output Delay Time
tDO
—
—
—
150
ns
(b) When CPU operates at 2 MHz (VDDH = 2.9 to 5.5 V)
Parameter
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 - P4
(A15 - A0)
Port setup value
Address output
Port setup value
5 V (VDDI)
0 V (VSS)
P8.0
(RD)
tOE
PA, P9
(D7 - D0)
5 V (VDDI)
0 V (VSS)
Port setup value
Input data
tOHA
Port setup value
5 V (VDDI)
0 V (VSS)
tDO
26/35
¡ Semiconductor
MSM63P180
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
—
61.0
—
ms
Address Setup Time
tAS
—
—
30.5
—
ms
Write Time
tW
—
—
15.3
—
ms
Write Recovery Time
tWR
—
—
15.3
—
ms
Data Setup Time
tDS
—
—
45.8
—
ms
Data Hold Time
tDH
—
—
15.3
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.9 to 5.5 V)
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
Parameter
tWC
—
1.0
—
—
ms
Address Setup Time
tAS
—
0.4
—
—
ms
Write Time
tW
—
0.2
—
—
ms
Write Recovery Time
tWR
—
0.2
—
—
ms
Data Setup Time
tDS
—
0.7
—
—
ms
Data Hold Time
tDH
—
0.2
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
P7 - P4
(A15 - A0)
PA, P9
(D7 - D0)
Port setup value
Address output
Port setup value
Output data
tDS
tDH
Port setup value
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
P8.1
(WR)
tAS
tW
tWR
27/35
¡ Semiconductor
MSM63P180
(3) PROM Operations (Applies to Both the Cases of Using and Not Using Backup)
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
PROM Power Source Voltage
VCC
Program Voltage
VPP
PROM Input Voltage
VI
PROM Output Voltage
VO
Storage Temperature
TSTG
Condition
VCC = VDD = VDDH = VDDI
Ta = 25°C
Ta = 25°C
VCC input
Ta = 25°C
VCC output
Ta = 25°C
—
Rating
Unit
–0.3 to +6.7
V
–0.3 to +14.0
V
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V)
Parameter
Symbol
Condition
Operating Temperature
VCC Power Supply Voltage
TOPEP
VCC
VPP Power Supply Voltage
VPP
Input Voltage
Range
Unit
—
0 to +65
°C
—
4.75 to 5.25
V
When data is read
4.75 to 5.25
V
VIH
When data is written
—
12.0 to 13.5
4.0 to VCC
V
V
VIL
—
0 to 1.0
V
28/35
¡ Semiconductor
MSM63P180
ELECTRICAL CHARACTERISTICS
(1) Read Operation
DC Characteristics
Parameter
VCC Power Supply Current
(Standby)
VCC Power Supply Current
(Operating)
Input Voltage
Output Current
Symbol
(VCC = VPP = 5 V ±5%, Ta = 25°C ±5°C unless otherwise specified)
Min.
Typ.
Max.
Condition
Unit
ICC1
CE = VIH
—
—
35
mA
ICC2
CE = VIL
—
—
100
mA
4.0
—
VCC
V
VIH
—
VIL
—
IOH
IOL
0
—
1.0
V
VOH = VCC – 0.5 V
–8
–4
–2
mA
VOL = 0.5 V
2
4
8
mA
AC Characteristics
(VCC = 5 V ±5%, VPP = VCC, Ta = 0 to +65°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Address Access Time
tACC
OE = CE = VIL
—
—
120
ns
CE Access Time
tCE
OE = VIL
—
—
120
ns
OE Access Time
tOE
CE = VIL
—
—
50
ns
Output Disable Time
tDF
CE = VIL
0
—
40
ns
Measurement conditions:
Input pulse level ............ 0.45 V to 4.55 V
Input rise/fall time ....... 5 ns
Threshold level .............. input 0.8 V, 2 V/output 0.8 V, 2 V
29/35
¡ Semiconductor
MSM63P180
5V
Address Input
0V
CE
5V
0V
tCE
5V
OE
tOE
tDF
0V
tACC
Data Output
5V
0V
30/35
¡ Semiconductor
MSM63P180
(2) Write Operation
DC Characteristics
(VSS = 0 V, VCC = 5 V ±5%, VPP = 12.5 V ±0.5 V, Ta = 25°C ±5°C unless otherwise specified)
Min.
Typ.
Max.
Parameter
Symbol
Condition
Unit
VPP Power Supply Current
VCC Power Supply Current
Input Voltage
Output Current
IPP
CE = VIH
—
—
50
mA
ICC
—
—
—
100
mA
VIH
—
4.0
—
VCC
V
—
VIL
IOH
VOH = VCC – 0.5 V
0
–8
—
–4
1.0
–2
V
mA
IOL
VOL = 0.5 V
2
4
8
mA
AC Characteristics
(VSS = 0 V, VCC = 5 V ±5%, VPP = 12.5 V ±0.5 V, Ta = 25°C ±5°C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
Address Setup Time
Parameter
tAS
—
2.0
—
—
ms
OE Setup Time
tOES
—
2.0
—
—
ms
Data Setup Time
tDS
—
2.0
—
—
ms
Address Hold Time
tAH
—
0
—
—
ms
Data Hold Time
tDH
—
2.0
—
—
ms
OE Output Floating Delay Time
tDFP
—
0
—
130
ns
VPP Power Source Setup Time
tVS
—
2.0
—
—
ms
Initial Program Pulse Width
tPW
6 V ±0.25 V
0.95
1.0
1.05
ms
Additional Program Pulse Width
tOPW
6 V ±0.25 V
2.85
—
78.75
ms
OE Output Effective Delay Time
tOE
—
—
—
150
ns
Measurement conditions:
Input pulse level ............ 0.45 V to 4.55 V
Input rise/fall time ....... less than 20 ns
Threshold level .............. input 0.8 V, 2 V/output 0.8 V, 2 V
31/35
¡ Semiconductor
MSM63P180
5V
Address Input
Address N
0V
tAH
tAS
5V
Data Input-Output
Data Input
Data Output
0V
tDH
tDS
tOE
tDFP
12.5 V
VPP
0V
tVS
5V
CE
0V
tPW
tOES
tOPW
5V
OE
0V
32/35
¡ Semiconductor
MSM63P180
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cv, C12, and CG
are for reference only.
LCD
Crystal
32.768 kHz
COM1-16
SEG0-63
XT0
OSC0
ROS
CG
12 to 30 pF
3V
1.5 V
XT1
VDDH
OSC1
VDD
Cv 0.1 mF
Open
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
CB1
CB2
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
VDD4
VDD3
VDD2
VDD1
C1
0.1 mF
Push SW
Open
Buzzer
VDD5
C2
MSM63P180
Key Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
MD
VDDI
MDB
P4-7
VPP
Open
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
5.0 V
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
33/35
¡ Semiconductor
MSM63P180
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cv, C12, CG, CL0,
and CL1 are for reference only.
LCD
Crystal
32.768 kHz
CG
12 to 30 pF
VDD
COM1-16
CL0 30 pF
SEG0-63
XT0
OSC0
XT1
VDDH
OSC1
Ceramic
Resonator
CL1
30 pF
5.0 V
VDD
Cv
0.1 mF
Open
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
VDD5
VDD4
VDD3
VDD2
VDD1
C1
C12
0.1 mF
Push SW
Open
Buzzer
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
CB1
CB2
C2
MSM63P180
Key Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
VPP
RESET
TST1
TST2
MD
VDDI
MDB
P4-7
Open
VDD
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
34/35
¡ Semiconductor
MSM63P180
PACKAGE DIMENSIONS
(Unit : mm)
LQFP176-P-2424-0.50-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
35/35