OKI MSM63182A

E2E0055-19-41
¡ Semiconductor
MSM63182A
¡ Semiconductor
This version:MSM63182A
Apr. 1999
4-Bit Microcontroller with Built-in 512-Dot Matrix LCD Drivers, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63182A is an enhanced version of the MSM63182 in which supply currents have been
improved.
The MSM63182A is a CMOS 4-bit microcontroller with built-in 512-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63182A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63182A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188/A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
4K words
Basic instruction length is 16 bits/1 word
• Data memory space
384 nibbles
• External data memory space
1/27
¡ Semiconductor
MSM63182A
64 Kbytes (expandable by using an I/O port)
• Stack level
Call stack level
Register stack level
: 8 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port
: 2 ports ¥ 4 bits
Output port
: 4 ports ¥ 4 bits
Input-output port
: 3 ports ¥ 4 bits
• Buzzer function
Buzzer output
Buzzer output modes
: 0.946 to 5.461 kHz (adjustable in 15 steps)
: Intermittent sound 1, 2; simple sound; continuous sound
• LCD driver
Number of segments
: 512 Max. (32 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/27
¡ Semiconductor
MSM63182A
• Timers and counter
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Interrupt sources
External interrupt
Internal interrupt
• Operating voltage
When backup used
When backup not used
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K)
Chip
: 2
: 6 (watchdog timer interrupt is a nonmaskable interrupt)
: 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
: (Product name: MSM63182A-xxxGS-K)
: (Product name: MSM63182A-xxx)
xxx indicates a code number.
Differences Between the MSM63182 and the MSM63182A
The MSM63182A has the following improved characteristics.
• Supply currents (IDD1, IDD2, IDD3) in DC characteristics
• The VDDL voltage during a halt of high-speed clock oscillation
3/27
¡ Semiconductor
MSM63182A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
ALU
RSP
G
MIE
INSTRUCTION
DECODER
STACK
CAL: 8-level
REG: 16-level
PC
Z
ROM
4KW
BUS
CONTROL
D0-7*
EXTMEM
A0-15*
RD*
WR*
IR
RAM
384N
BUZZER
BD
BDB
INT182
INT
1
TST1
TST2
RST
INT
4
TBC
TST
INPUT
PORT
DATA BUS
RESET
BLD
XT0
XT1
OSC
INT
1
P0.0-P0.3
P1.0-P1.3
P4.0-P4.3
OUTPUT
PORT
100HzTC
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
OSC0
INT
1
OSC1
WDT
P8.0-P8.3
VDDH
VDD
CB1
I/O
PORT
BACK
UP
INT
1
CB2
VDD1
P9.0-P9.3
PA.0-PA.3
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDL
BIAS
LCD
&
DSPR
COM1-16
SEG0-31
VDDI
VSS
4/27
¡ Semiconductor
MSM63182A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
(NC)
(NC)
P7.3
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
(NC)
(NC)
(NC)
(NC)
(NC)
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
VDD
VDDL
OSC1
OSC0
RESET
XT1
XT0
TST2
TST1
P5.3
(NC)
(NC)
(NC)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(NC)
(NC)
(NC)
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
(NC)
(NC)
(NC)
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
(NC)
(NC)
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
VDDI
BDB
BD
P7.0
P7.1
P7.2
(NC)
(NC)
PIN CONFIGURATION (TOP VIEW)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/27
¡ Semiconductor
MSM63182A
PAD CONFIGURATION
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
54 SEG0
53 SEG1
52 SEG2
51 SEG3
50 SEG4
49 SEG5
48 SEG6
47 SEG7
46 SEG8
45 SEG9
44 SEG10
43 SEG11
42 SEG12
41 SEG13
40 SEG14
39 SEG15
38 SEG16
37 SEG17
36 SEG18
35 SEG19
34 SEG20
33 SEG21
32 SEG22
31 SEG23
30 SEG24
29 SEG25
28 SEG26
27 SEG27
26 SEG28
25 SEG29
24 SEG30
23 SEG31
P7.2
P7.1
P7.0
BD
BDB
VDDI
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
P8.3
P8.2
P8.1
P8.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
P6.0
P7.3
72 XT0
71 XT1
70 RESET
69 OSC0
68 OSC1
67 VDDL
66 VDD
65 CB2
64 CB1
63 VDDH
62 C2
61 C1
60 VDD5
59 VDD4
58 VDD3
57 VDD2
56 VDD1
55 VSS
75 P5.3
74 TST1
73 TST2
Pad Layout
Chip Size
Chip Thickness
Coordinate Origin
Pad Hole Size
Pad Size
Minimum Pad Pitch
:
:
:
:
:
:
X
4.44 mm ¥ 4.92 mm
350 mm (typ.)
Chip center
100 mm ¥ 100 mm
110 mm ¥ 110 mm
140 mm
Note: The chip substrate voltage is VSS.
6/27
¡ Semiconductor
MSM63182A
Pad Coordinates
Pad
Pad
Pad
Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm)
1
P7.2
–1547
–2265
37
SEG17
2075
–210
73
TST2
–1247
2265
2
P7.1
–1407
–2265
38
SEG16
2075
–70
74
TST1
–1387
2265
3
P7.0
–1267
–2265
39
SEG15
2075
70
75
P5.3
–1548
2265
4
BD
–1090
–2265
40
SEG14
2075
210
76
P5.2
–2075
2170
5
BDB
–950
–2265
41
SEG13
2075
350
77
P5.1
–2075
2030
6
VDDI
–810
–2265
42
SEG12
2075
490
78
P5.0
–2075
1890
7
COM1
–630
–2265
43
SEG11
2075
630
79
P4.3
–2075
1750
8
COM2
–490
–2265
44
SEG10
2075
770
80
P4.2
–2075
1610
9
COM3
–350
–2265
45
SEG9
2075
910
81
P4.1
–2075
1470
10
COM4
–210
–2265
46
SEG8
2075
1050
82
P4.0
–2075
1330
11
COM5
–70
–2265
47
SEG7
2075
1190
83
P0.3
–2075
1190
12
COM6
70
–2265
48
SEG6
2075
1330
84
P0.2
–2075
1050
13
COM7
210
–2265
49
SEG5
2075
1470
85
P0.1
–2075
910
14
COM8
350
–2265
50
SEG4
2075
1610
86
P0.0
–2075
770
15
COM9
490
–2265
51
SEG3
2075
1750
87
P8.3
–2075
630
16
COM10
630
–2265
52
SEG2
2075
1890
88
P8.2
–2075
490
17
COM11
770
–2265
53
SEG1
2075
2030
89
P8.1
–2075
350
18
COM12
910
–2265
54
SEG0
2075
2170
90
P8.0
–2075
210
19
COM13
1050
–2265
55
VSS
1575
2265
91
P9.3
–2075
70
20
COM14
1190
–2265
56
VDD1
1425
2265
92
P9.2
–2075
–70
21
COM15
1330
–2265
57
VDD2
1275
2265
93
P9.1
–2075
–210
22
COM16
1470
–2265
58
VDD3
1125
2265
94
P9.0
–2075
–350
23
SEG31
2075
–2170
59
VDD4
975
2265
95
PA.3
–2075
–490
24
SEG30
2075
–2030
60
VDD5
825
2265
96
PA.2
–2075
–630
25
SEG29
2075
–1890
61
C1
675
2265
97
PA.1
–2075
–770
26
SEG28
2075
–1750
62
C2
525
2265
98
PA.0
–2075
–910
27
SEG27
2075
–1610
63
VDDH
375
2265
99
P1.3
–2075
–1050
28
SEG26
2075
–1470
64
CB1
225
2265
100
P1.2
–2075
–1190
29
SEG25
2075
–1330
65
CB2
75
2265
101
P1.1
–2075
–1330
30
SEG24
2075
–1190
66
VDD
–75
2265
102
P1.0
–2075
–1470
31
SEG23
2075
–1050
67
VDDL
–225
2265
103
P6.3
–2075
–1610
32
SEG22
2075
–910
68
OSC1
–375
2265
104
P6.2
–2075
–1750
33
SEG21
2075
–770
69
OSC0
–525
2265
105
P6.1
–2075
–1890
34
SEG20
2075
–630
70
RESET
–675
2265
106
P6.0
–2075
–2030
35
SEG19
2075
–490
71
XT1
–825
2265
107
P7.3
–2075
–2170
36
SEG18
2075
–350
72
XT0
–975
2265
7/27
¡ Semiconductor
MSM63182A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63182A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Power
Supply
Pin
Type
VDD
52
—
Positive power supply
VSS
41
—
Negative power supply
Description
VDD1
42
Power supply pins for LCD bias (internally generated).
VDD2
43
Capacitors (0.1 mF) should be connected between these pins and
VDD3
44
VDD4
45
VDD5
46
C1
C2
—
VSS.
47
—
Capacitor connection pins for LCD bias generation.
48
—
A capacitor (0.1 mF) should be connected between C1 and C2.
VDDI
110
—
VDDL
53
—
VDDH
49
—
CB1
50
—
Pins to connect a capacitor for voltage multiplier.
CB2
51
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
XT0
58
I
XT1
57
O
and CG (5 to 25 pF) should be connected between XT0 and VSS.
OSC0
55
I
High-speed clock oscillation pins.
OSC1
54
O
oscillation resistor (ROS) should be connected to these pins.
Input pins for testing.
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and VSS.
Voltage multiplier pin for power supply backup (internally generated).
A capacitor (1.0 mF) should be connected between this pin and VSS.
Low-speed clock oscillation pins.
A 32.768 kHz crystal should be connected between XT0 and XT1,
Oscillation
A ceramic resonator and capacitors (CL0, CL1) or external
TST1
60
I
TST2
59
I
A pull-down resistor is internally connected to these pins.
Test
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Reset
RESET
56
I
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Buzzer
BD
108
O
Buzzer output pin (non-inverted output)
BDB
109
O
Buzzer output pin (inverted output)
8/27
¡ Semiconductor
MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P0.0/INT5
78
P0.1/INT5
77
P0.2/INT5
76
P0.3/INT5
75
P1.0/INT5
94
P1.1/INT5
93
P1.2/INT5
92
P1.3/INT5
91
P4.0/A0
74
P4.1/A1
73
P4.2/A2
72
P4.3/A3
71
P5.0/A4
70
P5.1/A5
69
P5.2/A6
68
P5.3/A7
61
P6.0/A8
98
P6.1/A9
97
P6.2/A10
96
P6.3/A11
95
P7.0/A12
107
P7.1/A13
106
P7.2/A14
105
P7.3/A15
99
P8.0/RD
82
P8.1/WR
81
P8.2
80
or high-impedance input is selectable for each bit.
P8.3/INT4
79
In output mode, P-channel open drain output, N-channel open
P9.0/D0
86
drain output, CMOS output, or high-impedance output is
P9.1/D1
85
P9.2/D2
84
P9.3/D3
83
PA.0/D4
90
PA.1/D5
89
PA.2/D6
88
PA.3/D7
87
Type
Description
4-bit input ports.
I
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
4-bit output ports.
O
P-channel open drain output, N-channel open drain output,
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
4-bit input-output ports.
I/O
In input mode, pull-up resistor input, pull-down resistor input,
selectable for each bit.
I/O
I/O
9/27
¡ Semiconductor
MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
COM1
111
COM2
112
COM3
113
COM4
114
COM5
115
COM6
116
COM7
117
COM8
118
COM9
119
COM10
120
COM11
121
COM12
122
COM13
123
COM14
124
COM15
125
COM16
126
SEG0
35
SEG1
34
SEG2
33
SEG3
32
SEG4
31
SEG5
30
SEG6
29
SEG7
28
SEG8
27
SEG9
26
SEG10
25
SEG11
24
SEG12
23
SEG13
22
SEG14
21
SEG15
20
SEG16
19
SEG17
18
SEG18
17
SEG19
16
SEG20
15
SEG21
14
SEG22
13
SEG23
12
SEG24
11
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
O
10/27
¡ Semiconductor
MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
SEG25
10
SEG26
9
SEG27
8
SEG28
7
SEG29
6
SEG30
5
SEG31
4
Type
Description
LCD segment signal output pins
O
11/27
¡ Semiconductor
MSM63182A
Table 2 shows the secondary functions of each pin of the MSM63182A.
Table 2 Pin Descriptions (Secondary Functions)
Symbol
Pin
Type
P8.3/INT4
79
I
P0.0/INT5
78
External 5 interrupt input pins.
P0.1/INT5
77
The change of input signal level causes an interrupt to occur.
External
P0.2/INT5
76
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
Interrupt
P0.3/INT5
75
P1.0/INT5
94
P1.1/INT5
93
P1.2/INT5
92
P1.3/INT5
91
Function
Description
External 4 interrupt input pin.
The change of input signal level causes an interrupt to occur.
Enable register (P1IE) enable or disable an interrupt for each bit.
I
12/27
¡ Semiconductor
MSM63182A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
External
Memory
Symbol
Pin
P4.0/A0
74
P4.1/A1
73
P4.2/A2
72
P4.3/A3
71
P5.0/A4
70
P5.1/A5
69
P5.2/A6
68
P5.3/A7
61
P6.0/A8
98
P6.1/A9
97
P6.2/A10
96
P6.3/A11
95
P7.0/A12
107
P7.1/A13
106
P7.2/A14
105
P7.3/A15
99
P9.0/D0
86
P9.1/D1
85
P9.2/D2
84
P9.3/D3
83
PA.0/D4
90
PA.1/D5
89
PA.2/D6
88
PA.3/D7
87
Type
Description
Address output bus for external memory
O
Data bus for external memory
I/O
P8.0/RD
82
O
Read signal output pin for external memory (negative logic)
P8.1/WR
81
O
Write signal output pin for external memory (negative logic)
13/27
¡ Semiconductor
MSM63182A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.6
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.9
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +4.2
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +6.8
V
Power Supply Voltage 6
VDD
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 7
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 8
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 9
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 Output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 Output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 Output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 Output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 Output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 7
VOUT7
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 8
VOUT8
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
14/27
¡ Semiconductor
MSM63182A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
0.9 to 2.7
V
VDDI
—
0.9 to 5.5
V
kHz
—
30 to 35
VDD = 1.2 to 2.7 V
300k to 500k
VDD = 1.5 to 2.7 V
200k to 1M
VDD = 1.2 to 2.7 V
100 to 300
VDD = 1.5 to 2.7 V
50 to 300
Symbol
Condition
Range
Unit
fXT
fCM
ROS
Hz
kW
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Top
—
–20 to +70
°C
VDD
—
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
V
fXT
—
30 to 35
kHz
VDD = 1.8 to 5.5 V
300k to 500k
VDD = 2.2 to 5.5 V
300k to 1M
VDD = 2.7 to 5.5 V
200k to 2M
fCM
ROS
VDD = 1.8 to 5.5 V
100 to 300
VDD = 2.2 to 5.5 V
50 to 300
VDD = 2.7 to 5.5 V
30 to 300
Hz
kW
15/27
¡ Semiconductor
MSM63182A
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
VDD2 Voltage
VDD2 Voltage Temperature Deviation
VDD1 Voltage
VDD3 Voltage
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min.
Typ.
Max. Unit suring
Circuit
1/5 bias, 1/4 bias
V
VDD2
1.7
1.8
1.9
(Ta = 25°C)
DVDD2
—
VDD1
1/5 bias, 1/4 bias
Typ.– 0.2 1/2 ¥ VDD2 Typ.+ 0.2
1/5 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
VDD3
1/4 bias (connect
VDD3 and VDD2)
VDD4 Voltage
VDD4
VDD5 Voltage
VDD5
VDDH Voltage
(Backup used)
VDDL Voltage
VDDH
VDDL
Crystal Oscillation Start Voltage
VSTA
Crystal Oscillation Hold Voltage
VHOLD
—
Typ.– 0.2
–4
VDD2
—
Typ.+ 0.2
1/5 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
1/4 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
1/5 bias
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.5
1/4 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
High-speed clock oscillation
stopped
VDD = 1.5 V
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
High-speed clock
oscillation stopped
mV/°C
V
V
V
V
2.8
—
3.0
V
2.0
—
2.7
V
0.8
1.3
1.8
V
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
1.2
—
5.5
V
Oscillation start time:
within 5 seconds
1.0
—
—
V
1
Backup
0.9
—
—
V
Backup not used
1.7
—
—
V
Crystal Oscillation Stop Detect Time
TSTOP
—
0.1
—
5.0
ms
External Crystal Oscillator Capacitance
CG
—
5
—
25
pF
Internal Crystal Oscillator Capacitance
CD
—
20
25
30
pF
—
30
—
pF
External Ceramic Oscillator
Capacitance
Internal RC Oscillator Capacitance
CL0, 1
COS
POR Voltage
VPOR1
Non-POR Voltage
VPOR2
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
—
8
12
16
pF
VDD = 1.5 V
0.0
—
0.4
V
VDD = 3.0 V
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.0
—
3.0
V
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
16/27
¡ Semiconductor
MSM63182A
DC Characteristics (continued)
• When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
5.1
6.5
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
5.1
7.0
stopped)
Supply Current 2
IDD2
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
3.9
5.0
—
3.9
7.0
mA
1
Supply Current 3
IDD3
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
—
13
17
mA
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation
(RC oscillation, f = approx. 720 kHz, ROS = 51 kW)
—
600
800
mA
Supply Current 5
IDD5
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
—
700
900
mA
• When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
Ta = –20 to +50°C —
2.4
2.8
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
2.4
3.0
stopped)
Supply Current 2
Supply Current 3
Supply Current 4
Supply Current 5
IDD2
IDD3
IDD4
IDD5
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
1.7
2.2
—
1.7
2.5
—
6.3
8.0
f = approx. 800 kHz,
ROS = 51 kW
—
450
600
f = approx. 500 kHz,
ROS = 100 kW
—
350
450
—
850
1000
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
CPU is in operation at
high-speed oscillation
(RC oscillation)
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
mA
mA
1
mA
mA
17/27
¡ Semiconductor
MSM63182A
DC Characteristics (continued)
Parameter
Output Current 1
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
(PA.0 to PA.3)
Symbol
IOH1
IOL1
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
VDDI = 1.5 V
–2.0
–1.2
–0.2
mA
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
–5.0
–3.0
–1.0
mA
VDDI = 5.0 V
–8.0
–4.0
–1.5
mA
VDDI = 1.5 V
0.2
1.2
2.0
mA
VDDI = 3.0 V
1.0
3.0
5.0
mA
VOL1 = 0.5 V
Output Current 2
(BD, BDB)
Output Current 3
(SEG0 to SEG31)
(COM1 to COM16)
IOH2
(OSC1)
4.0
8.0
mA
–2.5
–1.3
–0.4
mA
VDD = 3.0 V
–6.0
–4.0
–2.0
mA
VDD = VDDH = 5.0 V
–9.0
–5.5
–3.0
mA
VDD = 1.5 V
0.4
1.3
2.5
mA
VDD = 3.0 V
2.0
4.0
6.0
mA
VDD = VDDH = 5.0 V
3.0
5.5
9.0
mA
—
—
–4
mA
VOL2 = 0.7 V
IOH3
VOH3 = VDD5 – 0.2 V (VDD5 level)
IOHM3
VOHM3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
mA
IOHM3S
VOHM3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
mA
IOMH3
VOMH3 = VDD3 + 0.2 V (VDD3 level)
4
—
—
mA
IOMH3S
VOMH3S = VDD3 – 0.2 V (VDD3 level)
—
—
–4
mA
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
mA
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
mA
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
mA
IOLM3S
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
mA
VOL3 = VSS + 0.2 V (VSS level)
4
—
—
mA
IOH4R
IOL4R
IOH4C
IOL4C
Output Leakage
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
(PA.0 to PA.3)
1.5
VDD = 1.5 V
IOL2
IOL3
Output Current 4
VOH2 = VDD – 0.7 V
VDDI = 5.0 V
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
–2.5
–1.5
–0.75
mA
(RC oscillation)
VDD = VDDH = 5.0 V
–3.5
–2.0
–1.0
mA
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.75
1.5
2.5
mA
(RC oscillation)
VDD = VDDH = 5.0 V
1.0
2.0
3.5
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–300
–180
–60
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
–450
–280
–100
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
60
120
300
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
100
200
450
mA
IOOH
VOH = VDDI
—
—
0.3
mA
IOOL
VOL = VSS
–0.3
—
—
mA
2
18/27
¡ Semiconductor
MSM63182A
DC Characteristics (continued)
Parameter
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
Symbol
IIH1
IIL1
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
30
90
180
mA
70
250
600
mA
VDDI = 5.0 V
VDDI = 1.5 V
–30
–10
–2
mA
VDDI = 3.0 V
–180
–90
–30
mA
VDDI = 5.0 V
–600
–250
–70
mA
0.0
—
1.0
mA
VIL1 = VSS (in a high impedance state)
–1.0
—
0.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–200
–110
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
–600
–350
–150
mA
IIH2R
VIH2R = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL2R
VIL2R = VSS (RC oscillation)
–1.0
—
0.0
mA
IIL2C
VDD = VDDH = 3.0 V
0.1
0.5
1.0
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
0.75
1.5
3.0
mA
VIL2C = VSS
VDD = VDDH = 3.0 V
–1.0
–0.5
–0.1
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–3.0
–1.5
–0.75
mA
VIH2C = VDDH
Input Current 3
IIH3
VIH3 = VDD
IIL3
VIL3 = VSS
VDD = 1.5 V
10
50
80
mA
VDD = 3.0 V
150
350
600
mA
VDD = VDDH = 5.0 V
Input Current 4
(TST1, TST2)
mA
VDDI = 3.0 V
IIL1Z
IIH2C
(RESET)
30
2
VIH1 = VDDI (in a high impedance state)
IIL2
10
VDDI = 1.5 V
IIH1Z
Input Current 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
0.5
1.0
2.0
mA
–1.0
—
0.0
mA
50
150
300
mA
VDD = 3.0 V
0.5
1.0
1.5
mA
VDD = VDDH = 5.0 V
1.25
2.5
4.0
mA
–1.0
—
0.0
mA
VDD = 1.5 V
IIH4
IIL4
VIH4 = VDD
VIL4 = VSS
3
19/27
¡ Semiconductor
MSM63182A
DC Characteristics (continued)
Parameter
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
Input Voltage 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
VIH1
VIL1
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VIH3
VIL3
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(PA.0 to PA.3)
DVT1
Hysteresis Width 2
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
DVT2
CIN
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
VDDI = 3.0 V
0.0
—
0.6
V
VDDI = 5.0 V
0.0
—
1.0
V
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
VDD = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
VDDI = 5.0 V
0.25
1.0
1.5
V
VDD = 1.5 V
0.05
0.1
0.3
V
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = VDDH = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
4
1
20/27
¡ Semiconductor
MSM63182A
Measuring circuit 1
CB1
CG
Cb12
XT0
CB2
C1
32.768 kHz
Crystal
XT1
C12
C2
q
*1
w
OSC0
OSC1
VSS VDD VDDI VDD1
A
Ca
V
Ca, Cb, Cc, Cd, Ce, Cl, C12
Cb12, Ch
CG
CL0
CL1
Ceramic Resonator
VDD2
VDD3
VDD4
VDD5
VDDH VDDL
Cb
Cc
Cd
Ce
Ch
V
: 0.1 mF
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
V
V
V
Cl
V
V
*1 RC Oscillator
q
ROS
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
A
*2
INPUT
VIL
VSS
OUTPUT
VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
21/27
¡ Semiconductor
MSM63182A
Measuring circuit 3
*4
A
INPUT
OUTPUT
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
*4
INPUT
VIL
VSS
OUTPUT
VDD
VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
22/27
¡ Semiconductor
MSM63182A
AC Characteristics (External Memory Interface)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Symbol
Condition
Min.
Typ.
Read Cycle Time
Parameter
Max.
Unit
tRC
—
—
RD Output Delay Time
tOE
—
—
61.0
—
ms
—
5.0
ms
Output Valid Time
tOHA
—
External Memory Output Delay Time
tDO
—
—
—
5.0
ms
—
—
5.0
ms
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
RD Output Delay Time
tRC
—
1.0
—
—
ms
tOE
—
—
—
100
ns
Output Valid Time
tOHA
—
—
—
100
ns
External Memory Output Delay Time
tDO
—
—
—
150
ns
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 - P4
(A15 - A0)
Port setup value
Address output
Port setup value
5 V (VDDI)
0 V (VSS)
P8.0
(RD)
tOE
PA, P9
(D7 - D0)
5 V (VDDI)
0 V (VSS)
Port setup value
Input data
tOHA
Port setup value
5 V (VDDI)
0 V (VSS)
tDO
23/27
¡ Semiconductor
MSM63182A
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
—
61.0
—
ms
Address Setup Time
tAS
—
—
30.5
—
ms
Write Time
tW
—
—
15.3
—
ms
Write Recovery Time
tWR
—
—
15.3
—
ms
Data Setup Time
tDS
—
—
45.8
—
ms
Data Hold Time
tDH
—
—
15.3
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
Parameter
tWC
—
1.0
—
—
ms
Address Setup Time
tAS
—
0.4
—
—
ms
Write Time
tW
—
0.2
—
—
ms
Write Recovery Time
tWR
—
0.2
—
—
ms
Data Setup Time
tDS
—
0.7
—
—
ms
Data Hold Time
tDH
—
0.2
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
P7 - P4
(A15 - A0)
PA, P9
(D7 - D0)
Port setup value
Address output
Port setup value
Output data
tDS
tDH
Port setup value
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
P8.1
(WR)
tAS
tW
tWR
24/27
¡ Semiconductor
MSM63182A
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
LCD
Crystal
32.768 kHz
COM1-16
SEG0-31
XT0
OSC0
ROS
CG
5 to
25 pF
Ch
1.0 mF
1.5 V
XT1
VDDH
OSC1
VDD
Cv 0.1 mF
Cb12
1.0 mF
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
CB2
VDDL
Open
P8.3
P8.2
VDD5
VDD4
VDD3
VDD2
VDD1
C1
0.1 mF
Push SW
Buzzer
CB1
C2
MSM63182A
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
BD
VDDI
BDB
P4-7
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
5.0 V
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
25/27
¡ Semiconductor
MSM63182A
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
LCD
Crystal
32.768 kHz
COM1-16
CL0 30 pF
SEG0-31
XT0
OSC0
XT1
VDDH
OSC1
Ceramic
Resonator
(Example: 1 MHz)
CG
5 to 25 pF
VDD
CL1
30 pF
5.0 V
VDD
Cv 0.1 mF Open
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
CB1
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
C12
0.1 mF
Push SW
Open
Buzzer
P8.3
P8.2
C2
MSM63182A
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
BD
VDDI
BDB
P4-7
VDD
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
26/27
¡ Semiconductor
MSM63182A
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/27
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan