OKI MSM63188A

E2E0056-19-62
¡ Semiconductor
MSM63188A
¡ Semiconductor
This version:
Jun. 1999
MSM63188A
4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit,
Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63188A is an enhanced version of the MSM63188 in which supply currents have been
improved.
The MSM63188A is a CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63188A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63188A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188/A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
16K words
Basic instruction length is 16 bits/1 word
• Data memory space
3584 nibbles
• External data memory space
64 Kbytes (expandable by using an I/O port)
1/32
¡ Semiconductor
• Stack level
Call stack level
Register stack level
MSM63188A
: 16 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port
: 2 ports ¥ 4 bits
Output port
: 6 ports ¥ 4 bits
Input-output port
: 6 ports ¥ 4 bits
• Melody output function
Melody sound frequency
Tone length
Tempo
Note data
Buzzer drive signal output
:
:
:
:
:
529 to 2979 Hz
63 types
15 types
Resides in the program memory
4 kHz
• LCD driver
Number of segments
: 1024 Max. (64 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Multiplier/divider circuits
Multiplier : (8 bits) ¥ (8 bits) Æ Product (16 bits)
Divider
: (16 bits) ÷ (8 bits) Æ Quotient (16 bits), Remainder (8 bits)
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/32
¡ Semiconductor
MSM63188A
• Timers and counter
8-bit timer ¥ 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
• Interrupt sources
External interrupt
Internal interrupt
• Operating voltage
When backup used
When backup not used
: UART mode, synchronous mode
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
: 32.768 kHz (internal clock mode), external
clock frequency
: 5 to 8 bits
: 4
: 13 (watchdog timer interrupt is a nonmaskable interrupt)
: 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
176-pin plastic LQFP (LQFP176-P-2424-0.50-BK) : (Product name: MSM63188A-xxxGS-BK)
Chip
: (Product name: MSM63188A-xxx)
xxx indicates a code number.
Differences Between the MSM63188 and the MSM63188A
The MSM63188A has the following improved characteristics.
• Supply currents (IDD1, IDD2, IDD3) in DC characteristics
• The VDDL voltage during a halt of high-speed clock oscillation
3/32
¡ Semiconductor
MSM63188A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
C
SP
G
ALU
RSP
MIE
STACK
INSTRUCTION
CAL : 16-level
DECODER
PC
Z
ROM
16KW
BUS
D0-7*
EXTMEM
CON-
A0-15*
TROL
RD*
WR*
IR
REG : 16-level
INT
4
TIMER
8bit ¥ 4
RAM
3584N
INT
2
INT188
INT
1
RST
MULDIV
INT
TST1
TST2
XT0
XT1
OSC0
OSC1
4
TST
TBC
RXC*
TXC*
RXD*
TXD*
MD
MELODY
DATA BUS
RESET
SIO
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
MDB
INT
1
INPUT
PORT
P0.0-P0.3
P1.0-P1.3
BLD
P2.0-P2.3
INT
OSC
1
TBCCLK*
HSCLK*
P3.0-P3.3
100HzTC
OUTPUT
PORT
1
P4.0-P4.3
P5.0-P5.3
INT
P6.0-P6.3
WDT
P7.0-P7.3
VDDH
VDD
CB1
P8.0-P8.3
BACK
UP
P9.0-P9.3
CB2
I/O
PORT
VDD1
PB.0-PB.3
VDD2
VDD3
VDD4
PA.0-PA.3
INT
BIAS
PC.0-PC.3
3
PD.0-PD.3
VDD5
C1
C2
VDDL
LCLK*
FRAME*
LCD
&
DSPR
COM1-16
SEG0-63
VDDI
VSS
4/32
¡ Semiconductor
MSM63188A
(NC)
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
(NC)
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
(NC)
(NC)
PIN CONFIGURATION (TOP VIEW)
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P5.0
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
P8.0
P8.1
P8.2
P8.3
P9.0
P9.1
P9.2
P9.3
PA.0
PA.1
PA.2
PA.3
PB.0
PB.1
PB.2
PB.3
PC.0
PC.1
PC.2
PC.3
PD.0
PD.1
PD.2
PD.3
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
VDD
VDDL
OSC1
OSC0
RESET
XT1
XT0
TST2
TST1
(NC)
(NC)
MD
MDB
(NC)
VDDI
(NC)
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
176-Pin Plastic LQFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/32
¡ Semiconductor
MSM63188A
PAD CONFIGURATION
VDDI
MDB
MD
TST1
TST2
XT0
XT1
RESET
OSC0
OSC1
VDDL
VDD
CB2
CB1
VDDH
C2
C1
VDD5
VDD4
VDD3
VDD2
VDD1
VSS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
156
157
158
159
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
P5.3
P5.2
P5.1
P5.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.3
P4.2
P4.1
P4.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
PD.3
PD.2
PD.1
PD.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.3
P7.2
P7.1
P7.0
P6.3
P6.2
P6.1
P6.0
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
Pad Layout
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
Y
X
Chip Size
Chip Thickness
Coordinate Origin
Pad Hole Size
Pad Size
Minimum Pad Pitch
:
:
:
:
:
:
6.60 mm ¥ 6.60 mm
350 mm (typ.)
Chip center
100 mm ¥ 100 mm
110 mm ¥ 110 mm
140 mm
Note: The chip substrate voltage is VSS.
6/32
¡ Semiconductor
MSM63188A
Pad Coordinates
Pad
Pad
Pad
Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm)
1
P4.3
–2837
–3105
42
SEG42
3155
–2870
83
SEG1
3155
2870
2
P4.2
–2697
–3105
43
SEG41
3155
–2730
84
SEG0
3155
3010
3
P4.1
–2557
–3105
44
SEG40
3155
–2590
85
COM16
2705
3105
4
P4.0
–2417
–3105
45
SEG39
3155
–2450
86
COM15
2565
3105
5
P3.3
–2277
–3105
46
SEG38
3155
–2310
87
COM14
2425
3105
6
P3.2
–2137
–3105
47
SEG37
3155
–2170
88
COM13
2285
3105
7
P3.1
–1997
–3105
48
SEG36
3155
–2030
89
COM12
2145
3105
8
P3.0
–1857
–3105
49
SEG35
3155
–1890
90
COM11
2005
3105
9
P2.3
–1717
–3105
50
SEG34
3155
–1750
91
COM10
1865
3105
10
P2.2
–1577
–3105
51
SEG33
3155
–1610
92
COM9
1725
3105
11
P2.1
–1437
–3105
52
SEG32
3155
–1470
93
COM8
1585
3105
12
P2.0
–1297
–3105
53
SEG31
3155
–1330
94
COM7
1445
3105
13
P1.3
–1157
–3105
54
SEG30
3155
–1190
95
COM6
1305
3105
14
P1.2
–1017
–3105
55
SEG29
3155
–1050
96
COM5
1165
3105
15
P1.1
–877
–3105
56
SEG28
3155
–910
97
COM4
1025
3105
16
P1.0
–737
–3105
57
SEG27
3155
–770
98
COM3
885
3105
17
P0.3
–597
–3105
58
SEG26
3155
–630
99
COM2
745
3105
18
P0.2
–457
–3105
59
SEG25
3155
–490
100
COM1
605
3105
19
P0.1
–317
–3105
60
SEG24
3155
–350
101
VSS
420
3105
20
P0.0
–177
–3105
61
SEG23
3155
–210
102
VDD1
270
3105
21
SEG63
54
–3105
62
SEG22
3155
–70
103
VDD2
120
3105
22
SEG62
194
–3105
63
SEG21
3155
70
104
VDD3
–30
3105
23
SEG61
334
–3105
64
SEG20
3155
210
105
VDD4
–179
3105
24
SEG60
474
–3105
65
SEG19
3155
350
106
VDD5
–329
3105
25
SEG59
614
–3105
66
SEG18
3155
490
107
C1
–479
3105
26
SEG58
754
–3105
67
SEG17
3155
630
108
C2
–629
3105
27
SEG57
894
–3105
68
SEG16
3155
770
109
VDDH
–779
3105
28
SEG56
1034
–3105
69
SEG15
3155
910
110
CB1
–929
3105
29
SEG55
1174
–3105
70
SEG14
3155
1050
111
CB2
–1079
3105
30
SEG54
1314
–3105
71
SEG13
3155
1190
112
VDD
–1229
3105
31
SEG53
1454
–3105
72
SEG12
3155
1330
113
VDDL
–1379
3105
32
SEG52
1594
–3105
73
SEG11
3155
1470
114
OSC1
–1529
3105
33
SEG51
1734
–3105
74
SEG10
3155
1610
115
OSC0
–1679
3105
34
SEG50
1874
–3105
75
SEG9
3155
1750
116
RESET
–1829
3105
35
SEG49
2014
–3105
76
SEG8
3155
1890
117
XT1
–1979
3105
36
SEG48
2154
–3105
77
SEG7
3155
2030
118
XT0
–2129
3105
37
SEG47
2294
–3105
78
SEG6
3155
2170
119
TST2
–2324
3105
38
SEG46
2434
–3105
79
SEG5
3155
2310
120
TST1
–2464
3105
39
SEG45
2574
–3105
80
SEG4
3155
2450
121
MD
–2604
3105
40
SEG44
2714
–3105
81
SEG3
3155
2590
122
MDB
–2744
3105
41
SEG43
3155
–3010
82
SEG2
3155
2730
123
VDDI
–2884
3105
7/32
¡ Semiconductor
MSM63188A
Pad Coordinates (continued)
Pad
Pad
Pad
Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm)
124
PD.3
–3155
2428
136
PA.3
–3155
748
148
P7.3
–3155
–932
125
PD.2
–3155
2288
137
PA.2
–3155
608
149
P7.2
–3155
–1072
126
PD.1
–3155
2148
138
PA.1
–3155
468
150
P7.1
–3155
–1212
127
PD.0
–3155
2008
139
PA.0
–3155
328
151
P7.0
–3155
–1352
128
PC.3
–3155
1868
140
P9.3
–3155
188
152
P6.3
–3155
–1492
129
PC.2
–3155
1728
141
P9.2
–3155
48
153
P6.2
–3155
–1632
130
PC.1
–3155
1588
142
P9.1
–3155
–92
154
P6.1
–3155
–1772
131
PC.0
–3155
1448
143
P9.0
–3155
–232
155
P6.0
–3155
–1912
132
PB.3
–3155
1308
144
P8.3
–3155
–372
156
P5.3
–3155
–2172
133
PB.2
–3155
1168
145
P8.2
–3155
–512
157
P5.2
–3155
–2312
134
PB.1
–3155
1028
146
P8.1
–3155
–652
158
P5.1
–3155
–2452
135
PB.0
–3155
888
147
P8.0
–3155
–792
159
P5.0
–3155
–2592
8/32
¡ Semiconductor
MSM63188A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63188A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Power
Supply
Description
Pin
Type
VDD
73
—
Positive power supply
VSS
62
—
Negative power supply
VDD1
63
Power supply pins for LCD bias (internally generated).
VDD2
64
Capacitors (0.1 mF) should be connected between these pins and
VDD3
65
VDD4
66
VDD5
67
C1
C2
—
VSS.
68
—
Capacitor connection pins for LCD bias generation.
69
—
A capacitor (0.1 mF) should be connected between C1 and C2.
VDDI
87
—
VDDL
74
—
VDDH
70
—
CB1
71
—
Pins to connect a capacitor for voltage multiplier.
CB2
72
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
XT0
79
I
XT1
78
O
and CG (5 to 25 pF) should be connected between XT0 and VSS.
OSC0
76
I
High-speed clock oscillation pins.
OSC1
75
O
oscillation resistor (ROS) should be connected to these pins.
TST1
81
I
Input pins for testing.
TST2
80
I
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and VSS.
Voltage multiplier pin for power supply backup (internally generated).
A capacitor (1.0 mF) should be connected between this pin and VSS.
Low-speed clock oscillation pins.
A 32.768 kHz crystal should be connected between XT0 and XT1,
Oscillation
A ceramic resonator and capacitors (CL0, CL1) or external
A pull-down resistor is internally connected to these pins.
Test
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Reset
RESET
77
I
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Melody
MD
84
O
Melody output pin (non-inverted output)
MDB
85
O
Melody output pin (inverted output)
9/32
¡ Semiconductor
MSM63188A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P0.0/INT5
154
P0.1/INT5
153
P0.2/INT5
152
P0.3/INT5
151
P1.0/INT5
150
P1.1/INT5
149
P1.2/INT5
148
P1.3/INT5
147
P2.0
146
P2.1
145
P2.2
144
P2.3
143
P3.0
142
P3.1
141
P3.2
140
P3.3
139
P4.0/A0
138
P4.1/A1
137
P4.2/A2
136
P4.3/A3
135
P5.0/A4
132
P5.1/A5
131
P5.2/A6
130
P5.3/A7
129
P6.0/A8
128
P6.1/A9
127
P6.2/A10
126
P6.3/A11
125
P7.0/A12
124
P7.1/A13
123
P7.2/A14
122
P7.3/A15
121
Type
Description
4-bit input ports.
I
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
4-bit output ports.
O
P-channel open drain output, N-channel open drain output,
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
O
O
10/32
¡ Semiconductor
MSM63188A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P8.0/RD
120
P8.1/WR
119
P8.2
118
P8.3/INT4
117
In output mode, P-channel open drain output, N-channel open
P9.0/D0
116
drain output, CMOS output, or high-impedance output is
P9.1/D1
115
P9.2/D2
114
P9.3/D3
113
PA.0/D4
112
PA.1/D5
111
PA.2/D6
110
PA.3/D7
109
PB.0/INT0/
TM0CAP/
TM0OVF
PB.1/INT0/
TM1CAP/
TM1OVF
PB.2/INT0/T02CK
Type
Description
4-bit input-output ports.
In input mode, pull-up resistor input, pull-down resistor input,
I/O
or high-impedance input is selectable for each bit.
selectable for each bit.
I/O
I/O
108
107
I/O
106
PB.3/INT0/T13CK
105
PC.0/INT1/RXD
104
PC.1/INT1/TXC
103
PC.2/INT1/RXC
102
PC.3/INT1/TXD
101
PD.0/FRAME
100
PD.1/LCLK
99
PD.2/TBCCLK
98
PD.3/HSCLK
97
I/O
I/O
11/32
¡ Semiconductor
MSM63188A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
COM1
61
COM2
60
COM3
59
COM4
58
COM5
57
COM6
56
COM7
55
COM8
54
COM9
53
COM10
52
COM11
51
COM12
50
COM13
49
COM14
48
COM15
47
COM16
46
SEG0
44
SEG1
43
SEG2
42
SEG3
41
SEG4
40
SEG5
39
SEG6
38
SEG7
37
SEG8
36
SEG9
35
SEG10
34
SEG11
33
SEG12
32
SEG13
31
SEG14
30
SEG15
29
SEG16
28
SEG17
27
SEG18
26
SEG19
25
SEG20
24
SEG21
23
SEG22
22
SEG23
21
SEG24
20
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
O
12/32
¡ Semiconductor
MSM63188A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
SEG25
19
SEG26
18
SEG27
17
SEG28
16
SEG29
15
SEG30
14
SEG31
13
SEG32
12
SEG33
11
SEG34
10
SEG35
9
SEG36
8
SEG37
7
SEG38
6
SEG39
5
SEG40
4
SEG41
3
SEG42
2
SEG43
1
SEG44
175
SEG45
174
SEG46
173
SEG47
172
SEG48
171
SEG49
170
SEG50
169
SEG51
168
SEG52
167
SEG53
166
SEG54
165
SEG55
164
SEG56
163
SEG57
162
SEG58
161
SEG59
160
SEG60
159
SEG61
158
SEG62
157
SEG63
156
Type
Description
LCD segment signal output pins
O
13/32
¡ Semiconductor
MSM63188A
Table 2 shows the secondary functions of each pin of the MSM63188A.
Table 2 Pin Descriptions (Secondary Functions)
Function
External
Interrupt
Symbol
Pin
PB.0/INT0
108
PB.1/INT0
107
PB.2/INT0
106
PB.3/INT0
105
an interrupt for each bit.
PC.0/INT1
104
External 1 interrupt input pins.
PC.1/INT1
103
PC.2/INT1
102
PC.3/INT1
101
P8.3/INT4
117
P0.0/INT5
154
External 5 interrupt input pins.
P0.1/INT5
153
The change of input signal level causes an interrupt to occur.
P0.2/INT5
152
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
P0.3/INT5
151
P1.0/INT5
150
P1.1/INT5
149
P1.2/INT5
148
P1.3/INT5
147
Type
Description
External 0 interrupt input pins.
I
I
The change of input signal level causes an interrupt to occur.
The Port B Interrupt Enable register (PBIE) enables or disables
The change of input signal level causes an interrupt to occur.
The Port C Interrupt Enable register (PCIE) enables or disables
an interrupt for each bit.
I
I
External 4 interrupt input pins.
The change of input signal level causes an interrupt to occur.
Enable register (P1IE) enable or disable an interrupt for each bit.
14/32
¡ Semiconductor
MSM63188A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Symbol
Pin
Type
PB.0/TM0CAP
108
I
Timer 0 capture input pin.
PB.1/TM1CAP
107
I
Timer 1 capture input pin.
PB.0/TM0OVF
108
O
Timer 0 overflow flag output pin.
PB.1/TM1OVF
107
O
Timer 1 overflow flag output pin.
PB.2/T02CK
106
I
External clock input pin for timer 0 and timer 2.
PB.3/T13CK
105
I
External clock input pin for timer 1 and timer 3.
PD.0/FRAME
100
O
Frame output pin for LCD driver expansion
Expansion
PD.1/LCLK
99
O
Clock output pin for LCD driver expansion
Oscillation
PD.2/TBCCLK
98
O
Low-speed oscillation clock output pin
Output
PD.3/HSCLK
97
O
High-speed oscillation clock output pin
PC.0/RXD
104
I
Serial port receive data input pin
Function
Capture
Timer
LCD
Description
External
Sync serial port clock input-output pin.
PC.1/TXC
103
I/O
Transmit clock output when this device is used as a master processor.
Serial
Transmit clock input when this device is used as a slave processor.
Port
Sync serial port clock input-output pin.
PC.2/RXC
102
I/O
Receive clock output when this device is used as a master processor.
Receive clock input when this device is used as a slave processor.
PC.3/TXD
101
O
Serial port transmit data output pin.
15/32
¡ Semiconductor
MSM63188A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
External
Memory
Symbol
Pin
P4.0/A0
138
P4.1/A1
137
P4.2/A2
136
P4.3/A3
135
P5.0/A4
132
P5.1/A5
131
P5.2/A6
130
P5.3/A7
129
P6.0/A8
128
P6.1/A9
127
P6.2/A10
126
P6.3/A11
125
P7.0/A12
124
P7.1/A13
123
P7.2/A14
122
P7.3/A15
121
P9.0/D0
116
P9.1/D1
115
P9.2/D2
114
Type
Description
Address output bus for external memory
O
Data bus for external memory
P9.3/D3
113
PA.0/D4
112
PA.1/D5
111
PA.2/D6
110
PA.3/D7
109
P8.0/RD
120
O
Read signal output pin for external memory (negative logic)
P8.1/WR
119
O
Write signal output pin for external memory (negative logic)
I/O
16/32
¡ Semiconductor
MSM63188A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.6
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.9
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +4.2
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +6.8
V
Power Supply Voltage 6
VDD
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 7
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 8
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 9
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 Output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 Output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 Output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 Output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 Output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 7
VOUT7
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 8
VOUT8
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
17/32
¡ Semiconductor
MSM63188A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
0.9 to 2.7
V
VDDI
—
0.9 to 5.5
V
kHz
fXT
Ceramic Oscillation Frequency
fCM
External RC Oscillator Resistance
ROS
—
30 to 35
VDD = 1.2 to 2.7 V
300k to 500k
VDD = 1.5 to 2.7 V
200k to 1M
Hz
VDD = 1.2 to 2.7 V
100 to 300
VDD = 1.5 to 2.7 V
50 to 300
Symbol
Condition
Range
Unit
kW
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Top
—
–20 to +70
°C
VDD
—
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
V
fXT
—
30 to 35
kHz
VDD = 1.8 to 5.5 V
300k to 500k
VDD = 2.2 to 5.5 V
300k to 1M
VDD = 2.7 to 5.5 V
200k to 2M
fCM
ROS
VDD = 1.8 to 5.5 V
100 to 300
VDD = 2.2 to 5.5 V
50 to 300
VDD = 2.7 to 5.5 V
30 to 300
Hz
kW
18/32
¡ Semiconductor
MSM63188A
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
VDD2 Voltage
VDD2 Voltage Temperature Deviation
VDD1 Voltage
VDD3 Voltage
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaMin.
Typ.
Max. Unit suring
Symbol
Condition
Circuit
1/5 bias, 1/4 bias
VDD2
1.7
1.8
1.9
V
(Ta = 25°C)
DVDD2
—
VDD1
1/5 bias, 1/4 bias
Typ.– 0.2 1/2 ¥ VDD2 Typ.+ 0.2
1/5 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
VDD3
1/4 bias (connect
VDD3 and VDD2)
VDD4 Voltage
VDD4
VDD5 Voltage
VDD5
VDDH Voltage
(Backup used)
VDDL Voltage
VDDH
VDDL
Crystal Oscillation Start Voltage
VSTA
Crystal Oscillation Hold Voltage
VHOLD
—
Typ.– 0.2
–4
VDD2
—
Typ.+ 0.2
1/5 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
1/4 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
1/5 bias
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.5
1/4 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
High-speed clock oscillation
stopped
VDD = 1.5 V
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
High-speed clock
oscillation stopped
mV/°C
V
V
V
V
2.8
—
3.0
V
2.0
—
2.7
V
1
0.8
1.3
1.8
V
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
1.2
—
5.5
V
Oscillation start time:
within 5 seconds
1.0
—
—
V
Backup
0.9
—
—
V
Backup not used
1.7
—
—
V
Crystal Oscillation Stop Detect Time
TSTOP
—
0.1
—
5.0
ms
External Crystal Oscillator Capacitance
CG
—
5
—
25
pF
Internal Crystal Oscillator Capacitance
CD
—
20
25
30
pF
—
30
—
pF
External Ceramic Oscillator
Capacitance
Internal RC Oscillator Capacitance
CL0, 1
COS
POR Voltage
VPOR1
Non-POR Voltage
VPOR2
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
—
8
12
16
pF
VDD = 1.5 V
0.0
—
0.4
V
VDD = 3.0 V
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.0
—
3.0
V
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
19/32
¡ Semiconductor
MSM63188A
DC Characteristics (continued)
• When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
5.6
7.0
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
5.6
8.5
Ta = –20 to +70°C —
stopped)
Supply Current 2
IDD2
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
4.5
5.5
—
4.5
7.0
mA
1
Supply Current 3
IDD3
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
—
18
22
mA
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation
(RC oscillation, f = approx. 720 kHz, ROS = 51 kW)
—
700
900
mA
Supply Current 5
IDD5
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
—
800
1000
mA
• When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
2.7
3.0
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
2.7
3.5
stopped)
Supply Current 2
Supply Current 3
Supply Current 4
Supply Current 5
IDD2
IDD3
IDD4
IDD5
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
2.1
2.4
—
2.1
3.0
—
8.5
10.5
f = approx. 800 kHz,
ROS = 51 kW
—
550
800
f = approx. 500 kHz,
ROS = 100 kW
—
390
450
—
1000
1500
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
CPU is in operation at
high-speed oscillation
(RC oscillation)
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
mA
mA
1
mA
mA
20/32
¡ Semiconductor
MSM63188A
DC Characteristics (continued)
Parameter
Output Current 1
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
Symbol
IOH1
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
VDDI = 1.5 V
–2.0
–1.2
–0.2
mA
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
–5.0
–3.0
–1.0
mA
···
(PC.0 to PC.3)
(PD.0 to PD.3)
IOL1
VOL1 = 0.5 V
Output Current 2
(MD, MDB)
Output Current 3
(SEG0 to SEG63)
(COM1 to COM16)
IOH2
(OSC1)
–4.0
–1.5
mA
0.2
1.2
2.0
mA
VDDI = 3.0 V
1.0
3.0
5.0
mA
VDDI = 5.0 V
1.5
4.0
8.0
mA
VDD = 1.5 V
–2.5
–1.3
–0.4
mA
VDD = 3.0 V
–6.0
–4.0
–2.0
mA
VDD = VDDH = 5.0 V
–9.0
–5.5
–3.0
mA
VDD = 1.5 V
0.4
1.3
2.5
mA
VDD = 3.0 V
2.0
4.0
6.0
mA
VDD = VDDH = 5.0 V
3.0
5.5
9.0
mA
—
—
–4
mA
VOL2 = 0.7 V
IOH3
VOH3 = VDD5 – 0.2 V (VDD5 level)
IOHM3
VOHM3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
mA
IOHM3S
VOHM3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
mA
IOMH3
VOMH3 = VDD3 + 0.2 V (VDD3 level)
4
—
—
mA
IOMH3S
VOMH3S = VDD3 – 0.2 V (VDD3 level)
—
—
–4
mA
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
mA
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
mA
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
mA
IOLM3S
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
mA
VOL3 = VSS + 0.2 V (VSS level)
4
—
—
mA
IOH4R
IOL4R
IOH4C
IOL4C
Output Leakage
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
–8.0
IOL2
IOL3
Output Current 4
VOH2 = VDD – 0.7 V
VDDI = 5.0 V
VDDI = 1.5 V
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
–2.5
–1.5
–0.75
mA
(RC oscillation)
VDD = VDDH = 5.0 V
–3.5
–2.0
–1.0
mA
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.75
1.5
2.5
mA
(RC oscillation)
VDD = VDDH = 5.0 V
1.0
2.0
3.5
mA
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–300
–180
–60
(ceramic oscillation)
VDD = VDDH = 5.0 V
–450
–280
–100
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
60
120
300
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
100
200
450
mA
···
IOOH
VOH = VDDI
—
—
0.3
mA
IOOL
VOL = VSS
–0.3
—
—
mA
2
(PD.0 to PD.3)
21/32
¡ Semiconductor
MSM63188A
DC Characteristics (continued)
Parameter
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
Symbol
IIH1
···
IIL1
(PD.0 to PD.3)
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
30
90
180
mA
70
250
600
mA
VDDI = 5.0 V
VDDI = 1.5 V
–30
–10
–2
mA
VDDI = 3.0 V
–180
–90
–30
mA
VDDI = 5.0 V
–600
–250
–70
mA
0.0
—
1.0
mA
VIL1 = VSS (in a high impedance state)
–1.0
—
0.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–200
–110
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
–600
–350
–150
mA
IIH2R
VIH2R = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL2R
VIL2R = VSS (RC oscillation)
–1.0
—
0.0
mA
IIL2C
VDD = VDDH = 3.0 V
0.1
0.5
1.0
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
0.75
1.5
3.0
mA
VDD = VDDH = 3.0 V
–1.0
–0.5
–0.1
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–3.0
–1.5
–0.75
mA
VIH2C = VDDH
VIL2C = VSS
Input Current 3
IIH3
VIH3 = VDD
IIL3
VIL3 = VSS
VDD = 1.5 V
10
50
80
mA
VDD = 3.0 V
150
350
600
mA
VDD = VDDH = 5.0 V
Input Current 4
(TST1, TST2)
mA
VDDI = 3.0 V
IIL1Z
IIH2C
(RESET)
30
2
VIH1 = VDDI (in a high impedance state)
IIL2
10
VDDI = 1.5 V
IIH1Z
Input Current 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
0.5
1.0
2.0
mA
–1.0
—
0.0
mA
50
150
300
mA
VDD = 3.0 V
0.5
1.0
1.5
mA
VDD = VDDH = 5.0 V
1.25
2.5
4.0
mA
–1.0
—
0.0
mA
VDD = 1.5 V
IIH4
IIL4
VIH4 = VDD
VIL4 = VSS
3
22/32
¡ Semiconductor
MSM63188A
DC Characteristics (continued)
Parameter
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
VIH1
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
0.0
—
0.6
V
VDDI = 5.0 V
0.0
—
1.0
V
Input Voltage 2
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
···
VDDI = 3.0 V
(PD.0 to PD.3)
(OSC0)
VIL1
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VDD = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
(PD.0 to PD.3)
VDDI = 5.0 V
0.25
1.0
1.5
V
Hysteresis Width 2
VDD = 1.5 V
0.05
0.1
0.3
V
VIH3
VIL3
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
DVT1
4
···
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
DVT2
CIN
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = VDDH = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
1
···
(PC.0 to PC.3)
(PD.0 to PD.3)
23/32
¡ Semiconductor
MSM63188A
Measuring circuit 1
CB1
CG
Cb12
XT0
CB2
C1
32.768 kHz
Crystal
XT1
C12
C2
q
*1
w
OSC0
OSC1
VSS VDD VDDI VDD1
A
Ca
V
Ca, Cb, Cc, Cd, Ce, Cl, C12
Cb12, Ch
CG
CL0
CL1
Ceramic Resonator
VDD2
VDD3
VDD4
VDD5
VDDH VDDL
Cb
Cc
Cd
Ce
Ch
V
: 0.1 mF
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
V
V
V
Cl
V
V
*1 RC Oscillator
q
ROS
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
A
*2
INPUT
VIL
VSS
OUTPUT
VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
24/32
¡ Semiconductor
MSM63188A
Measuring circuit 3
*4
A
INPUT
OUTPUT
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
*4
INPUT
VIL
VSS
OUTPUT
VDD
VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
25/32
¡ Semiconductor
MSM63188A
AC Characteristics (Serial Interface, Serial Port)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
(1) Synchronous Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
tf
—
—
—
1.0
ms
TXC/RXC Input Rise Time
tr
—
—
—
1.0
ms
TXC/RXC Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
TXC/RXC Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
TXC/RXC Input Cycle Time
tCYC
—
2.0
—
—
ms
tCYC1(O)
CPU in operation state at 32 kHz
—
30.5
—
ms
—
0.5
—
ms
TXC/RXC Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 2.7 V to 5.5 V
TXD Output Delay Time
tDDR
Output load capacitance 10 pF
—
—
0.4
ms
RXD Input Setup Time
tDS
—
0.5
—
—
ms
RXD Input Hold Time
tDH
—
0.8
—
—
ms
Synchronous communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
TXC (PC.1)/
RXC (PC.2)
5 V (VDDI)
tr
0 V (VSS)
tf
tCWH
tCWL
tDDR
tDDR
TXD (PC.3)
5 V (VDDI)
0 V (VSS)
tDS
RXD (PC.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
26/32
¡ Semiconductor
MSM63188A
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transmit Baud Rate
TBRT
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT–TCR
TBRT
TBRT+TCR
s
Receive Baud Rate
RBRT
RBRT = 1/fBRT
RBRT¥0.97
RBRT
RBRT¥1.03
s
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
TBRT
5 V (VDDI)
TXD (PC.3)
0 V (VSS)
RBRT
RXD (PC.0)
5 V (VDDI)
0 V (VSS)
27/32
¡ Semiconductor
MSM63188A
AC Characteristics (External Memory Interface)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Symbol
Condition
Min.
Typ.
Read Cycle Time
Parameter
Max.
Unit
tRC
—
—
RD Output Delay Time
tOE
—
—
61.0
—
ms
—
5.0
ms
Output Valid Time
tOHA
—
External Memory Output Delay Time
tDO
—
—
—
5.0
ms
—
—
5.0
ms
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
RD Output Delay Time
tRC
—
1.0
—
—
ms
tOE
—
—
—
100
ns
Output Valid Time
tOHA
—
—
—
100
ns
External Memory Output Delay Time
tDO
—
—
—
150
ns
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 - P4
(A15 - A0)
Port setup value
Address output
Port setup value
5 V (VDDI)
0 V (VSS)
P8.0
(RD)
tOE
PA, P9
(D7 - D0)
5 V (VDDI)
0 V (VSS)
Port setup value
Input data
tOHA
Port setup value
5 V (VDDI)
0 V (VSS)
tDO
28/32
¡ Semiconductor
MSM63188A
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
—
61.0
—
ms
Address Setup Time
tAS
—
—
30.5
—
ms
Write Time
tW
—
—
15.3
—
ms
Write Recovery Time
tWR
—
—
15.3
—
ms
Data Setup Time
tDS
—
—
45.8
—
ms
Data Hold Time
tDH
—
—
15.3
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
1.0
—
—
ms
Address Setup Time
tAS
—
0.4
—
—
ms
Write Time
tW
—
0.2
—
—
ms
Write Recovery Time
tWR
—
0.2
—
—
ms
Data Setup Time
tDS
—
0.7
—
—
ms
Data Hold Time
tDH
—
0.2
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
P7 - P4
(A15 - A0)
PA, P9
(D7 - D0)
Port setup value
Address output
Port setup value
Output data
tDS
tDH
Port setup value
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
P8.1
(WR)
tAS
tW
tWR
29/32
¡ Semiconductor
MSM63188A
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
LCD
Crystal
32.768 kHz
CG
COM1-16
SEG0-63
XT0
OSC0
ROS
5 to
25 pF
Ch
1.0 mF
1.5 V
XT1
VDDH
OSC1
VDD
Cv 0.1 mF
1.0 mF
Cb12
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
Open
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
0.1 mF
Push SW
Buzzer
CB1
C2
MSM63188A
SW Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
MD
VDDI
MDB
P4-7
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
5.0 V
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
30/32
¡ Semiconductor
MSM63188A
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
LCD
Crystal
32.768 kHz
CG
5 to 25 pF
VDD
COM1-16
CL0 30 pF
SEG0-63
XT0
OSC0
XT1
VDDH
OSC1
Ceramic
Resonator
(Example: 1 MHz)
CL1
30 pF
5.0 V
VDD
Cv 0.1 mF Open
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
CB1
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
C12
0.1 mF
Push SW
Open
Buzzer
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
C2
MSM63188A
SW Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
MD
VDDI
MDB
P4-7
VDD
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
31/32
¡ Semiconductor
MSM63188A
PACKAGE DIMENSIONS
(Unit : mm)
LQFP176-P-2424-0.50-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
32/32
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan