OKI MSM6896

E2U0022-28-81
¡ Semiconductor
MSM6895/6896
¡ Semiconductor
This version:
Aug. 1998
MSM6895/6896
Previous version: Nov. 1996
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM6895/MSM6896, developed especially for low-power and multi-function applications
in ISDN telephone terminals, are single +5 V power supply CODEC LSI devices. The devices
consist of the analog speech paths directly connectable to a handset, the calling circuit directly
connectable to a piezosounder, the push-button key scanning interface between push buttons
and control processors, the dial tone generator, the B-channel interface, the CODEC, and the
processor interface. The functions can be controlled via the 8-bit data bus.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
Power ON Mode
: 20 mW Typ. 53 mW Max.
CODEC Power Down Mode
: 10 mW Typ. 21 mW Max.
• In compliance with ITU-T’s companding law
m-law
: MSM6895
A-law
: MSM6896
• Transmission clocks
Continuous CLK
: 64, 128, 256 kHz
Burst CLK
: 192, 384, 768, 1536, 2048 kHz
• Built-in PLL
• Built-in Reference Voltage Supply
• Ringing Tone
: Controlled by processor, 9 modes
• Ringing Tone Combination
: Controlled by processor, 6 modes
• Information Tone
: Controlled by processor, 9 modes
• Built-in PB Tone Generator
• B-Channel Selectable
• General Latch Output for Speech path Control
: 4 bits
• Watchdog Timer
: 500 ms
• Key Scanning I/O
Output
: 5 bits
Input
: 8 bits
• Direct Connection to Handset
• Built-in Preamplifier for Loudspeaker
• Handfree Interface
• Digital and Analog Interface for the phone-conference speech paths
• Package:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6895GS-BK)
(Product name : MSM6896GS-BK)
1/43
¡ Semiconductor
MSM6895/6896
BLOCK DIAGRAM
TMX1I
M
TPBI MLDY
T2O
TMX2I
T1O
CAI
TEST
AIN
SW
&
MIX
TPAI
CK1536
TEST
CHANNEL SELECTOR
TPAO
CODEC
CAO
AOUT
R1I
PLL
HANDSET
R2I
B1
B2T
B2R
B2
BR1
BT1
BR2
BT2
CK8
CK64
SW
&
MIX
RPO
B1T
B1R
F-TONE
GEN
8K
64K
SW0
SW1
R-TONE
GEN
RMI
RMO1
+
SW
CE
–
SPO
SP
WR
RD
DTMF TONE
GEN
S-TONE
GEN
SW
&
MIX
RESET
MPU INTF.
RMO0
8BIT
Data Bus
AD0
AD1
INTT
LATCH
LA ~
LD
SA0
4BIT
LOSS
SW
CONT.
SA1
TIME
LML
BUZZER
VSG
VA VD VAG VDG
KEY INTF.
SCANNING
OUTPUT
SGGEN
KEY DATA INPUT
PO0 ~
VSGC PO4
0
1
2
3
4
0
1
2
3
4 5
PI0 to
PI7
6 7
SWITCH
HOOK
PUSH-BOTTON SWITCH
2/43
¡ Semiconductor
MSM6895/6896
65 AD1
66 WR
67 RD
68 CE
69 B1T
70 B2T
71 B1R
72 B2R
73 BT1
74 BT2
75 BR1
76 BR2
77 RESET
78 TIME
79 LML
80 LA
PIN CONFIGURATION (TOP VIEW)
LB 1
64 VD
LC 2
63 AD0
LD 3
62 DB7
SW0 4
61 DB6
SW1 5
60 DB5
VDG 6
59 DB4
VAG 7
58 DB3
SA0 8
57 DB2
SA1 9
56 DB1
NC 10
55 DB0
RM1 11
54 INTT
NC 20
45 PO4
TMX2I 21
44 PO3
MLDY 22
43 PO2
TPBI 23
42 PO1
TMX1I 24
41 PO0
LOSS 40
46 PI0
CK8 39
NC 19
CK64 38
47 PI1
CK1536 37
R1I 18
TEST 36
48 PI2
CA0 35
R2I 17
VSGC 34
49 PI3
CAI 33
RPO 16
VA 32
50 PI4
NC 31
SPO 15
NC 30
51 PI5
T2O 29
RMO1 14
T1O 28
52 PI6
TPAO 27
RMO0 13
VSG 26
53 PI7
TPAI 25
NC 12
NC : No connect pin
80-Pin Plastic QFP
3/43
¡ Semiconductor
MSM6895/6896
PIN DESCRIPTION
Pin
Symbol
Type
Description
Pin
Symbol
Type
Description
NC
1
LB
DO
Data Latch Output B
31
—
—
2
LC
DO
Data Latch Output C
32
VA
—
+5 V Analog Power Supply
3
LD
DO
Data Latch Output D
33
CAI
AI
Analog Signal Input to CODEC
4
SW0
DI
Sounder Tone Select (1)
34
VSGC
AO
Bypass Capacitor for Signal Ground
5
SW1
DI
Sounder Tone Select (2)
35
CAO
AO
Analog Signal Output from CODEC
6
VDG
—
Digital Ground
36
TEST
DI
Control Input for Test
7
VAG
—
Analog Ground
37
CK1536
DI
Clock Input for Test
8
SA0
DO
Sounder Output (+)
38
CK64
DI
Transmission Colck Input
9
SA1
DO
Sounder Output (–)
39
CK8
DI
Frame Synchronous Clock Input
Howler Tone Control Signal
10
—
—
NC
40
LOSS
DO
11
RMI
AI
Receive Main Amp Input
41
PO0
DO
Key Scanning Signal Output (0)
12
—
—
NC
42
PO1
DO
Key Scanning Signal Output (1)
13
RMO0
AO
Receive MainAmp Output (+)
43
PO2
DO
Key Scanning Signal Output (2)
14
RMO1
AO
Receive MainAmp Output (–)
44
PO3
DO
Key Scanning Signal Output (3)
15
SPO
AO
Speaker Pre-Amp Output
45
PO4
DO
Key Scanning Signal Output (4)
16
RPO
AO
Receive Pre-Amp Output
46
PI0
DI
Key Scanned Data Input (0)
17
R2I
AI
Receive Addition Signal Input
47
PI1
DI
Key Scanned Data Input (1)
18
R1I
AI
Receive Signal Input
48
PI2
DI
Key Scanned Data Input (2)
19
—
—
NC
49
PI3
DI
Key Scanned Data Input (3)
20
—
—
NC
50
PI4
DI
Key Scanned Data Input (4)
21
TMX2I
AI
Transmit Addtion Signal Input (2)
51
PI5
DI
Key Scanned Data Input (5)
22
MLDY
AI
Hold Tone Input
52
PI6
DI
Key Scanned Data Input (6)
Key Scanned Data Input (7)
23
TPBI
AI
Transmit Pre-Amp (B) Input
53
PI7
DI
24
TMX1I
AI
Transmit Addtion Signal Input (1)
54
INTT
DO
Interrupt Output
25
TPAI
AI
Transmit Pre-Amp (A) Input
55
DB0
I/O
Data Bus (0)
26
VSG
AO
Signal Ground
56
DB1
I/O
Data Bus (1)
27
TPAO
AO
Transmit Pre-Amp (A) Output
57
DB2
I/O
Data Bus (2)
28
T1O
AO
Transmit Signal Output (1)
58
DB3
I/O
Data Bus (3)
29
T2O
AO
Transmit Signal Output (2)
59
DB4
I/O
Data Bus (4)
30
—
—
NC
60
DB5
I/O
Data Bus (5)
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¡ Semiconductor
MSM6895/6896
PIN DESCRIPTION (Continued)
Pin
Symbol
Type
61
DB6
I/O
62
DB7
I/O
63
AD0
64
VD
65
AD1
66
WR
67
68
Description
Pin
Symbol
Type
Description
Data Bus (6)
71
B1R
DI
B1 Channel Recive Input
Data Bus (7)
72
B2R
DI
B2 Channel Recive Input
DI
Address Data (0)
73
BT1
DI
B Channel Selector Transmit Data (1)
—
+5 V Digital Power Supply
74
BT2
DI
B Channel Selector Transmit Data (2)
DI
Address Data Input (1)
75
BR1
DO
B Channel Selector Receive Data (1)
DI
Write Signal Input
76
BR2
DO
B Channel Selector Receive Data (2)
RD
DI
Read Signal Input
77
RESET
DI
Reset Input
CE
DI
Chip Enable
78
TIME
DO
Timer Output
69
B1T
DO
B1 Channel Transmit Output
79
LML
DO
Hold Tone Control Output
70
B2T
DO
B2 Channel Transmit Output
80
LA
DO
Data Latch Output (A)
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¡ Semiconductor
MSM6895/6896
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB, LC, LD
General latch outputs for external control.
Statuses of these outputs are controlled via the processor interface. Refer to the description of the
control data for details.
SW0, SW1
External control signal inputs for setting the tone combination of the ringing tone.
When the external control for setting the tone combination is selected, the tone combination is
set by these pins.
Wambling Cycle
f1
f2
Tone combination 1
16 Hz
1000 Hz
1333 Hz
1
Tone combination 2
16 Hz
800 Hz
1000 Hz
0
Tone combination 3
8 Hz
800 Hz
1000 Hz
1
Tone combination 1
16 Hz
1000 Hz
1333 Hz
SW0
SW1
0
0
0
1
1
1 / f1
1 / f2
Wambling Cycle Time
VDG
Digital Ground.
VAG
Analog Ground.
6/43
¡ Semiconductor
MSM6895/6896
SA0, SA1
Sounder (ringing tone) driving outputs.
The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily
configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the
ringing tone volume is selectable from four levels and one of six tone combinations is selectable.
Initially, the ringing tone volume is set at a maximum and the tone combination is set externally.
If these pins are used with no-load, tone volume cannot be controlled.
When tone volume control is required, a load resistor must be connected between SA0 and SA1.
RMI, RMO0, RMO1
Receive main amplifier input and outputs.
RMI is the main amplifier input and RMO0 and RMO1 are the main amplifier outputs. The
output signal on RMO1 is inverted against RMO0, so the earphone of a piezo electric-type
handset is directly connected between RMO0 and RMO1. The RMI input pin is connected to the
receive preamplifier output pin (RPO).
If the adjusting of receive path frequency characteristics is required, insert the following circuit
for adjustment. During initial setting, the speech path from RMI to RMO0 and RMO1 is
disconnected and the output of RMO0 and RMO1 is at the VSG level (VA/2). The speech path
is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO
RMI
VSG
C2
R1
C1
R2
SPO
Output of preamplifier for speaker.
Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker.
During initial setting, SPO is in a non-signal state (VSG level), and a speech signal, RTONE0,
RTONE1, FTONE, hold acknowledge tone, and PB signal acknowledge tone are output through
processor control.
7/43
¡ Semiconductor
MSM6895/6896
R1I, R2I, RPO
Receive preamplifier inputs and output.
R1I and R2I are for the inputs and RPO is for the output of the receive preamplifier. Normally,
R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is
used as the mixing signal input pin.
During initial setting, the RPO output is in non-signal state (VSG level), and speech signal,
RTONE1, RTONE2, FTONE, PB acknowledge tone, and side tone signal are output through
processor control. And if the three-party speech function is required, the R2I pin is connected to
the analog output of the other CODEC.
MLDY
Hold tone signal input.
This pin is connected to the output of external melody IC. Through processor control, the signal
applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from
the SPO output pin as a hold acknowledge tone on the receive path.
TPBI
Transmit signal input.
When the handset is used, TPBI is connected to the transmit preamplifier output pin (TPAO). If
adjustment of frequency characteristics on the transmit path is required, insert a circuit for
adjustment of characteristic between TPAO and TPBI. Through processor control, the signal
applied to this pin is output via the T1O and T2O pins on the transmit path output and its side
tone via the RPO pin.
A circuit example for adjustment of frequency characteristics
TPAO
TPBI
R3
C3
VSG
R4
C4
TMX1I, TMX2I
Transmit addition signal inputs.
Through processor control, the input signals to TMX1I and TMX2I are added to the transmit
signal and are output to T1O and T2O respectively.
8/43
¡ Semiconductor
MSM6895/6896
TPAI, TPAO
The transmit preamplifier input and output.
TPAI is the input and TPAO is the output. Connect TPAI to the microphone of handset via an ACcoupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit
path from TPAI to TPAO is always established regardless of processor control.
VSG
Signal ground level output.
The output level is equal to a half of the power supply voltage.
VSGC
Bypass capacitor connecting pin for signal ground level.
Insert a 0.1 mF capacitor with good higher frequency characteristic, between VSGC and VAG.
VA, VD
+5 V power supply.
VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V
analog path of the system.
CAI
CODEC analog output.
Connect CAI to T1O.
CAO
CODEC analog output.
Connect CAO to R1I via an AC-Coupling capacitor.
9/43
¡ Semiconductor
MSM6895/6896
TEST, CK1536
External master clock inputs.
Since the MSM6895 and MSM6896 contain PLL internally, the external clock signal is eliminated.
But the device can operate with the external clock through these pins.
When these pins are not used, leave these pins open or at 0 V.
Mode
Internal PLL
External master clock
TEST pin
CK1536 pin
0V
open or 0 V
Digital "1"
Input the signal of 1536 kHz
When the external clock is used, the CK1536 signal is required to be synchronized in phase with
the CK8 signal.
CK64
CODEC PCM data input and output shift clock input.
When the continuous clock is set, the frequency is one of 64 kHz, 128 kHz, and 256 kHz. When
the burst clock is used, one of 192, 384, 768, 1536, and 2048 kHz is available. If the BCLOCK signal
is not applied, PLL is out of synchronization and goes into the self-running mode.
CK8
Synchronous signal input.
CODEC PCM data is sent out sequencially from MSB at the rising edge of the CK64 signal in
synchronization with the rise of the synchronous signal. PCM data should be entered from MSB
in synchronization with the rise of the synchronous signal. PCM data is shifted in at the falling
edge of the CK64 signal.
Since the CK8 signal is used for a trigger signal for PLL and for a clock signal to the tone generator,
if this signal is not applied, not only any tone can not be output, but also PLL goes out of
synchronization and goes into self-running mode. This signal has to be synchronous with the
CK64 signal and its frequency must be within 8 kHz ±50 ppm to ensure the CODEC AC
characteristics (mainly frequency characteristics).
LOSS
Signal output for controlling the external circuits.
When the howler tone of sounder is selected through processor control, the output is in a digital
"1".
Initially, this output is set to a digital "0".
10/43
¡ Semiconductor
MSM6895/6896
PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
Key scanning outputs.
These output pins need external pull-up resistors because of their open- drain circuits. Through
processor control, these outputs can be set open or to digital "0". Initially, these outputs are set
at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7
Key scanning inputs.
In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7).
INTT
Interrupt signal output to the processor.
INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control
signal from the processor. INTT does not output any signal while no CK8 signal is input.
Interrupt release signal
from processor
t < 8 ms
8 ms < t < 16 ms
t < 8 ms
INTT output
8 ms
16 ms
8 ms
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7
Data bus inputs and outputs.
11/43
¡ Semiconductor
MSM6895/6896
AD0, AD1
Address data inputs for the internal control registers.
Addressing of the internal control registers is executed by AD0 and AD1 and sub address data,
DB7 and DB6.
Write
Read
AD1
AD0
DB7
DB6
Function
0
0
0
0
Sounder Control
0
0
0
1
Control of function key acknowledge tone
0
0
1
0
PB tone control
0
0
1
1
0
1
—
—
Control of channel selector
1
0
—
—
Key scanning output control, interrupt release control
1
1
0
0
Volume control and tone combination control of sounder
1
1
0
1
CODEC power down control
1
1
1
0
1
1
1
1
Frequency control of howler tone
1
0
—
—
Read of the key scanning data
Control of the internal control latch and the general-purpose latch,
Reset control of the watch dog timer.
Level control of transmit path, PB tone, and Hold tone, Gain control of
receive path
WR
Write signal for internal control registers.
Data on the data bus is written into the registers at the rising edge of WR under the condition of
digital "0" of CE (Chip Enable). While CE is in digital "1" state, WR becomes invalid. The Write
cycle is a minimum of 2 ms, but if the CK64 and CK8 signals are silent, the write cycle requires
a minimum of 50 ms.
A minimum of 2 ms specified as the write cycle is valid 10 ms after CK64 and CK8 signals are input.
RD
Read signal input to read PI0 to PI7 out of the processor.
When CE and RD are in digital "0" state, the digital values on PI0 to PI7 are output onto the data
buses DB0 to DB7. While CE is in digital "1" state, the RD signal becomes invalid.
12/43
¡ Semiconductor
MSM6895/6896
CE
Chip Enable signal input.
When CE is in digital "0" state, WR and RD are valid.
B1T, B2T, B1R, B2R
B channel interface inputs and outputs.
B1T and B2T are outputs, and B1R and B2R are inputs. Through channel control by the processor,
various data paths are set. The CODEC input and output signals are input and output via these
pins.
Initially the B1T and B2T outputs are fixed in a digital "1", and the B1R and B2R inputs are
neglected.
BR1, BR2, BT1, BT2
External digital inputs and outputs to the B-channel.
BR1 and BR2 are outputs, and BT1 and BT2 are inputs. Through channel control by processor,
the digital paths are set between these input and output pins and the B channel.
These signals are applied to another CODEC interface of three-party the speech path and to the
interface of 64 kbps at the rate adaptor circuit.
Initially the BR1 and BR2 outputs are fixed in a digital "1", and the BT1 and BT2 inputs are
neglected.
RESET
Reset signal input.
Digital "0" input to RESET makes all of internal control registers to be initialized. When powered
on, this RESET signal should be input for initializing the system.
TIME
Watchdog timer output.
When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal
is continuously output. When RESET is at digital "0", this timer is reset. And, in about 500 ms after
RESET goes to digital "1", the first timer output signal is issued and then the timer signal is output
at intervals of a 500 ms. If the CK8 signal is not input, the TIME signal is not output.
LML
Control signal output for external hold tone generator.
LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold
acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0"
state.
13/43
¡ Semiconductor
MSM6895/6896
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Symbol
Condition
Rating
Unit
VDD
VAG, VDG = 0 V
0 to 7
V
Analog Input Voltage
VAIN
VAG, VDG = 0 V
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
VAG, VDG = 0 V
–0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VD
VA, VD (Voltage must be fixed)
4.75
5.0
5.25
V
Operating Temperature
Ta
—
–10
+25
+70
°C
Input High Voltage
VIH
All Digital Input Pins
2.2
—
VDD
V
Input Low Voltage
VIL
All Digital Input Pins
0
—
0.8
V
Digital Input Rise Time
tIr
All Digital Input Pins
—
—
50
ns
Digital Input Fall Time
tIf
All Digital Input Pins
—
—
50
ns
Digital Output Load
RDL
CDL
10
—
—
kW
—
—
100
pF
Typ.
Max.
Unit
—
kHz
PO0 to PO4 Output
Recommended Operating Conditions (CODEC Digital Interface)
Parameter
Symbol
Condition
Min.
64
Clock Frequency
FC
CK64
—
128
256
Sync Pulse Frequency
FS
CK8
—
8.0
—
kHz
Clock Duty Ratio
DC
CK64
40
50
60
%
tXS
CK64ÆCK8
See Fig.1
—
—
100
ns
tSX
CK8ÆCK64
See Fig.1
—
—
100
ns
tWS
—
1 CK64
—
100
ms
Data Setup Time
tDS
B1R, B2R
100
—
—
ns
Data Hold Time
tDH
B1R, B2R
100
—
—
ns
Allowable Jitter Width
—
CK8
—
—
500
ns
Sync Pulse Setting Time
Sync Pulse Width
14/43
¡ Semiconductor
MSM6895/6896
Recommended Operating Conditions (Processor Digital Interface)
Min.
Typ.
Max.
Unit
Write Pulse Period
Parameter
PW
WR
2000
—
—
ns
Write Pulse Width
TW
WR
100
—
—
ns
Read Pulse Width
TR
RD
200
—
—
ns
Address Data
Setup Time
tAW1
AD0, AD1ÆWR
10
—
—
ns
tAR1
AD0, AD1ÆRD
80
—
—
ns
Address Data
Hold Time
tAW2
WRÆAD0, AD1
50
—
—
ns
tAR2
RDÆAD0, AD1
10
—
—
ns
tCW1
CEÆWR
10
—
—
ns
tCR1
CEÆRD
80
—
—
ns
tCW2
WRÆCE
50
—
—
ns
tCR2
RDÆCE
10
—
—
ns
CE Setup Time
CE Hold Time
Symbol
Condition
See Fig.2
Data Setup Time
tDW1
DB0 to 7ÆWR
110
—
—
ns
Data Hold Time
tDW2
WRÆDB0 to 7
20
—
—
ns
Reset Pulse Width
tWRES
RESET
100
—
—
ns
Min.
Typ.
Max.
Unit
TPAI
—
—
0.24
TPBI
—
—
0.31
—
—
2.40
—
—
1.90
—
—
1.20
RMI
—
—
0.51
CAI
—
—
2.40
20
—
—
RMO0, RMO1
3
—
—
TPAO, T1O, T2O,
RPO, SPO, CAO
—
—
100
pF
RMO0, RMO1
—
—
55
nF
TPAI, TPBI, RMI
–10
—
+10
MLDYI, TMX1I, TMX2I
–50
—
+50
R1I, R2I
–25
—
+25
CAI
–100
—
+100
Recommend Operating Conditions (Analog Interface)
Parameter
Symbol
Condition
TMX1I, TMX2I
(Transmit Gain: Typ.)
Analog Input Voltage
VAIN
MLDYI
(Transmit Gain: Typ.)
R1I, R2I
(Transmit Gain: Typ.)
TPAO, T1O, T2O,
Analog Load Resistance
Analog Load Capacitance
Allowable Analog
Input Offset Voltage
RAL
CAL
Voff
RPO, SPO, CAO
VPP
kW
mV
15/43
¡ Semiconductor
MSM6895/6896
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Power Supply Current
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1
Operating Mode (No Signal, Sounder OFF)
—
3.9
10.0
mA
IDD2
CODEC Receive Power Down
—
3.3
8.0
mA
IDD3
CODEC Transmit Power Down
—
2.8
7.0
mA
IDD4
CODEC Transmit/Receive Power Down
—
2.2
4.0
mA
Input High Voltage
VIH
—
2.2
—
VDD
V
Input Low Voltage
VIL
—
0.0
—
0.8
V
High Input Leakage
Current
IIH
—
—
—
2.0
mA
Low Input Leakage
Current
IIL
—
—
—
0.5
mA
Digital Output High
Voltage
VOH
IOH = 0.4 mA
2.4
—
VDD
IOH = 1 mA
3.8
—
VDD
Digital Output Low
Voltage
VOL
IOL = –1.6 mA
0.0
—
0.4
V
IO
—
—
—
10
mA
Analog Output Offset
Voltage
Voff
TPAO, T1O, T2O,
CAO, RPO, RMO1, RMO2, SPO
–100
—
+100
mV
Input Capacitance
CIN
—
—
5
—
pF
TPAI, TPBI, MLDYI, RMI
—
10
—
MW
Analog Input Resistance
RIN
TMX1I, TMX2I, R1I, R2I
10
—
—
kW
CAI (fin : < 4 kHz)
—
1
—
MW
—
—
VA/2
–0.05
VA/2
VA/2
+0.05
V
ISGF
FORCE Current
1.0
1.5
—
ISGS
SINK Current
0.3
0.5
—
Digital Output Leakage
Current
VSG Voltage
VSG Drive Current
V
mA
16/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 1 (CODEC)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Transmit Frequency
Response
Receive Frequency
Response
Transmit Signal to
Distortion Ratio
Receive Signal to
Distortion Ratio
Transmit Gain
Tracking
Receive Gain
Tracking
Notes:
Symbol Freq. Level
(Hz) (dBm0)
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Loss R3
Loss R4
Loss R5
SD T1
SD T2
SD T3
60
300
1020
2020
3000
3400
300
1020
2020
3000
3400
1020
Condition
20
–0.15
27
+0.07
Reference
–0.03
+0.06
0.38
–0.03
Reference
–0.02
+0.15
0.56
43.0
41.0
38.0
—
+0.20
31.0
—
26.5
—
43.0
41.0
40.0
—
—
—
34.0
—
31.0
—
+0.01
Reference
+0.13
+0.32
+0.64
0.0
Reference
–0.06
–0.20
–0.27
+0.3
0
–0.15
–0.15
0.0
35
35
35
29
28
24
23
37
37
37
31
30
26
25
–0.3
3
0
–30
*1
*2
SD T5
–45
*2
SD R1
SD R2
SD R3
3
0
–30
*1
SD R4
–40
*2
SD R5
–45
*2
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
3
–10
–40
–50
–55
3
–10
–40
–50
–55
1020
Max.
–0.15
–0.15
0.0
–0.15
–40
1020
Typ.
0
SD T4
1020
Min.
–0.3
–0.6
–1.5
–0.2
–0.2
–0.4
–0.8
Unit
+0.20
+0.20
0.80
+0.20
dB
+0.20
+0.20
0.80
—
—
—
dB
dB
dB
+0.3
+0.6
+1.5
+0.2
dB
+0.2
+0.4
+0.8
dB
*1 Psophometric filter is used
*2 Upper is specified for the MSM6895, lower for the MSM6896
17/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 1 (CODEC) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Symbol Freq. Level
(Hz) (dBm0)
Absolute Delay Time
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
Discrimination
Out-of-band Signal
Spurious
Intermodulation Distortion
Power Supply Noise
Rejection Ratio
Notes:
Min.
Typ.
Max.
—
–73.5
–71
–70
–69
—
–77.8
–74
Transmit CODEC
0.5671
0.6007
0.6363
Receive CODEC
0.5671
0.6007
0.6363
A to A
CK64 = 64 kHz
—
0.58
0.60
Transmit Æ Receive
—
—
—
—
—
—
—
—
—
—
66
0.19
0.12
0.02
0.05
0.08
0.0
0.0
0.0
0.09
0.12
86
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Receive Æ Transmit
70
78
—
Nidle T
—
—
AIN = SG
*1
Nidle R
—
—
*1
*3
1020
0
Td
1020
0
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
tgd R2
tgd R3
tgd R4
tgd R5
CR T
500
600
1000
2600
2800
500
600
1000
2600
2800
Idle Channel Noise
Absolute Amplitude
Condition
AV T
AV R
*2
Unit
dBmOp
0
*4
0
*4
Vrms
ms
ms
ms
dB
1020
0
DIS
4.6 kHz to
72 kHz
–25
0 to 4000 Hz
30
32.0
—
dB
S
300 to
3400
0
4.6 kHz to 100 kHz
—
–37.5
–35
dBmO
IMD
fa = 470
fb = 320
–4
2fa–fb
—
–52
–35
dBmO
0 to 50
kHz
100
mVpp
*5
—
30
—
dB
CR R
PSR T
PSR R
*1 Psophometric filter is used
*2 Upper is specified for the MSM6895, lower for the MSM6896
*3 PCM data for MSM6895: All "1"
PCM data for MSM6896: "11010101"
*4 Minimum value of the group delay distortion
*5 The measurement under idle channel noise
18/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 2 (Transmit Path)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Symbol
Freq.
(Hz)
Level
(dBV)
Pre-Amp Gain
GTPA
1020
–24.4
Transmit Path 1 Gain
GTPB1
Transmit Path 2 Gain
GTPB2
1020
–22.1
Transmit Addition Signal 1 Gain
GTMX1
Transmit Addition Signal 2 Gain
GTMX2
1020
–4.4
VPBT1
—
—
T1O
VPBT2
—
—
T2O
—
—
Parameter
Condition
Min.
Typ. Max.
TPAI-TPAO
18.0
20.0
22.0
dB
TPBI-T1O
15.7
17.7
19.7
dB
TPBI-T2O
15.7
17.7
19.7
dB
TMX1I-T1O
–2.0
0.0
+2.0
dB
TMX1I-T2O
–2.0
0.0
+2.0
dB
–17.4 –15.4 –13.4
dBV
–17.4 –15.4 –13.4
dBV
– 3 dB
–5.0
–3.0
–1.0
dB
– 6 dB
–8.0
–6.0
–4.0
dB
–0.9
—
+0.9
%
dB
In-Channel PB Signal Output Level
In-Channel PB Signal Output
Level Setting
In-Channel PB Signal
Frequency Deviation
In-Channel PB Signal Distortion
Set at
typical gain
typical
setting
GPBT2
DfPBT
—
—
T1O, T2O
THDPBT
—
—
In-Band Distortion
—
–35
–30
MLDYI-T1O Set at
–4.0
–2.0
0.0
Hold Tone Path Gain
1020
–22.4
GPAT2
RG1 PAT
Hold Tone Path Gain Setting
1020
–22.4
Ni TPA
—
—
Ni TPB
—
—
VOT
—
—
Idle Channel Noise
dB
typical
MLDYI-T2O gain
–4.0
–2.0
0.0
For
–3 dB
–5.0
–3.0
–1.0
dB
–6 dB
–8.0
–6.0
–4.0
dB
—
–93
—
dBV
—
–91
—
dBV
2.4
—
—
VPP
typical
setting
RG2 PAT
Note:
typical gain
For
GPBT1
GPAT1
Maximum Output Voltage Swing
Set at
Unit
TPAI: 510 W at termination
Meature at TPAO *6
T1O, T2O
*6
TPAO, T1O,
T2O, RL = 20 kW
*6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted
19/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 3 (Receive Path)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Receive Main Amp. Gain
Receive Main Amp.
Output Gain Difference
Receive Main Amp.
Output Phase Difference
Receive Signal Path Gain
Symbol
GRMO0
GRMO1
Freq.
(Hz)
1020
Level
(dBV)
Receive Addition Signal Path
Gain Setting
13.2
15.3
17.3
dB
RMI-RMO1
13.2
15.3
17.3
dB
DGRMO
1020
–19.4
RMO0/RMO1
—
–0.01
—
dB
DPRMO
1020
–19.4
RMO0/RMO1
—
–179.6
—
deg
GRPA
1020
–14.4
R1I-RPO
–8.0
–6.0
–4.0
dB
1.0
3.0
5.0
RG RPA2
1020
–23.4
GRPB
1020
–14.4
1020
–14.4
RG RPB1
RG RPB2
RG RPB3
Set at
typical
For
+3 dB
typical
+6 dB
4.0
6.0
8.0
setting
+9 dB
7.0
9.0
11.0
–8.0
–6.0
–4.0
Set at
R2I-RPO
typical
For
+3 dB
1.0
3.0
5.0
typical
+6 dB
4.0
6.0
8.0
setting
+9 dB
7.0
9.0
11.0
–8.0
–6.0
–4.0
GSP
1020
–8.0
–6.0
–4.0
–3.0
–4.4
R2I-SPO
Hold Acknowledge Tone Path Gain GPAS
PB Acknowledge Tone Output Level
PB Acknowledge Tone Frequency
Difference
PB Acknowledge Tone Distortion
Side Tone Path Gain
Idle Channel Noise
VPBRP
1020
–7.4
Set at
typical
Set at
typical
dB
dB
dB
dB
MLDYI-SPO
–5.0
–1.0
dB
RPO
–32.1 –30.1 –28.1
dBV
SPO
–30.2 –28.2 –26.2
dBV
—
—
DfPBR
—
—
RPO, SPO
–0.9
—
+0.9
%
THD PBR
—
—
RPO, SPO
—
–35
–30
dB
TPBI-RPO
VPBRP
GSIDE
1020
–21.4
8.9
10.9
12.9
dB
Ni RPO
—
—
RPO
*6
—
–86
—
dBV
Ni SPO
—
—
SPO
*6
—
–86
—
dBV
—
–95
—
dBV
Ni RMO
Note:
Unit
RMI-RMO0
R1I-SPO
Speaker Preamp. Gain
Typ. Max.
–19.4
RG RPA3
Receive Addition Signal Path Gain
Min.
–19.4
RG RPA1
Receive Signal Path Gain Setting
Condition
—
—
RMI, VSG
RMO0, RMO1
*6
*6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted
20/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 3 (Receive Path) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Symbol
Freq.
(Hz)
Level
(dBV)
VOR
—
—
VOM
—
—
RTONE0 Output Amplitude
*7 VRT0
—
—
RPO
RTONE1 Output Amplitude
*8 VRT1
—
—
RPO
132.0 157.0 187.0 mVPP
RPO
135.5 161.0 191.5
SPO
159.0 189.0 224.6
Parameter
Maximum Output Amplitude
FTONE Output Amplitude
Notes:
VFTRP
VFTSP
—
—
Condition
RPO, SPO
RL = 20 kW
RMO0, RMO1
RL = 3 kW +55 nF
Min.
Typ. Max.
Unit
2.4
—
—
VPP
3.0
—
—
VPP
77.2
91.7
109.0 mVPP
mVPP
*7 DT, PDT, SDT, CRBT, IIT
*8 RBT, DT, T250
21/43
¡ Semiconductor
MSM6895/6896
AC Characteristics 4 (Ringing Tone Output Circuit)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Calling Tone Output Amplitude *9
Symbol
Freq.
(Hz)
Level
(dBV)
Note:
Min.
Typ. Max.
VST1
SA0-
Volume 1 3.25
4.0
—
VST2
SA1
Volume 2 0.73
1.28
1.98
730 W Volume 3 0.25
0.47
0.65
Volume 4 0.13
0.28
0.45
3.25
4.0
—
VST3
—
—
—
—
VST4
Howler Tone Output Amplitude
Condition
VHOW
to
VDG
Unit
VPP
VPP
*9. IR-1, IR-2, SIR-1, SIR-2, CR, T1K, HR, SPT
Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Digital Output (Latch) Delay Time
Symbol
Condition
tPDLA WRÆLA, LB, LC, LD, LML, LOSS
WRÆPO0, PO1, PO2, PO3, PO4
key Scanning Output Delay Time
tPDSCN
Digital Output (Data) Delay Time
tPDDATA RDÆDB0 to DB7
Digital Path Delay Time
tPDPATH
CODEC Data Output Delay Time
tPDCOD CK64ÆB1T, B2T
Pull-up resistor : 10 kW
BT1ÆBR1, BR2
BT2ÆBR1, BR2
Min.
Typ. Max.
Unit
0.5
—
1.9
ms
0.5
—
1.9
ms
20
52
150
ns
20
52
150
ns
20
50
100
ns
22/43
¡ Semiconductor
MSM6895/6896
TIMING DIAGRAM
1
CK64
tSX
2
3
4
5
6
7
8
tXS
CK8
tWS
B1T or
B2T
tpd cod
MSB
B2
B3
tDS
B1R or
B2R
MSB
B4
B5
B6
B7
B8
tDH
B2
B3
B4
B5
B6
B7
B8
Figure 1 CODEC Timing
A0, A1
tAW1
tAW2
tAR1
tAR2
tCW1
tCW2
tCR1
tCR2
CE
WR
TW
TR
RD
tDW1 tDW2
tPDDATA
tPDDATA
DB0 to DB7
PO0 to PO4
tPDSCN
tPDLA
Latch Output
Figure 2 Processor Interface Timing
23/43
Control Data Description
Sounder control
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Output Tone
Frequency
Make/Break Timing *6
(Hz)
Make (Sec) Break1 (Sec) Break2 (Sec)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
PDC
0
0
0
0
SPT
1
*1
0
0
0
1
IR-1
Wamble Tone
0
0
1
0
IR-2
Wamble Tone
0
0
1
1
SIR-1
Wamble Tone
0.25
0
1
0
0
CR
Wamble Tone
Continuous
0
1
0
1
HOW
800 or
Continuous
*2
Wamble Tone
0
24/43
*2.
*3.
0.125
•
Tone Output:
1
2
—
SA0, SA1
0.5
0.5
—
0.25
2.25
0.125
0
1
1
0
SIR-2
Wamble Tone
0.5
1
—
0
1
1
1
T1K
1
0.25
0.25
—
1
0
0
0
HR
1
0.125
0.125
—
1
0
0
0
DT
400
Continuous
1
0
1
0
SDT
400
0.125
0.125
—
Tone Output:
1
0
1
1
RBT
400/16
1
2
—
1
1
0
0
BT
400
0.5
0.5
—
RPO, Refer to Table 2
and 4.
1
1
0
1
PDT
400
0.25
0.25
—
1
1
1
0
CRBT
•
—
X
X
X
X
400/16
0.5
Suspends the tones above.
PDC: This bit is used for the CODEC power-down control. For making this bit valid, "0"s must be written to the control data bits
described in the later section.
PDC = 1: CODEC is in power-down mode. PDC = 0: CODEC is in operation mode.
When the HOW is indicated, the LOSS output is "1". Otherwise it is "0".
In the above specification, the data contents written later are valid. The signal of sounder path (SA0, SA1) and the signal of receive path
(RPO) can not be output simultaneously.
MSM6895/6896
*1.
Remarks
¡ Semiconductor
FUNCTIONAL DESCRIPTION
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
X
X
0
0
1
*4.
*5.
*6.
Output Tone
Frequency
Make/Break Timing *6
(Hz)
Make (Sec) Break1 (Sec) Break2 (Sec)
IIT
400
0.25
X
X
0
1
0
T250
250
Continuous
NTTC
X
0
1
1
FTONE (1)
1k
Continuous
FTONE (2)
1k
0.25
*4
X
1
0
0
0
0
0
0
0
0
Suspends the all above tones
0
0
0
0
0
1
Suspends the IIT tone
0.1
0
1
0
Suspends the T250 tone
0
1
1
Suspends the FTONE
2.25
Remarks
Tone output:
RPO, SPO
•
¡ Semiconductor
Control of function key acknowledge tone
—
NTTC = 1 when the initial state is set. NTTC can be set as PBTC when the PB tone is set, but the data written into NTTC in later is valid.
When NTTC = 1, the FTONE (1) and FTONE (2) signals are output from SPO. When NTTC = 0, these signals are output from RPO.
NTTC = 1 when FTONE and PB tone is stopped.
When two or more signals are specified out of IIT, T250 and FTONE, the output signals are compounded by two or three tones.
The definition of Make/Break Timing is as follows;
Break1
Break2
Make
MSM6895/6896
25/43
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Output PB Frequency
Remarks
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PB
Low
High
1
0
1
PBTC
0
0
0
0
1
697 Hz
1209 Hz
When PBTC = 0, the PB tone is output from the transmit path and the
0
0
0
1
2
697 Hz
1336 Hz
receive path RPO.
0
0
1
0
3
697 Hz
1477 Hz
The conditions of internal control signals are MUTN = 0 and NTTC = 0.
0
0
1
1
A
697 Hz
1633 Hz
0
1
0
0
4
770 Hz
1209 Hz
When PBTC = 1, the PB tone is output only from the receive path
0
1
0
1
5
770 Hz
1336 Hz
SPO.
0
1
1
0
6
770 Hz
1477 Hz
The PB signal is not output from the transmit path.
0
1
1
1
B
770 Hz
1633 Hz
The conditions of internal control signals are MUTN = 1 and NTTC = 1.
1
0
0
0
7
852 Hz
1209 Hz
1
0
0
1
8
852 Hz
1336 Hz
When the initial state is set and the PB tone is suspended,
1
0
1
0
9
852 Hz
1477 Hz
the conditions of internal control signals are MUTN = 1 and NTTC = 1.
1
0
1
1
C
852 Hz
1633 Hz
1
1
0
0
*
941 Hz
1209 Hz
1
1
0
1
0
941 Hz
1336 Hz
1
1
1
0
#
941 Hz
1477 Hz
1
1
1
1
D
941 Hz
1633 Hz
X
X
X
X
0
0
¡ Semiconductor
PB tone control
Suspends the PB tone
MSM6895/6896
26/43
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control data
Latch output
Remarks
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
0
0
0
0
1
0
0
1
0
LML1 = 1
Initially all latch are set to "0". For details of speech path control, refer to Table 1 to 4.
0
0
1
1
LMX1 = 1
Each latch can be specified independently.
0
1
0
1
LT2 = 1
0
1
1
0
LML2 = 1
0
1
1
1
LMX2 = 1
1
0
0
0
LR = 1
1
0
0
1
LS = 1
1
0
1
0
LMN = 1
1
0
1
1
LMR = 1
1
1
0
0
LA = 1
These general latches are for external control. LA, LB, LC, and LD correspond to
1
1
0
1
LB = 1
the external pin symbols and are set independently. Initially, all latches are set to "0".
1
1
1
0
LC = 1
1
1
1
1
LD = 1
1
1
Latch codes described above
LT1 = 1
These latch are for internal control and used for control of speech path.
¡ Semiconductor
Latch control and timer reset
The output at the LML pin is in "1" when either LML1, LML2, or LMR is in "1".
Sets the corresponding latches listed above to "0".
0
0
0
0
0
0
0
0
Sets all latches listed above to "0".
1
1
0
0
0
0
Resets the watch dog timer.
MSM6895/6896
27/43
Status Symbol
Notes:
Output Signal at T1O
Control Symbol
LML1 LT1 LMX1 LML2 LT2 LMX2 LMN MUTN SG
Ht
SG
T
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
1
1
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
0
—
—
—
1
—
—
—
—
—
—
TA-1
0
0
X
—
—
—
X
X
1
TA-2
0
1
0
—
—
—
0
1
TA-3
0
1
0
—
—
—
1
1
TA-4
0
1
1
—
—
—
0
1
TA-5
0
1
1
—
—
—
1
1
TA-6
0
1
X
—
—
—
X
T
TMX1 PBt
Output Signal at T2O
TMX2 PBt
Ht
TA-7
1
X
X
—
—
—
X
X
—
—
—
—
1
—
—
—
—
—
TB-1
—
—
—
0
0
X
X
X
—
—
—
—
—
1
—
—
—
—
TB-2
—
—
—
0
1
0
0
1
—
—
—
—
—
—
1
—
—
—
TB-3
—
—
—
0
1
0
1
1
—
—
—
—
—
1
—
—
—
—
TB-4
—
—
—
0
1
1
0
1
—
—
—
—
—
—
1
1
—
—
TB-5
—
—
—
0
1
1
1
1
—
—
—
—
—
—
—
1
—
—
TB-6
—
—
—
0
1
X
X
0
—
—
—
—
—
—
—
—
1
—
TB-7
—
—
—
1
X
X
X
X
—
—
—
—
—
—
—
—
—
1
¡ Semiconductor
Table 1. Transmit speech path setting list
1. MUTN of Control Signal is set by PBTC (DB4).
MUTN = 1 when the initial state is set. MUTN = 0 when PBTC = 0. MUTN = 1 when PBTC= 1.
2. SG: Signal ground, T: Transmit signal, TMX1: Transmit addition signal 1, TMX2: Transmit addition signal 2, PBt: PB signal, Ht: Hold
tone signal
3. The output signals of T1O and T2O are the signals added by the signals indicated in "1"s in each column.
MSM6895/6896
28/43
Status Symbol
Notes:
Control Signal
Control Signal Output signal of
Output Signal at RPO
R1
R2
Ts
RT0
RT1
FT
PBr
LR
0/1
—
—
—
1
1
1/0
1/0
0
SG
0/1
1
—
1
1
1
1/0
1/0
1
Input signal to RMI
0
0/1
1
—
—
1
1
1/0
1/0
X
0/1
1
—
—
1
1
1/0
1/0
1
0/1
—
1
1
1
1
1/0
1/0
0
0
0/1
—
1
—
1
1
1/0
1/0
1
X
0/1
—
1
—
1
1
1/0
1/0
1
0
1
0/1
1
1
1
1
1
1/0
1/0
1
0
0
0/1
1
1
—
1
1
1/0
1/0
1
1
X
0/1
1
1
—
1
1
1/0
1/0
0
X
X
X
—
—
—
1
1
—
—
1
0
X
X
X
1
—
—
1
1
—
—
0
1
X
X
X
—
1
—
1
1
—
—
1
1
X
X
X
1
1
—
1
1
—
—
LS
LT1
LT2
LMN MUTN NTTC
RP-1
0
0
0
X
X
RP-2
0
1
0
0
1
RP-3
0
1
0
0
RP-4
0
1
0
1
RP-5
0
0
1
0
RP-6
0
0
1
RP-7
0
0
1
RP-8
0
1
RP-9
0
1
RP-10
0
1
RP-11
1
0
RP-12
1
RP-13
1
RP-14
1
RMO0 and RMO1
29/43
MSM6895/6896
4. R1: Receive signal 1, R2: Receive signal 2, Ts: Side tone signal, RT0: DT, PDT, SDT, CRBT, and IIT, RT1: RBT, BT, and T250, FT:
FTONE and PBr: PB acknowledge signal.
5. Output Signal RPO is the signal added by the signal indicated in "1"s in each column.
6. "0"s of Control Signal NTTC are equivalent to "1"s of the Output Signals FT and PBr, and "1"s are equivalent to "0"s of Output Signals.
7. Control Signals MUTN and NTTC are the internal control signals. Initially, both signals are in "1"s. MUTN is controlled by PBTC
of controlling the PB tone.
MUTN = 0 when PBTC = 0. MUTN = 1 when PBTC = 1.
NTTC is controlled by PBTC of controlling the PB tone or NTTC of controlling the function key acknowledge tone, but the NTTC
data written later is valid.
NTTC = 0 when PBTC = 0. NTTC = 1 when PBTC = 1.
¡ Semiconductor
Table 3. Control of receive
main amplifier
Table 2. Receive speech path setting list (RPO output)
Status Symbol
Notes:
Output Signal at SPO
Control Signal
SG
R1
R2
RT0
RT1
FT
PBr
Hr
0
1
—
—
—
—
—
—
—
X
1
—
—
—
—
—
1
1
—
X
0/1
—
—
—
—
—
0/1
0/1
1
0
0
X
—
—
—
1
1
1
1
—
0
1
0
X
—
1
—
1
1
1
1
—
0
0
1
X
—
—
1
1
1
1
1
—
1
0
1
1
X
—
1
1
1
1
1
1
—
1
1
0
0
X
—
—
—
1
1
1
1
1
LS
LMR
LT1
RS-1
0
0
X
LT2 NTTC
X
RS-2
0
0
X
RS-3
0
1
X
RS-4
1
0
RS-5
1
RS-6
1
RS-7
RS-8
RS-9
1
1
1
0
X
—
1
—
1
1
1
1
1
RS-10
1
1
0
1
X
—
—
1
1
1
1
1
1
RS-11
1
1
1
1
X
—
1
1
1
1
1
1
1
¡ Semiconductor
Table 4. Receive speech path setting list (SPO)
8. SG: Signal ground, R1: Receive signal 1, R2: Receive signal 2, Hr: Hold acknowledge tone, PBr: PB acknowledge tone, FT: FTONE,
RT0: DT, PDT, SDT, CRBT, and IIT and RT1: RBT, BT, and T250.
9. An Output Signal at SPO is the signal added by the signal indicated in "1"s in each column.
10. The Control Signal NTTC is defined equally to Notes : 7.
MSM6895/6896
30/43
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Status
Control Data
Main Connection Status
Remarks
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Symbol
0
0
0
0
0
0
0
0
A1
0
0
1
A2
B1T¨DOUT
B1RÆDIN independently.
0
1
0
A3
B1T¨BT1
B1RÆBR1
0
1
1
A4
B1T¨BT2
1
0
0
B1
B2T¨"1"
1
0
1
B2
B2T¨DOUT
B2RÆDIN
1
1
0
B3
B2T¨BT1
B2RÆBR1 Refer to Table 5 and 6 for details.
B1T¨"1"
B1RÆNo connection Different groups (A, B, C, and D) are set
B1RÆBR2 For setting the same group, the data written later is
B2RÆNo connection valid.
1
1
1
B4
B2T¨BT2
B2RÆBR2 The initial statuses are A1 and B2.
1
X
X
X
C
B1T¨B2R
B2T¨B1R
X
X
X
1
X
X
X
X
D1
B1T¨B1R
X
X
1
X
X
X
X
X
D2
B2T¨B2R
X
1
X
X
X
X
X
X
D3
BT1ÆBR1
1
X
X
X
X
X
X
X
D4
BT2ÆBR2
¡ Semiconductor
Channel selector control
MSM6895/6896
31/43
Status
Output Pin Connection Status
Symbol
BIT
B2T
DIN
BR1
BR2
A1
1
—
*1
*1
*1
A2
DOUT
—
B1R
*1
*1
A3
BT1
—
*1
B1R
*1
A4
BT2
—
*1
*1
B1R
B1
—
1
*1
*1
*1
B2
—
DOUT
B2R
*1
*1
B3
—
BT1
*1
B2R
*1
B4
—
BT2
*1
*1
B2R
Remarks
Table 6. Output pin status by the combination of A and B
Setting of A Setting of B
Initial Setting
A1
Initial Setting
A2
Output Pin Connection Status
DIN
BR1
BR2
B1
1
1
1
B2
B2R
1
1
B3
1
B2R
1
B4
1
1
B2R
B1
B1R
1
1
B2
B1R or B2R
1
1
B3
B1R
B2R
1
B4
B1R
1
B2R
C
B2R
B1R
—
—
—
B1
1
B1R
1
D1
B1R
*3
—
*4
*4
B2
B2R
B1R
1
D2
*2
B2R
—
*4
*4
B3
1
B1R or B2R
1
D3
*2
*3
—
BT1
*4
B4
1
B1R
B2R
D4
*2
*3
—
*4
BT2
B1
1
1
B1R
B2
B2R
1
B1R
B3
1
B2R
B1R
B4
1
1
B1R or B2R
A4
*5.
Initial Setting
DIN *5
BR1 *5
BR2 *5
When writing is performed in the sequence of setting of A and
setting of B, the output status becomes B2R, and when writing
is performed in the sequence of setting of B and setting of A, the
output status becomes B1R.
32/43
MSM6895/6896
Notes: 11. *1. According to the combination of A and B (Table 6).
*2. One of statuses A1 to A4 is held.
*3. One of statuses B1 to B4 is held.
*4. One of statuses A1 to A4 or one of statuses B1 to B4,
whichever is written later, is held.
When the setting of C is performed before the setting
of D group, the setting of D must be performed after
the setting of the group A and B.
12. The statuses of the pins indicated by "—" is not
affected.
13. DIN is connected to the digital input of CODEC and
DOUT is connected to the digital output of CODEC.
A3
Remarks
¡ Semiconductor
Table 5. Output pin connection status by channel selector control
WRITE Mode
Address Data
AD1 = 1, AD0 = 0
Control Data
DB7
DB6
DB5
0
0
0
DB4
DB3
DB2
DB1
Remarks
DB0
Output Data
The data set in DB4 to DB0 is output from output pins PO4 to PO0, respectively.
The output statuses are held until the data is rewritten.
¡ Semiconductor
key scanning output control and interrupt
When the data is "0", the output goes to "0", when the data is "1", the output is left open.
Initially, PO4 to PO0 are left open.
1
X
X
X
X
X
X
X
Resets the INTT output and sets to "1".
This control data is valid only when written, it is not held.
MSM6895/6896
33/43
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
Control Data
Control
Remarks
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
X
X
X
X
0
0
Volume 1 (High)
The setting of volume and tone
0
1
Volume 2 (Medium)
combination is performed
1
0
Volume 3 (Low1)
simultaneously, not
independently.
1
1
Volume 4 (Low2)
X
X
Tone combination setting (Initial setting) by external control (SW0, SW1)
0
0
0
0
0
1
Tone combination 1 (1.0 kHz and 1.3 kHz, 16 Hz Wamble period)
Initially the high volume is set,
0
1
0
Tone combination 2 (0.8 kHz and 1.0 kHz, 16 Hz Wamble period)
and tone combination is set
0
1
1
Tone combination 3 (0.8 kHz and 1.0 kHz, 8 Hz Wamble period)
externally.
1
0
1
Tone combination 4 (0.5 kHz and 0.65 kHz, 16 Hz Wamble period)
1
1
0
Tone combination 5 (0.4 kHz and 0.5 kHz, 16 Hz Wamble period)
1
1
1
Tone combination 6 (0.4 kHz and 0.5 kHz, 8 Hz Wamble period)
¡ Semiconductor
Sounder, volume, and tone combination
MSM6895/6896
34/43
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
Contorol Data
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
X
X
X
0
0
0
Control
CODEC power-down is controlled by PDC (DB4) during sounder
control. (Initial setting)
Remarks
Data written later is valid.
¡ Semiconductor
CODEC power down control
PDC = 0 CODEC power-on
PDC = 1 CODEC power-down
1
0
1
CODEC Transmit power-down
1
1
0
CODEC Receive power-down
1
1
1
CODEC Transmit and Receive power-down
1
0
0
CODEC power-down release
MSM6895/6896
35/43
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
DB7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
X
X
X
X
0
0
0
1
1
X
Control
Remarks
Sets the transmit PB tone and hold tone level at the typical
The gain setting of the transmit path
value.(Initial setting)
and the receive path can be performed
Sets the transmit PB tone and hold tone level by 3 dB below the
simultaneously, not independently.
¡ Semiconductor
Gain control
typical value.
Sets the transmit PB tone and hold tone level by 6 dB below the
typical value.
0
0
X
X
Sets the receive gain at the typical value. (Initial setting)
0
1
X
X
Sets the receive gain by 3 dB above the typical value.
1
0
X
X
Sets the receive gain by 6 dB above the typical value.
1
1
X
X
Sets the receive gain by 9 dB above the typical value.
MSM6895/6896
36/43
WRITE Mode
Address Data
AD1 = 1, AD0 = 0
Control Data
Control
Remarks
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
X
X
X
X
X
0
Howler tone frequency: 0.8 kHz
1
Howler tone frequency: 1.0 kHz and 1.3 kHz, 16 Hz Wamble period
Initial setting
¡ Semiconductor
Howler tone color combination
Key scanning data read out
READ Mode
Address Data
AD1 = 1, AD0 = 0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
Control
The data input to the pins PI7 to PI0 is output from DB7 to DB0, respectively.
MSM6895/6896
37/43
Speaker
DG
LED
Driver
AG
AG
0.47 mF
1 mF
SW
Matrix
1 mF
100 kW
AG
LB
SA1
LA
SAO
SPO
RMO1
RMI
RMO0
VSG
CAO
R1I
RPO
TPAI
100 kW Melody
Tone
Generation
0.47 mF
MSM6895
LML
10 mF
+
PO3
TPAO
PO0
TPBI
TMX1I
TMX2I
R2I
T1O
CAI
MLDY
PO4
Handset
VSGC
B1T
B1R
B2T
B2R
CK8
CK64
BT1
BT2
TEST
CK1536
WR
RD
CE
AD1
AD0
DB7 to DB0
INTT
TIME
RESET
VA
VD
VAG
VDG
100 kW ¥ 2
+5 V
SW0
SW1
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
+5 V analog
DG
0-20W
10 mF
AG
+
100 kW ¥ 8
+5 V
0.1 mF
1 mF
DG
Swith the sounder
tone combination
0 V analog
+5 V analog
Controller
Line Interface
¡ Semiconductor
MSM6895/6896
APPLICATION CIRCUIT
Line
Sounder
38/43
PO2
PO1
¡ Semiconductor
MSM6895/6896
Application circuit at the PCM Signal Data Rate of 192, 384, 768, 1536 and 2048
kbps.
BCLOCK signal
When the PCM signal data rate is one of 192, 384, 768, 1536, and 2048 kbps, input the 9-bit burst
clock corresponding to the frequency equivalent to each of the data rates, as CK64 signal.
125 mS
CK8
1 2 3 4 5 6 7 8 9
CK64
PCMIN/OUT
1 2 3 4 5 6 7 8
Burst clock generator
+5 V
16
11 10
9
Equivalent to the 74LS161
1
2
7
8
MSM6895/6896
Continuous Clock
0V
CK64
8 kHz
Syncronous Signal
CK8
Continuous Clock
Syncronous Signal
Burst Clock
39/43
¡ Semiconductor
MSM6895/6896
Application Circuit of Three-party Speech Path
Speaker A
(A)
M
(A)
(A + C)
TPAI TPAO TPBI
(B)
(A + B)
Handset
(C)
(B)
(C)
(B)
T1O
TMX2I
T2O
TMX1I
CAO
AD
B1T
DA
B1R
B2T
R2I
R1I
CAI
B2R
MSM6895
RPO
RMI
(B + C)
(A + B)
(C)
RMO0
BR2
RMO1
BT2
AIN
MSM7508
AOUT
AD
DA
(A + C)
(B)
Speaker B
(A + B)
(C)
Speaker C
Note:
(A) indicates
the voice signal of
the A speaker
PCMOUT
PCMIN
Speech path setting (Speech through a handset)
Transmit:
Receive:
TA-4 (LT1 = 1, LMX1 = 1, LMN = 0, MUTN = 1)
TB-4 (LT2 = 1, LMX2 = 1, LMN = 0, MUTN = 1)
RP-8 (LT1 = 1, LT2 = 1, LMN = 0, MUTN = 1, LR = 1)
Channel selector control
A2, B4
40/43
MLDY
TMX2I
TMX1I
T1O
T2O
CAI (Maximum input of 1.2 Vop)
0 dB
TPAI
+20 dB
+17.7 dB
0, –3, –6dB
+
AD
0 dB
–2 dB
0, –3, –6dB
0, 3, 6, 9 dB
R1I
+6 dB
–6 dB
0, 3, 6, 9 dB
R2I
DA
0 dB
0 dB
–6 dB
0, –3, –6 dB
+
RPO
RMI
–6.8 dB
–8.8 dB
–
–2 dB
0, –3, –6 dB
+6 dB
+15.3 dB
RMO0
X1
RMO1
X–1
RTONE1
RTONE2
FTONE
+
91.7 mVPP (DT, PDT, SDT, CRBT)
157 mVPP (RBT, BT, T250)
161 mVPP
PB tone
–6.8 dB
SPO
¡ Semiconductor
TPBI
SPEECH PATH GAIN
TPAO
Generator
0 dB
–21.4 dBV (240 mVPP per signal)
FTONE
189 mVPP
41/43
CAO (Maximum input of 1.2 Vop)
MSM6895/6896
–3 dB
¡ Semiconductor
MSM6895/6896
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.
• Unused analog input pins must be connected to the VSG pin and unused digital pins must
be connected to the GND pin.
42/43
¡ Semiconductor
MSM6895/6896
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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