FEDL7022-01-06 1Semiconductor ML7022-01 This version: May 2000 Previous version: Sep. 1999 Single Rail Dual Channel PCM CODEC GENERAL DESCRIPTION The ML7022 is a two-channel single-rail CODEC CMOS IC for voice signals ranging from 300 to 3400Hz. This device contains two-channel analog-to-digital (A/D) and digital-to-analog (D/A) converters on a single chip. The ML7022 is designed especially for a single power supply and low power applications and achieves a reduced footprint. The ML7022 is best suited for line card applications with easy interface to subscriber line interface circuits (SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external components and optimizing board space. FEATURES • Single 5 V Power Supply Operation • Using ∆-Σ ADC and DAC Technique • Low Power Consumption 2-Channel Operating Mode: typical: 70 mW max.: 90 mW 1-Channel Operating Mode: typical: 40 mW max.: 55 mW Power Saving Mode: (CPD1 = CPD2 = “0”) typical: 9 mW max.: 12.5 mW Power Down Mode: (PDN = “0”) typical: 0.05 mW max.: 0.25 mW • ITU-T Companding Law - µ-law • Built-in Dual 3-bit Latches with CMOS Drive Capability • Serial PCM Interface • Master Clock: 4.096 MHz • Transmission Clocks: 256 to 4096 kbps • Adjustable Transmit Gain • Built-in Reference Voltage Supply • Analog Output can Directly Drive a 600Ω Line Transformer • Latched Content Echo-back Function • Package Type: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB) 1/20 AOUT2 SG Gen. LPF ∆-Σ DA CONV RC LPF VDD AG DG SGC LPF BPF BPF ∆-Σ DA CONV ∆-Σ AD CONV ∆-Σ AD CONV RC LPF RC LPF RC LPF AOUT1 GSX2 AIN2 GSX1 AIN1 Power Cont. & Clock Gen. Expander Expander Compressor Compressor LATCH RCONT TCONT DIN RSYNC BCLK XSYNC DOUT FEDL7022-01-06 1Semiconductor ML7022-01 BLOCK DIAGRAM C1A C2A C3A C1B C2B C3B PDN MCK 2/20 FEDL7022-01-06 1Semiconductor ML7022-01 PIN CONFIGURATION (TOP VIEW) VDD 1 30 PDN TEST1 2 29 C1A TEST2 3 28 C2A AIN1 4 27 C3A GSX1 5 26 RSYNC AOUT1 6 25 XSYNC TEST3 7 24 DG AG 8 23 DOUT SGC 9 22 DIN 21 BCLK AOUT2 10 GSX2 11 20 MCK AIN2 12 19 C3B TEST4 13 18 C2B TEST5 14 17 C1B 16 TEST6 VDD 15 30-Pin Plastic SSOP 3/20 FEDL7022-01-06 1Semiconductor ML7022-01 PIN DESCRIPTIONS Pin Symbol Type Description 1 VDD — 2 TEST1 I Device Test Pin 1 3 TEST2 I Device Test Pin 2 Power Supply * 4 AIN1 I Channel-1 Transmit Op-amp Input 5 GSX1 O Channel-1 Transmit Op-amp Output 6 AOUT1 O Channel-1 Receive Output 7 TEST3 I 8 AG — Analog Ground 9 SGC O Signal Ground 10 AOUT2 O Channel-2 Receive Output 11 GSX2 O Channel-2 Transmit Op-amp Output Device Test Pin 3 12 AIN2 I Channel-2 Transmit Op-amp Input 13 TEST4 I Device Test Pin 4 14 TEST5 I Device Test Pin 5 15 VDD — 16 TEST6 I Device Test Pin 6 17 C1B O C1B Bit Latched Output 18 C2B O C2B Bit Latched Output 19 C3B O C3B Bit Latched Output 20 MCK I Master Clock (4.096 MHz) 21 BCLK I Shift Clock for the DIN and DOUT 22 DIN I Data Input 23 DOUT O Data Output 24 DG — Digital Ground 25 XSYNC I 26 RSYNC I Receive Synchronizing Signal 27 C3A O C3A Bit Latched Output 28 C2A O C2A Bit Latched Output 29 C1A O C1A Bit Latched Output 30 PDN I Power Down Control Power Supply * Transmit Synchronizing Signal * VDD of pin 1 and VDD of pin 15 are connected internally, but these pins must be connected on the printed circuit board. 4/20 FEDL7022-01-06 1Semiconductor ML7022-01 ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit — –0.3 to +7.0 V — –0.3 to VDD+0.3 V VDIN — –0.3 to VDD+0.3 V TSTG — –55 to +150 °C Symbol Condition Power Supply Voltage VDD Analog Input Voltage VAIN Digital Input Voltage Storage Temperature RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Symbol Condition Min. Typ. Max. Unit VDD Voltage must be fixed 4.75 5.0 5.25 V Operating Temperature TOP — –40 — +85 °C Analog Input Voltage VAIN Gain = 1 — — 3.4 VPP High Level Input Voltage VIH 2.2 — VDD V Low Level Input Voltage VIL 0 — 0.8 V MCK –0.01% 4096 +0.01% kHz MCK Frequency FMCK All Digital Input Pins BCLK Frequency FBCLK BCLK 256 — 4096 kHz Sync Pulse Frequency FSYNC XSYNC, RSYNC — 8 — kHz Clock Duty Ratio DCLK MCK, BCLK 40 50 60 % — — 50 ns — — 50 ns Digital Input Rise Time TIR Digital Input Fall Time TIF MCK to BCLK Phase Difference TMB MCK, BCLK — — 50 ns Transmit Sync Pulse Setting TXS BCLK to XSYNC 50 — — ns Time TSX XSYNC to BCLK 50 — — ns Receive Sync Pulse Setting TRS BCLK to RSYNC 50 — — ns Time TSR RSYNC to BCLK 50 — — ns Sync Pulse Width TWS XSYNC, RSYNC 1 BCLK — 100 µs DIN Set-up Time TDS DIN 50 — — ns DIN Hold Time TDH DIN 50 — — ns RDL Pull-up Resistor, DOUT 0.5 — — kΩ DOUT — — 50 pF C1A, C2A, C3A,C1B, C2B, C3B — — 50 pF SG to AG 0.1 — — µF Digital Output Load Bypass Capacitor for SGC CDL CSG All Digital Input Pins 5/20 FEDL7022-01-06 1Semiconductor ML7022-01 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit IDD1 2CH Operating Mode, No Signal PDN = “1”, CPD1 = CPD2 = “1” — 14.0 18.0 mA IDD2 1CH Operating Mode, No Signal PDN = “1”, CPD1 = “1”, CPD2 = “0” or PDN = “1”, CPD1 = “0”, CPD2 = “1” — 8.0 11.0 mA IDD3 Power Saving Mode, PDN = “1”, CPD1 = CPD2 = “0” — 1.8 2.5 mA IDD4 Power Down Mode, PDN = “0” — 0.01 0.05 mA High Level Input Leakage Current IIH All Digital Input Pins VI = VDD — — 2.0 µA Low Level Input Leakage Current IIL All Digital Input Pins VI = 0 V — — 0.5 µA DOUT, Pull-up = 0.5 kΩ 0 0.2 0.4 V C1A, C2A, C3A, C1B, C2B, C3B IOL = 0.4 mA 0 0.2 0.4 V C1A, C2A, C3A, C1B, C2B, C3B IOH = 0.4 mA 2.5 — — V — — V Power Supply Current Digital Output Low Voltage Digital Output High Voltage VOL VOH VDD C1A, C2A, C3A, C1B, C2B, C3B IOH = 50 µA –0.5 Digital Output Leakage Current IO DOUT High Impedance State — — 10 µA Input Capacitance CIN — — 5 — pF Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Parameter SGC Rise Time Symbol Condition Min. Typ. Max. Unit TSGC SG to AG 0.1 µF Rise time to 90% of max. level — — 10 ms Transmit Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Input Resistance RINX RLGX 20 Output Load Capacitance CLGX AIN1, AIN2 GSX1, GSX2 with respect to SG *1 10 Output Load Resistance — Output Amplitude VOGX Offset Voltage VOSGX Gain = 1 Typ. Max. Unit — — MΩ — — kΩ — 30 pF –1.13 — 1.13 V –20 — 20 mV *1 0.27 dBm (600Ω) = 3.17 dBm0 (µ-law) = 2.26 VPP 6/20 FEDL7022-01-06 1Semiconductor ML7022-01 Receive Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Output Load Resistance RLAO AOUT1, AOUT2 (each) with respect to SG 0.6 — — kΩ Output Load Capacitance CLAO AOUT1, AOUT2 — — 50 pF Output Amplitude VOAO AOUT1, AOUT2, RLAO = 0.6 kΩ with respect to SG –1.7 — 1.7 V Offset Voltage VOSAO AOUT1, AOUT2 with respect to SG –100 — 100 mV AC Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Parameter Transmit Frequency Response Receive Frequency Response Transmit Signal to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Receive Gain Tracking Symbol Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 SDT1 SDT2 SDT3 SDT4 SDT5 SDR1 SDR2 SDR3 SDR4 SDR5 GTT1 GTT2 GTT3 GTT4 GTT5 GTR1 GTR2 GTR3 GTR4 GTR5 Freq. (Hz) 60 300 1020 3000 3300 3400 100 1020 3000 3300 3400 1020 1020 1020 1020 Condition Level (dBm0) Min. 25 –0.15 0 GSXn to DOUT (Attenuation) 0 DIN to AOUTn (Attenuation) 3 0 –30 –40 –45 3 0 –30 –40 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 NIDLET — — NIDLER — — Idle Channel Noise GSXn to DOUT *2 DIN to AOUTn *2 –0.15 –0.15 0 –0.15 –0.15 –0.15 0 36 36 36 30 25 36 36 36 30 25 –0.2 GSXn to DOUT –0.2 –0.6 –1.2 –0.2 DIN to AOUTn –0.2 –0.6 –1.2 AINn = SG *2 AINn to DOUT DIN = 0 code *2 DIN to AOUTn Typ. 45 0.15 Reference 0.02 0.1 0.6 0.04 Reference 0.07 0.2 0.6 43 40 38 32 29 42 39 39 33 30 0.02 Reference 0.06 0.4 0.4 0 Reference –0.02 –0.1 –0.2 Max. Unit — 0.20 0.20 0.80 0.80 0.2 0.2 0.8 0.8 — — — — — — — — — — 0.2 dB dB dB dB 0.2 0.6 1.2 0.2 dB 0.2 0.6 1.2 dB — 14 16 — 6 10 dBrnc0 *2 C-message Filter is used 7/20 FEDL7022-01-06 1Semiconductor ML7022-01 AC Characteristics (Continued) Parameter Symbol Freq. (Hz) AVT Absolute Level (Initial Difference) AVR Absolute level (Deviation of Temperature and power) Absolute Delay Transmit Group Delay Receive Group Delay Cross Talk Attenuation Discrimination Out of Band Spurious Signal Frequency Distortion Intermoduration Distortion Power Supply Noise Rejection Ratio Digital Output Delay Time DOUT Operation Delay Time AOUT Signal Output Delay Time 1020 AVTT AVRT TD 1020 (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C) Condition Min. Typ. Max. Unit Level (dBm0) GSXn to DOUT 0.535 0.555 0.574 VDD = 5 V, Ta = 25°C Vrms DIN to AOUTn 0.806 0.835 0.864 VDD = 5 V, 0 Ta = 25°C –0.3 — 0.3 VDD = 4.75 to 5.25 V dB Ta = –40 to 85°C –0.3 — 0.3 0 A to A Mode BCLK = 2048 kHz TGD T1 500 TGD T2 600 TGD T3 1000 0 *3 TGD T4 2600 TGD T5 2800 TGD R1 500 TGD R2 600 TGD R3 1000 0 *3 TGD R4 2600 TGD R5 2800 CRT Trans to Receive 1020 0 CRR Receive to Trans CRCH Channel to Channel DIS 4.6 to 72k 0 0 to 4 kHz 300 to OBS 0 4.6 kHz to 1000 kHz 3.4k SFDT 1020 0 0 to 4 kHz SFDR IMDT fa = 470 –4 2 fa - fb fb = 320 IMDR PSRT1 0 to 4k PSRT2 4 to 50k 100 *4 mVrms PSRR1 0 to 4k PSRR2 4 to 50k TSD DOUT TXD1 Pull-up resister = 0.5 kΩ CL = 50 pF and 1 LSTTL TXD2 C1A, C2A, C3A, C1B, C2B, C3B TPDC CL = 50 pF and 1 LSTTL — 0.58 0.6 ms — — — — — — — — — — 75 75 75 30 0.26 0.16 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 83 80 78 32 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — — — — –37.5 –35 — — — — 40 50 40 50 20 20 20 –50 –48 –50 –54 44 55 45 56 — — — –40 –40 –40 –40 — — — — 100 100 100 20 — 1000 ns ms ms dB dB dB dBm0 dBm0 dB ns TDDO Time of operation start after power on — 4 — ms TDAO Time of base band signal output start after power on — 4 — ms *3 Minimum value of the group delay distortion *4 The measurement under idle channel noise 8/20 FEDL7022-01-06 1Semiconductor ML7022-01 TIMING DIAGRAM MCK BCLK XSYNC 1 2 TMB 3 4 5 6 7 8 TSX TXS TWS TSD MSD D2 TXD1 DOUT TXD2 D4 D3 D5 D6 D7 D8 Figure 1 Transmit Side Timing Diagram MCK BCLK 1 2 TMB 3 4 5 6 7 8 TSR TRS RSYNC TWS DIN MSD TDS D2 D3 TDH D4 D5 D6 D7 D8 Figure 2 Receive Side Timing Diagram 1 9 17 25 1 BCLK CH1 PCM DATA ECHO bits CH2 PCM DATA ECHO bits MSD D2 D3 MSD D2 D3 D4 D5 D6 D7 D8 EPD2 EC3B EC2B EC1B DOUT MSD D2 D3 D4 D5 D6 D7 D8 EPD1 EC3A EC2A EC1A XSYNC Figure 3 Transmit Side Bit Configuration 1 9 17 25 1 BCLK MSD D2 D3 MSD D2 D3 D4 D5 D6 D7 D8 CPD2 C3B C2B C1B DIN MSD D2 D3 D4 D5 D6 D7 D8 CPD1 C3A C2A C1A RSYNC CH1 PCM DATA Latch Data CH2 PCM DATA Latch Data CH1 power down control bit CH2 power down control bit Figure 4 Receive Side Bit Configuration 9/20 C3A, C2A, C1A, C3B, C2B, C1B Figure 5 Control Bit Timing and Echo Back Timing TPDC EC1A EC2A EC3A EPD1 D8 D7 D6 D5 D4 D3 D2 MSD TPDC CH1 PCM ECHO OUTPUT DATA BIT C1A C2A C3A CPD1 D8 D7 D6 D5 D4 D3 D2 MSD CH2 PCM ECHO OUTPUT DATA BIT EC1B EC2B EC3B EPD2 D8 D7 D6 D5 D4 D3 D2 MSD CH2 PCM ECHO OUTPUT DATA BIT 25 C1B C2B C3B CPD2 D8 D7 D6 D5 D4 D3 D2 MSD CH1 PCM ECHO OUTPUT DATA BIT 17 EC1A EC2A EC3A EPD1 D8 D7 D6 D5 D4 D3 D2 MSD DOUT 9 C1A C2A C3A CPD1 D8 D7 D6 D5 D4 D3 D2 MSD DIN 1 CH2 PCM Control INPUT DATA DATA 25 CH1 PCM Control INPUT DATA DATA 17 EC1B EC2B EC3B EPD2 D8 D7 D6 D5 D4 D3 D2 MSD CH2 PCM Control INPUT DATA DATA 9 C1B C2B C3B CPD2 D8 D7 D6 D5 D4 D3 D2 MSD CH1 PCM Control INPUT DATA DATA XSYNC RSYNC BCLK 1 FEDL7022-01-06 1Semiconductor ML7022-01 10/20 AOUTn DOUT CPD1 (CPD2) SGC PDN TDAO TDDO SG Level Figure 6 SGC, DOUT and AOUT Output Timing High Impedance TSGC FEDL7022-01-06 1Semiconductor ML7022-01 11/20 FEDL7022-01-06 1Semiconductor ML7022-01 FUNCTIONAL DESCRIPTION Pin Functional Description AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below. If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down mode, the GSX1 and GSX2 outputs are at AG voltage. In the case of the analog input 2.26 Vpp at GSX pin with digital output +3.17 dBm0 (µ-law). GSX1 R2 CH1 Analog Input C1 AIN1 R1 SG GSX2 R4 CH2 Analog Input C2 AIN2 R3 CH1 Gain Gain = R2/R1 ≤ 10 R1: Variable R2 > 20 kΩ C1 > 1/ (2 × 3.14 × 30 × R1) CH2 Gain Gain = R4/R3 ≤ 10 R3: Variable R4 > 20 kΩ C2 > 1/ (2 × 3.14 × 30 × R3) SG AOUT1, AOUT2 AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2. The output signal has an amplitude of 3.4Vpp above and below the signal ground voltage (SG).When the digital signal of +3.17 dBm0 is input to DIN, it can drive a load of 600Ω or more. During power saving or power down mode, these outputs are at a high impedance. VDD Power supply for +5 V. Connect a bypass capacitor of 0.1 µF with excellent high frequency characteristics between this pin and the AG pin. Although VDD pin 1 and VDD pin 15 are connected internally, these pins must be connected on the printed circuit board. 12/20 FEDL7022-01-06 1Semiconductor ML7022-01 AG Ground for the analog signal circuits. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. SGC Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1 µF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. During power down mode, this outputs are at the voltage level of AG with about 50 kΩ impedance. MCK Master clock input. The frequency must be 4.096 MHz. BCLK Shift clock signal input for the DIN and DOUT signals. The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK. RSYNC Receive synchronizing signal input. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). 13/20 FEDL7022-01-06 1Semiconductor ML7022-01 DIN DIN is a data input pin. The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2 pin. The 28 bit signal structure is shown in Figure 4. It consists of voice band PCM signals (8 bits each), the generalpurpose latch signal (6 bits total), the power down control signal (1 bit per channel) and empty bits (4 bits). The signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits. The start of the PCM data (Channel 1’s MSD) is identified at the rising edge of RSYNC. The general purpose latch signal (C3A, C2A, C1A, C3B, C2B, C1B) are output from six latch output pins. When the CPD1 (bit of DIN) = “0”, Channel 1 block is in a power down state. When the CPD2 (bit of DIN) = “0”, Channel 2 block is in a power down state. DOUT DOUT is a data output pin. The signal consist of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the echo bit (6 bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The output cording format follows ITU-T recommendation on coding law. The output signal is output from Channel 1’s MSD bit in a sequential order, synchronizing with the rising edge of the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state during power down state. A pull-up resistor must be connected to this pin because it is an open drain output. Table 1 The Output Cording Format PCMIN/PCMOUT INPUT/OUTPUT Level µ-law MSD D2 D3 D4 D5 D6 D7 D8 + Full scale 1 0 0 0 0 0 0 0 +0 1 1 1 1 1 1 1 1 –0 0 1 1 1 1 1 1 1 – Full scale 0 0 0 0 0 0 0 0 14/20 FEDL7022-01-06 1Semiconductor ML7022-01 C1A, C2A, C3A, C1B, C2B, C3B General-purpose latched output signal. C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing. These outputs can drive a LSTTL/CMOS device without external resistor. PDN Power down control signal. When PDN is at logic “0” level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all internal latches are in initial state (logic “0” level). TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 These pins are used for device test. These device test pin must be connected to the AG pin. 15/20 FEDL7022-01-06 1Semiconductor ML7022-01 Table 2 Condition of DOUT by the Power Control PDN CPD1 CPD2 CH1 PCM Data CH2 PCM Data CH1 Echo Bit CH2 Echo Bit 0 0/1 0/1 1 0 0 H H H H 11111111 11111111 1 1 0 Operate 11111111 1 0 1 11111111 Operate Latched Data Latched Data 1 1 1 Operate Operate Table 3 Condition of the Latched Output by the Power Control PDN CPD1 CPD2 0 0/1 0/1 1 0/1 0/1 0/1 0/1 0/1 LIN 0 C1A, C2A, C3A C1B, C2B, C3B L L Latched Data Latched Data L L 1 Table 4 Condition of the Analog Output by the Power Control PDN CPD1 CPD2 GSX1 GSX2 AOUT1 AOUT2 SGC 0 0/1 0/1 High Impedance High Impedance High Impedance High Impedance *5 1 0 0 High Impedance High Impedance High Impedance High Impedance Operate 1 1 0 Operate High Impedance Operate High Impedance Operate 1 0 1 High Impedance Operate High Impedance Operate Operate 1 1 1 Operate Operate Operate Operate Operate *5 The voltage level of AG with about 50 kΩ 16/20 +5 V 0V Channel 2 analog output Channel 2 analog input Channel 1 analog output Channel 1 analog input 1 µF + 0.1 µF 0.1 µF VDD DG AG SGC AOUT2 GSX2 AIN2 AOUT1 GSX1 AIN1 C1A C2A C3A C1B C2B C3B TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 DOUT DIN MCK BCLK XSYNC RSYNC PDN ML7022 1 kΩ Latch output Power down control 0: power down/1: operation Master clock & Bit clock input +5 V 2CH Multiplex PCM signal output 2CH Multiplex PCM signal input Master clock & Bit clock input FEDL7022-01-06 1Semiconductor ML7022-01 APPLICATION CIRCUITS 17/20 FEDL7022-01-06 1Semiconductor ML7022-01 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low impedance. • Unless unavoidable, use short lead type socket. • When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. • Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device. 18/20 FEDL7022-01-06 1Semiconductor ML7022-01 PACKAGE DIMENSIONS (Unit: mm) SSOP30-P-56-0.65-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.19 TYP. 5/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/20 FEDL7022-01-06 1Semiconductor ML7022-01 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 20/20