PEDL7048-01-01 1Semiconductor ML7048-01 This version: Oct. 2001 Preliminary 3-Channel Single Rail CODEC GENERAL DESCRIPTION The ML7048 is a three-channel single rail CMOS CODEC LSI. This device contains filters for A-to-D and D-toA conversions of voice signals ranging 300 to 3400 Hz. The ML7048 is designed for a single power supply and low power applications and contains three-channel A-toD and D-to-A converters on a single chip, and achieves a reduced footprint and external component parts. The ML7048 is best suited for ISDN terminal and digital telephone terminal applications. FEATURES • Single 5 V Power Supply Operation • Using ∆-Σ ADC and DAC Technique • Low Power Consumption 3-Channel Operating Mode: typical: 140 mW max.:174 mW Power Saving Mode: (PDN = “1”, PDN1 to 3 = “0”) typical: 15 mW max.: 26 mW Power Down Mode: (PDN = “0”) typical: 0.05 mW max.: 0.3 mW • ITU-T Companding Law: µ-law • PCM Interface: 3-Channel Independent or 3-Channel Continuous Serial Interface Pin Selectable • Master Clock: 12.288 MHz or 15.360 MHz Pin Selectable • Transmission Clocks: 64, 128, 256, 512, 1024, 2048 kHz 96, 192, 384, 768, 1536 kHz • Adjustable Transmit Gain for Each Channel • Built-in Reference Voltage Supply • Differential Analog Output can Directly Drive a 600Ω Transformer. • Package: 44-pin Plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML7048-01GA) 1/20 PEDL7048-01-01 1Semiconductor ML7048-01 RC LPF ∆-Σ AD CONV. BPF BPF GSX1 AIN2– AIN2+ GSX2 AIN3– AIN3+ RC LPF ∆-Σ AD CONV. BPF GSX3 TCONT ∆-Σ AD CONV. Compressor RC LPF Compressor AIN1– AIN1+ Compressor BLOCK DIAGRAM DOUT1 DOUT2 DOUT3 XSYNC RC LPF AOUT1+ ∆-Σ DA CONV. LPF Expander BCLK P/S AOUT1– AOUT2+ ∆-Σ DA CONV. LPF RCONT RC LPF Expander RSYNC DIN1 DIN2 DIN3 RC LPF AOUT3+ ∆-Σ DA CONV. LPF Expander AOUT2– AOUT3– SGC VDDA VDD AG DG SG Gen. Power Cont. & DLL & Clock Gen. MCKSEL MCK PDN PDN1 PDN2 PDN3 2/20 PEDL7048-01-01 1Semiconductor ML7048-01 34 PDN 35 PDN1 36 PDN2 37 PDN3 39 DG 38 VDD 40 AG 41 AOUT1– 42 AOUT1+ 43 GSX1 44 AIN1– PIN CONFIGURATION (TOP VIEW) AIN1+ 1 33 TEST3 VDDA 2 32 DOUT3 AOUT2– 3 31 DOUT2 AOUT2+ 4 30 DOUT1 GSX2 5 29 DG AIN2– 6 28 DIN3 AG 7 27 DIN2 AIN2+ 8 26 DIN1 VDDA 9 25 RSYNC SGC 10 24 XSYNC AIN3+ 11 P/S 22 MCK 20 BCLK 21 MCKSEL 19 AG 16 DG 17 VDD 18 AOUT3– 15 AOUT3+ 14 GSX3 13 AIN3– 12 23 TEST2 44-Pin Plastic QFP 3/20 PEDL7048-01-01 1Semiconductor ML7048-01 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Symbol AIN1+ VDDA AOUT2– AOUT2+ GSX2 AIN2– AG AIN2+ VDDA SGC AIN3+ AIN3– GSX3 AOUT3+ AOUT3– AG DG VDD MCKSEL MCK BCLK Type I — O O O I — I — O I I O O O — — — I I I 22 P/S I 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 TEST2 XSYNC RSYNC DIN1 DIN2 DIN3 DG DOUT1 DOUT2 DOUT3 TEST3 PDN PDN1 PDN2 PDN3 VDD DG AG AOUT1– AOUT1+ GSX1 AIN1– I I I I I I — O O O I I I I I — — — O O O I Description Channel-1 Transmit Amp Non-inverting Input Analog Power Supply Channel-2 Receive Amp Inverting Output Channel-2 Receive Amp Non-inverting Output Channel-2 Transmit Amp Output Channel-2 Transmit Amp Inverting Input Analog Ground Channel-2 Transmit Amp Non-inverting Input Analog Power Supply Analog Signal Ground Channel-3 Transmit Amp Non-inverting Input Channel-3 Transmit Amp Inverting Input Channel-3 Transmit Amp Output Channel-3 Receive Amp Non-inverting Output Channel-3 Receive Amp Inverting Output Analog Ground Digital Ground Digital Power Supply Master Clock Frequency Select Signal Master Clock PCM Signal Shift Clock 3-Channel Independent/3-Channel Continuous Serial Interface Select Signal Test Control Signal 2 Transmit Sync Signal Receive Sync Signal Channel-1 PCM Signal Input Channel-2 PCM Signal Input Channel-3 PCM Signal Input Digital Ground Channel-1 PCM Signal Output Channel-2 PCM Signal Output Channel-3 PCM Signal Output Test Control Signal 3 Power Down Control Signal Channel-1 Power Down Control Signal Channel-2 Power Down Control Signal Channel-3 Power Down Control Signal Digital Power Supply Digital Ground Analog Ground Channel-1 Receive Amp Inverting Output Channel-1 Receive Amp Non-inverting Output Channel-1 Transmit Amp Output Channel-1 Transmit Amp Inverting Input 4/20 PEDL7048-01-01 1Semiconductor ML7048-01 PIN FUNCTIONAL DESCRIPTION AIN1+, AIN2+, AIN3+, AIN1–, AIN2–, AIN3–, QSX1, GSX2, GSX3 AIN1+, AIN1– and GSX1 are the transmit inputs and transmit level adjustment pins for Channel 1, AIN2+, AIN2– and GSX2 are those for Channel 2. AIN3+, and AIN3– and GSX3 are those for Channel 3. AIN1+, AIN2+ and AIN3+ are non-inverting inputs for the op-amp. AIN1–, AIN2– and AIN3– are inverting inputs for the op-amp. GSX1, GX2 and GX3 are the outputs for op-amp. Do the level adjustment as described below. If AINn– and AINn+ are not used, connect AINn– to GSXn and AINn+ to SGC. During power saving and power down modes, GSX1, GSX2, and GSX3 outputs are at a high impedance. During power down mode in each channel, the GSX output of a channel in power down mode is at a high impedance. GSXn Channel n analog input R2n C1n R1n AINn– AINn+ SGC SG Gen. Channel n gain Gain = R2n/R1n ≤ 10 R1: Variable R2 > 20 kΩ C1n > 1/(2 × 3.14 × 30 × R1n) R1 + R2 < 500 kΩ AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, AOUT3– AOUT1+ and AOUT1– are the receive analog output pins for Channel 1, AOUT2+ and AOUT2– are those for Channel 2, and AOUT3+ and AOUT3– are those for Channel 3. AOUT1– is the inverting output for AOUT1+, AOUT2– is for AOUT2+, and AOUT3– is for AOUT3+. A load of 600Ω or more can be driven between AOUT1+ and AOUT1–, AOUT2+ and AOUT2–, and AOUT3+ and AOUT3–. The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG) when the digital signal of 3.17 dBm0 is input to DIN1, DIN2, and DIN3. During power saving and power down modes, the AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, and AOUT3– outputs are at a high impedance. During power down mode in each channel, the AOUTn+ and AOUTn– of a channel in power down are at a high impedance. SGC Bypass capacitor pin used to generate the signal ground voltage level. Connect a 1 µF capacitor with excellent high frequency characteristics between the SGC pin and the AG pin. MCK Master clock input pin. The frequency is 12.288 MHz or 15.360 MHz. The frequency is switched by MCKSEL. This master clock may be asynchronous with BCLK, RSYNC, and XSYNC. MCKSEL Master clock frequency select signal input pin. Input a 12.288 MHz clock to the MCK pin when MCKSEL is “0”. Input a 15.360 MHz clock to the MCK pin when MCKSEL is “1”. PDN Power down control signal input pin. When PDN is “0”, all circuits are in power down mode. 5/20 PEDL7048-01-01 1Semiconductor ML7048-01 PDN1, PDN2, PDN3 PDN1 is the power down control signal input pin for Channel 1, PDN2 is for Channel 2, and PDN3 is for Channel 3. When PDN is “1” and PDN1, PDN2, and PDN3 are “0s”, the corresponding channel goes in power saving mode (all analog circuits except the reference voltage generation circuit are being powered down). P/S Signal input pin for selecting either 3-channel independent serial interface or 3-channel continuous serial interface. When P/S is “0”, 3-channel independent serial interface, in which the input/output of each channel is made through DIN1 to 3 and DOUT1 to 3 independently, is selected. When P/S is “1”, 3-channel continuous serial interface, in which the input/output of each channel is made from DIN1 and DOUT1 continuously. When 3-channel continuous serial interface is selected, DOUT2 and DOUT3 pins are at a high impedance. Connect the DIN2 and DIN3 pins to the digital ground (DG). BCLK PCM signal shift clock input pin for DIN1, DIN2, DIN3, DOUT1, DOUT2, and DOUT3. The frequency is equal to the data rate. The clock frequencies available are 64, 96, 128, 192, 256, 384, 512, 1024, 1536, and 2048 kHz. When P/S is “1” and 3-channel continuous serial interface is selected, the frequencies of 64, 96, and 128 kHz cannot be used. RSYNC Receive synchronizing signal input pin. This signal selects necessary 8-bit PCM data from serial PCM signals for the DIN1, DIN2 and DIN3 pins. This synchronizing signal must be synchronized in phase with BCLK (generated from BCLK). XSYNC Transmit synchronizing signal input pin. This synchronizing signal must be synchronized in phase with BCLK (generated from BCLK). The DPLL circuit is synchronized in phase with XSYNC. DIN1, DIN2, DIN3 When P/S is “0” and 3-channel independent serial interface is selected, DIN1 is the PCM signal input pin for Channel 1, DIN2 is for Channel 2, and DIN3 is for Channel 3. When P/S is “1” and 3-channel continuous serial interface is selected, DIN1 is the PCM signal input pin for each channel and data is input in the order of Channel 1, Channel 2 and Channel 3. At that time, connect DIN2 and DIN3 to the digital ground (DG). The PCM signal data rate is equal to the frequency of BCLK. The PCM signal is shifted at the falling edge of BCLK. The MSD of PCM data is identified at the rising edge of RSYNC. 6/20 PEDL7048-01-01 1Semiconductor ML7048-01 DOUT1, DOUT2, DOUT3 When P/S is “0” and 3-channel independent serial interface is selected, DOUT1 is the PCM signal output pin for Channel 1, DOUT2 is for Channel 2, and DOUT3 is for Channel 3. When P/S is “1” and 3-channel continuous serial interface is selected, DOUT1 is the PCM signal output pin for each channel and data is output in the order of Channel 1, Channel 2, and Channel 3. At that time, DOUT2 and DOUT3 are at a high impedance state. The PCM signal is sequentially output starting from MSD in synchronization with the rise of BCLK. (MSD may be output at the rising edge of XSYNC depending on the timing of BCLK and XSYNC.) These pins are at a high impedance during the time other than PCM data output bits. These pins also are at a high impedance during power down mode and power saving mode. These pins must be internally connected to pull-up resistors because the output form is of open-drain. For coding law, the ITU-T Recommend µ-law is employed. PCMIN / PCMOUT µ-law Input/output level M S D D 2 D 3 D 4 D 5 D 6 D 7 D 8 + full scale 1 0 0 0 0 0 0 0 +0 1 1 1 1 1 1 1 1 –0 0 1 1 1 1 1 1 1 – full scale 0 0 0 0 0 0 0 0 Table 1 Coding law VDDA +5V power supply for analog signal circuits. Use an analog power supply system of equipment used. Connect a bypass capacitor of 1 µF with excellent high frequency characteristics and a capacitor of 10 µF between this pin and the AG pin. AG Ground pin for analog signal circuits. VDD +5V power supply pin for digital signal circuits. Although this pin and VDDA are not connected internally, these pins must be connected on the printed circuit board. DG Ground pin for digital signal circuits. Although this pin and AG are not connected internally, these pins must be connected on the printed circuit board. TEST2, TEST3 These pins are used for device test. These device test pins must be connected to the DG pin. 7/20 PEDL7048-01-01 1Semiconductor ML7048-01 PDN PDNn DOUTn 0 0/1 H 1 0 11111111 1 1 Converted output Table 2 Power Control vs. DOUT Output Status GSX1, AOUT1± GSX2, AOUT2± GSX3, AOUT3± SGC 0/1 High impedance High impedance High impedance Connected to AG with a resistor of about 50 kΩ 0 0 High impedance High impedance High impedance Operating 1 0/1 0/1 Operating Depending on PDN2 Depending on PDN3 Operating 1 0/1 1 0/1 Depending on PDN1 Operating Depending on PDN3 Operating 1 0/1 0/1 1 Depending on PDN1 Depending on PDN2 Operating Operating PDN PDN1 PDN2 PDN3 0 0/1 0/1 1 0 1 Table 3 Power Control vs. Analog Output Status 8/20 PEDL7048-01-01 1Semiconductor ML7048-01 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — –0.3 to +7.0 V — –0.3 to VDD+0.3 V Digital Input Voltage VDIN — –0.3 to VDD+0.3 V Storage Temperature TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Symbol Condition Min. Typ. Max. Unit VDD Voltage must be fixed 4.75 5.0 5.25 V Operating Temperature TOP — –30 — +85 °C Analog Input Voltage VAIN Gain = 1 — — 2.26 VPP High Level Input Voltage VIH 2.2 — VDD V Low Level Input Voltage VIL 0 — 0.8 V MCKSEL = “0” –100ppm 12.288 +100ppm MCKSEL = “1” –100ppm 15.360 +100ppm All Digital Input Pins MCK Frequency FMCK BCLK Frequency FBCLK BCLK Sync Pulse Frequency FSYNC XSYNC, RSYNC — 8 — kHz Clock Duty Ratio DCLK MCK, BCLK 40 50 60 % — — 50 ns Digital Input Rise Time TIR All Digital Input Pins 64k, 128k, 256k, 512k, 1.024M, 2.048M 96k, 192k, 284k, 768k, 1.536M MHz Hz Digital Input Fall Time TIF — — 50 ns Transmit Sync Pulse Setting TXS BCLK to XSYNC 50 — — ns Time TSX XSYNC to BCLK 50 — — ns Receive Sync Pulse Setting TRS BCLK to RSYNC 50 — — ns Time TSR RSYNC to BCLK 50 — — ns Sync Pulse Width TWS XSYNC, RSYNC 1 BCLK — 100 µs DIN Set-up Time TDS DIN1 to 3 50 — — ns DIN Hold Time TDH DIN1 to 3 50 — — ns RDL Pull-up Resistor, DOUT1 to 3 0.5 — — kΩ CDL DOUT1 to 3 — — 50 pF Allowable Jitter Width TJT XSYNC, RSYNC — — 500 ns Bypass Capacitor for SGC CSG Between SGC and AG 1 — — µF Digital Output Load 9/20 PEDL7048-01-01 1Semiconductor ML7048-01 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit IDD1 3CH Operating Mode, No Signal PDN = “1”, PDN1 = PDN2 = PDN3 = “1” — 28.0 33.0 mA IDD2 Power Saving Mode, PDN = “1”, PDN1 = PDN2 = PDN3 = “0” — 3.0 5.0 mA IDD3 Power Down Mode, PDN = “0” All inputs fixed — 0.01 0.05 mA High Level Input Leakage Current IIH All Digital Input Pins VI = VDD — — 10 µA Low Level Input Leakage Current IIL All Digital Input Pins VI = 0 V — — 10 µA VOL DOUT1 to 3, Pull-up = 0.5 kΩ 0 0.2 0.4 V Digital Output Leakage Current IO DOUT1 to 3, High Impedance State — — 10 µA Input Capacitance CIN — — 5 — pF Power Supply Current Digital Output Low Voltage Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter SGC Rise Time Symbol Condition Min. Typ. Max. Unit TSGC SGC to AG 0.1 µF Rise time to 90% of max. level — — 100 ms Transmit Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Input Resistance RINX AIN1, AIN2 10 — — MΩ Output Load Resistance RLGX GSX1, GSX2 20 — — kΩ Output Load Capacitance CLGX with respect to SG voltage — — 30 pF Output Amplitude VOGX *1 –1.13 — +1.13 V Offset Voltage VOSGX –50 — +50 mV Gain = 1 *1 –2.73 dBm (600Ω) = 3.17 dBm0 (µ-law) = 2.26 VPP 10/20 PEDL7048-01-01 1Semiconductor ML7048-01 Receive Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Output Load Resistance RLAO AOUT1±, AOUT2± AOUT3± with respect to inverting output 0.6 — — kΩ Output Load Capacitance CLAO AOUT1±, AOUT2±, AOUT3± — — 50 pF Output Amplitude VOAO AOUT1±, AOUT2±, AOUT3±, RLAO=0.6 kΩ with respect to inverting output –1.7 — +1.7 V Offset Voltage VOSAO AOUT1±, AOUT2±, AOUT3± with respect to SG voltage –100 — +100 mV AC Characteristics (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter Transmit Frequency Response Receive Frequency Response Transmit Signal to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Receive Gain Tracking Idle Channel Noise Symbol Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 SDT1 SDT2 SDT3 SDT4 SDT5 SDR1 SDR2 SDR3 SDR4 SDR5 GTT1 GTT2 GTT3 GTT4 GTT5 GTR1 GTR2 GTR3 GTR4 GTR5 NIDLET NIDLER Freq. 60 300 1020 3000 3300 3400 100 1020 3000 3300 3400 1020 1020 1020 1020 — — Condition Level Min. 25 –0.15 0 (Attenuation) 0 (Attenuation) 3 0 –30 –40 –45 3 0 –30 –40 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 — — *2 *2 –0.15 –0.15 0 –0.15 –0.15 –0.15 0 36 36 36 30 25 36 36 36 30 25 –0.2 –0.2 –0.6 –1.2 –0.2 DIN to AOUTn AINn = SG *2 DIN = 0 code *2 –0.2 –0.6 –1.2 — — Typ. 45 +0.15 Reference +0.02 +0.1 0.6 +0.04 Reference +0.07 +0.20 0.6 43 41 39 34 31 43 41 39 34 31 +0.02 Reference +0.06 +0.3 +0.5 0 Reference –0.02 –0.1 –0.2 –76 –88 Max. Unit — +0.20 +0.20 +0.80 0.80 +0.2 dB +0.20 +0.80 0.8 — — — — — — — — — — +0.2 dB +0.2 +0.6 +1.2 +0.2 dB +0.2 +0.6 +1.2 –72 –82 dB dB dB dBrn0p *2 P-message Filter is used 11/20 PEDL7048-01-01 1Semiconductor ML7048-01 AC Characteristics (Continued) (VDD = 4.75 to 5.25 V, Ta = –30 to +85°C) Parameter Absolute Level (Initial Difference) Absolute level (Deviation of Temperature and power) Absolute Delay Transmit Group Delay Receive Group Delay Cross Talk Attenuation Symbol Condition Freq. Level AVT AVR 1020 0 AVTT VDD = 4.75 to 5.25 V Ta = –40 to 85°C AVRT 0 A to A Mode BCLK = 2048 kHz Typ. Max. 0.535 0.555 0.574 0.806 0.835 0.864 –0.3 — 0.3 –0.3 — 0.3 — 0.54 0.6 1020 TGD T1 500 — 0.26 0.75 TGD T2 600 — 0.16 0.35 TGD T3 1000 — 0.02 0.125 TGD T4 2600 — 0.05 0.125 TGD T5 2800 — 0.07 0.75 TGD R1 500 — 0.00 0.75 TGD R2 600 — 0.00 0.35 TGD R3 1000 — 0.00 0.125 TGD R4 2600 — 0.06 0.125 TGD R5 2800 — 0.09 0.75 Trans to Receive 80 85 — Receive to Trans 75 80 — Channel to Channel 80 85 — 0 0 CRT CRR *3 1020 0 *3 Unit Vrms TD CRCH Discrimination VDD = 5 V, Ta = 25°C VDD = 5 V, Ta = 25°C Min. dB ms ms ms dB DIS 4.6 to 72k 0 0 to 4 kHz 30 32 — dB Out of Band Spurious OBS 300 to 3.4k 0 4.6 kHz to 1000 kHz — –37.5 –35 dB Signal Frequency Distortion 1020 0 0 to 4 kHz — –50 –40 SFDR — –48 –40 –4 2 fa - fb — –52 –40 — –52 –40 40 44 — 50 55 — 40 45 — 50 56 — 20 — 100 20 — 100 TXD2 DOUTn Pull-up resister = 0.5 kΩ CL = 50 pF and 1 LSTTL 20 — 100 DOUT Signal Output Delay Time TDDO Signal rise time after power on by PDNn *5 — 4 — ms AOUT Signal Output TDAO Signal rise time after power on by PDNn *5 — 4 — ms Intermoduration Distortion Power Supply Noise Rejection Ratio Digital Output Delay Time SFDT IMDT fa = 470 IMDR fb = 320 PSRT1 0 to 4k PSRT2 4 to 50k 100 PSRR1 0 to 4k mVrms PSRR2 4 to 50k TSD TXD1 *4 dBm0 dBm0 dB ns *3 Minimum value of the group delay distortion *4 The measurement under idle channel noise *5 The rise time of SGC by PDN is not included. DOUT and AOUT will not rise before inputting XSYNC. 12/20 PEDL7048-01-01 1Semiconductor ML7048-01 TIMING DIAGRAM BCLK XSYNC 1 TWS TSD MSD TXD1 DOUTn 2 3 4 5 6 7 8 TSX TXS D2 TXD2 D4 D3 D5 D6 D7 D8 Note: In the above diagram, 3-channel independent serial interface is selected. When 3-channel continuous serial interface is selected, 24-bit data is output from DOUT1 in the order of Channel 1, Channel 2, and Channel 3. Figure 1 Transmit side Timing Diagram BCLK RSYNC DINn 1 TRS 2 3 4 5 6 7 8 TSR TWS MSD D2 TDS TDH D3 D4 D5 D6 D7 D8 Note: In the above diagram, 3-channel independent serial interface is selected. When 3-channel continuous serial interface is selected, 24-bit data is input to DIN1 in the order of Channel 1, Channel 2, and Channel 3. Figure 2 Receive Side Timing Diagram PDN SGC TSGC PDNn DOUTn TDDO High Impedance AOUTn± TDAO SG Level Note: DOUT and AOUT will not rise before inputting XSYNC. Figure 3 SGC, DOUT, AOUT Outputs Timing 13/20 PEDL7048-01-01 1Semiconductor ML7048-01 APPLICATION CIRCUITS When 3-channel independent serial interface is selected +5 V ML7048-01 GSX1 Channel 1 analog input Channel 2 analog input Channel 3 analog input 20 kΩ 1 µF 20 kΩ 20 kΩ 1 µF 20 kΩ 20 kΩ 1 µF 20 kΩ AIN1– DOUT1 AIN1+ DOUT2 GSX2 DOUT3 AIN2– AIN2+ DIN1 GSX3 DIN2 AIN3– DIN3 AIN3+ MCK Channel 1 analog output Channel 1 analog inverting output AOUT1+ BCLK AOUT1– XSYNC Channel 1 PCM Signal Output Channel 2 PCM Signal Output Channel 3 PCM Signal Output Channel 1 PCM Signal Input Channel 2 PCM Signal Input Channel 3 PCM Signal Input Master clock Input Bit Clock Input Sync Signal Input RSYNC Channel 2 analog output AOUT2+ AOUT2– Channel 2 analog inverting output PDN PDN1 Channel 3 analog output Channel 3 analog inverting output AOUT3+ PDN2 AOUT3– PDN3 Power Down Control Channel 1 Power Down Control Channel 2 Power Down Control Channel 3 Power Down Control SGC 1 µF +5 V VDD 10 µF 0V VDDA 1 µF MCKSEL P/S AG TEST2 DG TEST3 * When MCK is 15.360 MHz, connect MCKSEL to VDD. 14/20 PEDL7048-01-01 1Semiconductor ML7048-01 When 3-channel continuous serial interface is selected +5 V ML7048-01 GSX1 Channel 1 analog input Channel 2 analog input Channel 3 analog input 20 kΩ 1 µF 20 kΩ 20 kΩ 1 µF 20 kΩ 20 kΩ 1 µF 20 kΩ AIN1– DOUT1 AIN1+ DOUT2 GSX2 DOUT3 PCM signal Output AIN2– AIN2+ DIN1 GSX3 DIN2 AIN3– DIN3 PCM Signal Input AIN3+ MCK Channel 1 analog output AOUT1+ BCLK Channel 1 analog inverting output AOUT1– XSYNC Channel 2 analog output AOUT2+ Channel 2 analog inverting output AOUT2– Channel 3 analog output AOUT3+ PDN2 Channel 3 analog inverting output AOUT3– PDN3 Master clock Input Bit Clock Input Sync Signal Input RSYNC PDN PDN1 Power Down Control Channel 1 Power Down Control Channel 2 Power Down Control Channel 3 Power Down Control SGC 1 µF +5 V VDD 10 µF 0V VDDA 1 µF MCKSEL P/S AG TEST2 DG TEST3 * When MCK is 15.360 MHz, connect MCKSEL to VDD. 15/20 PEDL7048-01-01 1Semiconductor ML7048-01 APPLICATION NOTE Pull-up Resistor for the DOUT Pin Use an optimal value of pull-up resistor for the DOUT pin considering the frequency and load capacitance of BCLK used. If a small value of pull-up resistor is used, the distortion characteristics may be degraded and current consumption also may be increased. Select a pull-up resistance referencing the following calculation conditions. Calculation conditions: If SYNC and BCLK have risen and data is looped between DOUT and DIN, data can be normally input and output. R PULL 1 − 20ns 4 × FBCLK = (Ω ) CL FBCLK : Frequency of BCLK CL : Load capacitance of DOUTn 20ns : Internal delay XSYNC, RSYNC BCLK t = RPULL × CL DOUTn Calculation example: BCLK (Hz) RPULL (kΩ) CL = 10 pF CL = 20 pF CL = 50 pF CL = 100 pF 64k 388.6 194.3 77.7 38.9 128k 193.3 96.7 38.7 19.3 256k 95.7 47.8 19.1 9.7 512k 46.8 23.4 9.4 4.7 1.024M 22.4 11.2 4.5 2.2 2.048M 10.2 5.1 2.0 1.0 Selection of resistance value: If the calculated resistance is more than 100 kΩ, use a 100 kΩ resistor. Since the calculated resistance +10% is allowable, you can use a typical resistance a little higher than the calculated resistance. 16/20 PEDL7048-01-01 1Semiconductor ML7048-01 Cross-talk between Channels This device contains a 3-channel CODEC. The circuits and layout of this device have been designed so that the internal cross-talk between channels is to be as small as possible. The pins also are carefully placed. It is required to design your printed circuit board considering the following descriptions. Transmit Side: AN1+, AN1–, AIN2+, AIN2–, AIN3+, and AIN3– are the input pins for op-amps with a high resistance. Consequently, if the wiring patterns of these pins are close to the wiring patterns of other signals, cross-talk may be caused. And a longer wiring pattern generates noises. The wiring pattern must be as short as possible and must not be close to the patterns of other signals. In addition, connect a ground pattern between these wiring patterns and the wiring patterns of other signals. AIN1+, AIN2+, and AIN3+ are connected to SGC. Connect a bypass capacitor to the SGC pin as closely as possible and place a wiring pattern for AIN+, AIN2+, and AIN3+ separately. Receive Side: AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, and AOUT3– are the outputs for op-amps with a low resistance. Although the cross-talk caused by wiring patterns is small when compared with the transmit side, Avoid placing the wiring patterns of these pins closely to the wiring patterns of other signals. RSYNC Timing Data that is input from DINn is latched at the rising edge of BCLK corresponding to the trailing edge of the last bit. If the latch timing and the internal processing timing (25.390 µs from the rise of XSYNC) are overlapped, data slip (data is deleted or the same data is output twice) data error may occur. Set the timing so that the latch timing and internal processing timing are not within ±500 ns considering the jitter of DPLL. XSYNC RSYNC BCLK DINn 25.390 µs Last bit Latch timing Internal processing timing Relationship between MCK and BCLK, XSYNC, RSYNC Although MCK may be asynchronous with BCLK, XSYNC, and RSYNC, take note of the following. If MCK and BCLK, XSYNC, RSYNC are generated from the different oscillation sources (ex. two crystal oscillators are used) with the same frequency, the difference in frequency may cause a beat. If this beat frequency is within the band, the characteristics may be degraded. 17/20 PEDL7048-01-01 1Semiconductor ML7048-01 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low impedance. • Connect the VDDA pin to the VDD pin as closely as possible and connect them to the analog power supply at a low impedance. • Directly mount this device onto the printed circuit board without using an IC socket. Unless unavoidable, use short lead type socket. • When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. • Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device. 18/20 PEDL7048-01-01 1Semiconductor ML7048-01 PACKAGE DIMENSIONS (Unit: mm) QFP44-P-910-0.80-2K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.41 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/20 PEDL7048-01-01 1Semiconductor ML7048-01 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 20/20