PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT821T/823T/825T (25Ω Ω Series) PI74FCT2821T/2823T 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS Bus Interface Registers Product Features: • PI74FCT821T/823T/825T/2821T/2823T is pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption • 25Ω series resistor on all outputs (FCT2XXX only) • TTL input and output levels • Low ground bounce outputs • Extremely low static power • Hysteresis on all inputs • Industrial operating temperature range: –40°C to +85°C • Packages available: – 24-pin 300 mil wide plastic DIP (P) – 24-pin 150 mil wide plastic QSOP (Q) – 24-pin 150 mil wide plastic TQSOP (R) – 24-pin 300 mil wide plastic SOIC (S) • Device models available upon request Product Description: Pericom Semiconductor’s PI74FCT series of logic circuits are produced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades. All PI74FCT2XXX devices have a built-in 25-ohm series resistor on all outputs to reduce noise because of reflections, thus eliminating the need for an external terminating resistor. The PI74FCT821T/2821T is a 10-bit wide register designed with ten D-type flip-flops with a buffered common clock and buffered 3-state outputs. The PI74FCT823/2823T is a 9-bit wide register designed with Clock Enable and Clear. The PI74FCT825T is an 8-bit wide register with all PI74FCT823T controls plus multiple enables. When output enable (OE) is LOW, the outputs are enabled. When OE is HIGH, the outputs are in the high impedance state. Input data meeting the setup and hold time requirements of the D inputs is transferred to the Y outputs on the LOW-to-HIGH transition of the clock input. Logic Block Diagram D0 D1 D2 D3 D4 D5 DN-1 DN EN CLR D CL Q D CL Q D CP Q CP Q CL Q D CP Q CL Q D CP Q CL Q D CP Q CL Q D CP Q CL Q D CP Q CL Q CP Q CP OE Y0 Y1 Y2 Y3 Y4 Y5 YN-1 YN OE1 OE2 OE3 PI74FCT825 Only 1 PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT821/2821T Product Pin Configuration OE 1 24 Vcc D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 19 Y4 18 Y5 17 Y6 24-PIN P24 Q24 R24 S24 D4 6 D5 7 D6 8 D7 9 16 Y7 D8 10 15 Y8 D9 11 14 Y9 GND 12 13 CP Product Pin Description Pin Name OE CP DN YN CLR EN GND VCC Description Output Enable Input (Active LOW) Clock Pulse for the register. Enters data on LOW-to-HIGH transition Data Inputs 3-State Outputs Clear Input (Active LOW) (823/825/2823 Only) Clock Enable Input (Active LOW) Ground Power PI74FCT821/823/825/2821/2823T Truth Table(1) PI74FCT823/2823T Product Pin Configuration Inputs OE1 1 24 Vcc D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 Y7 D8 10 15 Y8 CLR 11 14 EN GND 12 13 CP 24-PIN P24 Q24 R24 S24 Function CLR High-Z H H Clear L L Hold H H Load H H H H 1. PI74FCT825T Product Pin Configuration OE1 1 24 OE2 2 23 OE3 D0 3 22 Y0 D1 4 21 Y1 D2 5 20 Y2 D3 6 19 Y3 D4 7 18 Y4 D5 8 17 Y5 D6 9 16 Y6 D7 10 15 Y7 CLR 11 14 EN GND 12 13 CP 24-PIN P24 Q24 R24 S24 Vcc 2 EN OE L H L H X H X L H H H L L H L H L L L L Outputs Internal CP ↑ ↑ X X X X ↑ ↑ ↑ ↑ DN L H X X X X L H L H YN Z Z Z L Z NC Z Z L H QN L H L L NC NC L H L H H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance NC = No Change ↑ = LOW-to-HIGH transition PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................................. –65°C to +150°C Ambient Temperature with Power Applied ................................. -40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ....... –0.5V to +7.0V DC Input Voltage ......................................................................... –0.5V to +7.0V DC Output Current ................................................................................... 120 mA Power Dissipation ......................................................................................... 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 5%) Parameters Description Test Conditions(1) Min. Typ(2) Max. Units VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –15.0 mA 2.4 3.0 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 48 mA 0.3 0.50 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 12 mA (25Ω Series) 0.3 0.50 V VIH Input HIGH Voltage Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level IIH Input HIGH Current VCC = Max. IIL Input LOW Current IOZH High Impedance IOZL Output Current VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA IOFF Power Down Disable VCC = GND, VOUT = 4.5V IOS Short Circuit Current VCC = Max.(3), VOUT = GND VH Input Hysteresis 2.0 V 0.8 V VIN = VCC 1 µA VCC = Max. VIN = GND –1 µA VCC = MAX. VOUT = 2.7V 1 µA VOUT = 0.5V –1 µA –0.7 –1.2 V — — 100 µA –60 –120 mA 200 mV Capacitance (TA = 25°C, f = 1 MHz) Parameters(4) Description Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. 3 PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Test Conditions(1) Parameters Description Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 500 µA ∆ICC Supply Current per Input @ TTL HIGH VCC = Max. VIN = 3.4V(3) 0.5 2.0 mA ICCD Supply Current per Input per MHz(4) VCC = Max., Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND 0.15 0.25 mA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = EN = GND fI = 5 MHZ One Bit Toggling VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = EN = GND Eight Bits Toggling fI = 2.5 MHZ 50% Duty Cycle VIN = VCC VIN = GND 1.5 3.5(5) mA VIN = 3.4V VIN = GND 2.0 5.5(5) VIN = VCC VIN = GND 3.8 7.3(5) VIN = 3.4V VIN = GND 6.0 16.3(5) Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4 V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 4 PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT821/2821T Switching Characteristics over Operating Range 821AT/2821AT 821BT/2821BT Com. Parameters tPLH tPHL tSU tH tSU tH tPHL tREM tW tW tPZH tPZL tPHZ tPLZ 821CT/2821CT Com. Com. Description Conditions(1) Min Max Min Max Min Max Unit Propagation Delay CP to YN (OE = LOW) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω 1.5 10.0 1.5 7.5 1.5 6.0 ns 1.5 20.0 1.5 15.0 1.5 12.5 ns 4.0 — 3.0 — 3.0 — ns 2.0 — 1.5 — 1.5 — ns 4.0 — 3.0 — 3.0 — ns 2.0 — 0 — 0 — ns 1.5 14.0 1.5 9.0 1.5 8.0 ns 6.0 — 6.0 — 6.0 — ns 7.0 — 5.0 — 6.0 — ns 6.0 — 6.0 — 6.0 — ns 1.5 11.5 1.5 8.0 1.5 7.0 ns 1.5 23.0 1.5 15.0 1.5 12.5 ns 1.5 7.0 1.5 6.5 1.5 6.2 ns 1.5 8.0 1.5 7.5 1.5 6.5 ns Setup Time HIGH or LOW, DN to CP Hold Time HIGH or LOW, DN to CP Setup Time HIGH or LOW, EN to CP Hold Time HIGH or LOW, EN to CP Propagation Delay, CLR to YN Recovery Time,(3) CLR to CP Clock Pulse Width(3) HIGH or LOW CLR Pulse Width(3) LOW Output Enable Time OE to YN Output Disable Time(3) OE to YN CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 5 PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT823/2823T Switching Characteristics over Operating Range 823AT/2823AT 823BT/2823BT Com. Parameters tPLH tPHL tSU tH tSU tH tPHL tREM tW tW tPZH tPZL tPHZ tPLZ 823CT/2823CT Com. Com. Description Conditions(1) Min Max Min Max Min Max Unit Propagation Delay CP to YN (OE = LOW) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω 1.5 10.0 1.5 7.5 1.5 6.0 ns 1.5 20.0 1.5 15.0 1.5 12.5 ns 4.0 — 3.0 — 3.0 — ns 2.0 — 1.5 — 1.5 — ns 4.0 — 3.0 — 3.0 — ns 2.0 — 0 — 0 — ns 1.5 13.0 1.5 9.0 1.5 8.0 ns 6.0 — 6.0 — 6.0 — ns 7.0 — 5.0 — 6.0 — ns 6.0 — 6.0 — 6.0 — ns 1.5 11.5 1.5 8.0 1.5 7.0 ns 1.5 23.0 1.5 15.0 1.5 12.5 ns 1.5 7.0 1.5 6.5 1.5 6.2 ns 1.5 8.0 1.5 7.5 1.5 6.5 ns Setup Time HIGH or LOW, DN to CP Hold Time HIGH or LOW, DN to CP Setup Time HIGH or LOW, EN to CP Hold Time HIGH or LOW, EN to CP Propagation Delay, CLR to YN Recovery Time,(3) CLR to CP Clock Pulse Width (3) HIGH or LOW CLR Pulse Width (3) LOW Output Enable Time OE to YN Output Disable Time(3) OE to YN CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 6 PS2023A 03/11/96 PI74FCT821T/823T/825T (25Ω Ω Series) P174FCT2821T/2823T BUS INTERFACE REGISTERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT825T Switching Characteristics over Operating Range 825AT 825BT Com. Parameters tPLH tPHL tSU tH tSU tH tPHL tREM tW tW tPZH tPZL tPHZ tPLZ 825CT Com. Com. Description Conditions(1) Min Max Min Max Min Max Unit Propagation Delay CP to YN (OE = LOW) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω 1.5 10.0 1.5 7.5 1.5 6.0 ns 1.5 20.0 1.5 15.0 1.5 12.5 ns 4.0 — 3.0 — 3.0 — ns 2.0 — 1.5 — 1.5 — ns 4.0 — 3.0 — 3.0 — ns 2.0 — 0 — 0 — ns 1.5 13.0 1.5 9.0 1.5 8.0 ns 6.0 — 6.0 — 6.0 — ns 7.0 — 5.0 — 6.0 — ns 6.0 — 6.0 — 6.0 — ns 1.5 11.5 1.5 8.0 1.5 7.0 ns 1.5 23.0 1.5 15.0 1.5 12.5 ns 1.5 7.0 1.5 6.5 1.5 6.2 ns 1.5 8.0 1.5 7.5 1.5 6.5 ns Setup Time HIGH or LOW, DN to CP Hold Time HIGH or LOW, DN to CP Setup Time HIGH or LOW, EN to CP Hold Time HIGH or LOW, EN to CP Propagation Delay, CLR to YN Recovery Time, CLR to CP Clock Pulse Width HIGH or LOW CLR Pulse Width(3) LOW Output Enable Time OE to YN Output Disable Time(3) OE to YN CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS2023A 03/11/96