Order this document by MC14489/D SEMICONDUCTOR TECHNICAL DATA P SUFFIX PLASTIC DIP CASE 738 CMOS The MC14489 is a flexible light–emitting–diode driver which directly interfaces to individual lamps, 7–segment displays, or various combinations of both. LEDs wired with common cathodes are driven in a multiplexed–by–5 fashion. Communication with an MCU/MPU is established through a synchronous serial port. The MC14489 features data retention plus decode and scan circuitry, thus relieving processor overhead. A single, current–setting resistor is the only ancillary component required. A single device can drive any one of the following: a 5–digit display plus decimals, a 4–1/2–digit display plus decimals and sign, or 25 lamps. A special technique allows driving 5 1/2 digits; see Figure 16. A configuration register allows the drive capability to be partitioned off to suit many additional applications. The on–chip decoder outputs 7–segment–format numerals 0 to 9, hexadecimal characters A to F, plus 15 letters and symbols. The MC14489 is compatible with the Motorola SPI and National MICROWIRE serial data ports. The chip’s patented BitGrabber registers augment the serial interface by allowing random access without steering or address bits. A 24–bit transfer updates the display register. Changing the configuration register requires an 8–bit transfer. • • • • • • • • • • Operating Voltage Range of Drive Circuitry: 4.5 to 6 V Operating Junction Temperature Range: – 40° to 130°C Current Sources Controlled by Single Resistor Provide Anode Drive Low–Resistance FET Switches Provide Direct Common Cathode Interface Low–Power Mode (Extinguishes the LEDs) and Brightness Controlled via Serial Port Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI in Low–Power Mode Power–On Reset (POR) Blanks the Display on Power–Up, Independent of Supply Ramp Up Time May Be Used with Double–Heterojunction LEDs for Optimum Efficiency Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.) See Application Note AN431, Temperature Measurement and Display Using the MC68HC05B4 and the MC14489 and Engineering Bulletin EB153, Driving a Seven–Segment Display with the NEURON CHIP 20 1 DW SUFFIX SOG PACKAGE CASE 751D 20 1 ORDERING INFORMATION MC14489P MC14489DW Plastic DIP SOG Package PIN ASSIGNMENT f 1 20 g e 2 19 h VDD 3 18 DATA OUT d 4 17 BANK 5 c 5 16 BANK 4 b 6 15 BANK 3 a 7 14 VSS Rx 8 13 BANK 2 BANK 1 9 12 DATA IN ENABLE 10 11 CLOCK BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. REV 3 10/95 Motorola, Inc. 1995 MOTOROLA MC14489 1 BLOCK DIAGRAM DATA IN CLOCK ENABLE 12 D 11 C 10 4 OSCILLATOR AND CONTROL LOGIC 4 4 4 4 4 4 4 DATA OUT 4 PIN 3 = VDD PIN 14 = VSS 4 NIBBLE MUX AND DECODER ROM 5 7 a TO g BLANK 5 4 4 BitGrabber DISPLAY REGISTER 24 BITS BitGrabber CONFIGURATION REGISTER 8 BITS POR 18 24–1/2–STAGE SHIFT REGISTER h DIM/BRIGHT ANODE DRIVERS (CURRENT SOURCES) BANK SWITCHES (FETs) 7 9 13 15 16 17 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 6 b c Rx 5 4 2 1 20 19 d e f g h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ a 8 MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit – 0.5 to + 6.0 V Vin DC Input Voltage – 0.5 to VDD + 0.5 V Vout DC Output Voltage – 0.5 to VDD + 0.5 V ± 15 mA Iin Iout IDD, ISS TJ RθJA Tstg TL DC Input Current — per Pin (Includes Pin 8) mA DC Output Current — Pins 1, 2, 4 – 7, 19, 20 Sourcing Sinking – 40 10 Pins 9, 13, 15, 16, 17 Sinking 320 Pin 18 ± 15 DC Supply Current, VDD and VSS Pins Chip Junction Temperature Device Thermal Resistance, Junction–to–Ambient (see Thermal Considerations section) Plastic DIP SOG Package Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds ± 350 mA – 40 to + 130 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. °C/W 90 100 – 65 to + 150 °C 260 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. MC14489 2 MOTOROLA ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TJ = – 40° to 130°C* unless otherwise indicated) Symbol VDD VDD (stby) Parameter Test Condition Power Supply Voltage Range of LED Drive Circuitry Minimum Standby Voltage Bits Retained in Display and Configuration Registers, Data Port Fully Functional VDD V Guaranteed Limit Unit — 4.5 to 6.0 V — 3.0 V VIL Maximum Low–Level Input Voltage (Data In, Clock, Enable) 3.0 6.0 0.9 1.8 V VIH Minimum High–Level Input Voltage (Data In, Clock, Enable) 3.0 6.0 2.1 4.2 V VHys Minimum Hysteresis Voltage (Data In, Clock, Enable) 3.0 6.0 0.2 0.4 V VOL Maximum Low–Level Output Voltage (Data Out) Iout = 20 µA 3.0 6.0 0.1 0.1 V Iout = 1.3 mA 4.5 0.4 VOH Minimum High–Level Output Voltage (Data Out) Iout = – 20 µA 3.0 6.0 2.9 5.9 Iout = – 800 µA 4.5 4.1 Maximum Input Leakage Current (Data In, Clock, Enable) Vin = VDD or VSS 6.0 ± 2.0 Vin = VDD or VSS, TJ = 25°C only 6.0 ± 0.1 iOL Minimum Sinking Current (a, b, c, d, e, f, g, h) Vout = 1.0 V 4.5 0.2 mA iOH Peak Sourcing Current — See Figure 9 for currents up to 35 mA (a, b, c, d, e, f, g, h) Rx = 2.0 kΩ, Vout = 3.0 V, Dimmer Bit = High 5.0 13 to 17.5 mA Rx = 2.0 kΩ, Vout = 3.0 V, Dimmer Bit = Low 5.0 6 to 9 Vout = VDD (FET Leakage) 6.0 50 Vout = VDD (FET Leakage), TJ = 25°C only 6.0 1 Vout = VSS (Protection Diode Leakage) 6.0 1 Maximum ON Resistance (Bank 1, Bank 2, Bank 3, Bank 4, Bank 5) Iout = 0 to 200 mA 5.0 10 Ω Maximum Quiescent Supply Current Device in Low–Power Mode, Vin = VSS or VDD, Rx in Place, Outputs Open 6.0 100 µA Same as Above, TJ = 25°C 6.0 20 Device NOT in Low–Power Mode, Vin = VSS or VDD, Outputs Open 6.0 1.5 Iin IOZ Ron IDD, ISS Iss Maximum Output Leakage Current (Bank 1, Bank 2, Bank 3, Bank 4, Bank 5) Maximum RMS Operating Supply Current (The VSS leg does not contain the Rx current component. See Pin Descriptions.) V µA µA mA * See Thermal Considerations section. MOTOROLA MC14489 3 AC ELECTRICAL CHARACTERISTICS (TJ = – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns) VDD V Guaranteed Limit Serial Data Clock Frequency, Single Device or Cascaded Devices NOTE: Refer to Clock tw below (Figure 1) 3.0 4.5 6.0 dc to 3.0 dc to 4.0 dc to 4.0 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Data Out (Figures 1 and 5) 3.0 4.5 6.0 140 80 80 ns tTLH, tTHL Maximum Output Transistion Time, Data Out (Figures 1 and 5) 3.0 4.5 6.0 70 50 50 ns fR Refresh Rate — Bank 1 through Bank 5 (Figures 2 and 6) 3.0 4.5 6.0 NA 700 to 1900 700 to 1900 Hz Cin Maximum Input Capacitance — Data In, Clock, Enable — 10 pF VDD V Guaranteed Limit Unit Parameter Symbol fclk Unit * See Thermal Considerations section. TIMING REQUIREMENTS (TJ = – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated) Symbol Parameter tsu, th Minimum Setup and Hold Times, Data In versus Clock (Figure 3) 3.0 4.5 6.0 50 40 40 ns tsu, th, trec Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock (Figure 4) 3.0 4.5 6.0 150 100 100 ns tw(L) Minimum Active–Low Pulse Width, Enable (Figure 4) 3.0 4.5 6.0 4.5 3.4 3.4 µs tw(H) Minimum Inactive–High Pulse Width, Enable (Figure 4) 3.0 4.5 6.0 300 150 150 ns Minimum Pulse Width, Clock (Figure 1) 3.0 4.5 6.0 167 125 125 ns Maximum Input Rise and Fall Times — Data In, Clock, Enable (Figure 1) 3.0 4.5 6.0 1 1 1 ms tw tr, tf * See Thermal Considerations section. ** For a high–speed 8–Clock access, th for Enable is determined as follows: VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 – (7500/fclk) VDD = 4.5 to 6 V, fclk > 2.34 MHz: th = 3300 – (7500/fclk) where th is in ns and fclk is in MHz. NOTES: 1. This restriction does NOT apply for fclk rates less than those listed above. For “slow” fclk rates, use the th limits in the above table. 2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table. MC14489 4 MOTOROLA tf tr VDD 90% CLOCK 50% 10% VSS tw tw 1/fclk tPLH DATA OUT tPHL 90% 50% 10% BANK OUTPUT tTLH 50% tTHL 1/fR Figure 1. Figure 2. tw(L) VALID ENABLE tw(H) VDD 50% VDD 50% DATA IN VSS tsu th VDD 50% CLOCK VSS VSS th tsu trec VDD CLOCK 50% FIRST CLOCK LAST CLOCK Figure 3. VSS Figure 4. VDD TEST POINT TEST POINT 56 Ω DEVICE UNDER TEST CL * *Includes all probe and fixture capacitance. Figure 5. MOTOROLA DEVICE UNDER TEST CL * *Includes all probe and fixture capacitance. Figure 6. MC14489 5 PIN DESCRIPTIONS DIGITAL INTERFACE Data In (Pin 12) Serial Data Input. The bit stream begins with the MSB and is shifted in on the low–to–high transition of Clock. When the device is not cascaded, the bit pattern is either 1 byte (8 bits) long to change the configuration register or 3 bytes (24 bits) long to update the display register. For two chips cascaded, the pattern is either 4 or 6 bytes, respectively. The display does not change during shifting (until Enable makes a low– to–high transition) which allows slow serial data rates, if desired. The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the two registers. Random access of either register is provided. That is, the registers may be accessed in any sequence. Data is retained in the registers over a supply range of 3 to 6 V. The format is shown in Figures 7 and 8. Information on the segment decoder is given in Table 1. Data In typically switches near 50% of VDD and has a Schmitt–triggered input buffer. These features combine to maximize noise immunity for use in harsh environments and bus applications. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail– to–rail. When interfacing to NMOS or TTL devices, either a level shifter (MC14504B, MC74HCT04A) or pullup resistor of 1 kΩ to 10 kΩ must be used. Parameters to be considered when sizing the resistor are the worst–case IOL of the driving device, maximum tolerable power consumption, and maximum data rate. Clock (Pin 11) Serial Data Clock Input. Low–to–high transitions on Clock shift bits available at Data In, while high–to–low transitions shift bits from Data Out. The chip’s 24–1/2–stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. The Clock input does not need to be synchronous with the on–chip clock oscillator which drives the multiplexing circuit. Eight clock cycles are required to access the configuration register, while 24 are needed for the display register when the MC14489 is not cascaded. See Figures 7 and 10. As shown in Figure 11, two devices may be cascaded. In this case, 32 clock cycles access the configuration register and 48 access the display register, as depicted in Figure 8. Cascading of 3, 4, and 5 devices is shown in Figures 12, 13, and 14, respectively. Clock typically switches near 50% of V DD and has a Schmitt–triggered input buffer. Slow Clock rise and fall times are tolerated. See the last paragraph of Data In for more information. NOTE To guarantee proper operation of the power–on reset (POR) circuit, the Clock pin must NOT be floated or toggled during power–up. That is, the Clock pin must be stable until the V DD pin reaches at least 3 V. If control of the Clock pin during power–up is not practical, then the MC14489 must be reset via bit C0 in the C register. To accomplish this, C0 is reset low, then set high. MC14489 6 Enable (Pin 10) Active–Low Enable Input. This pin allows the MC14489 to be used on a serial bus, sharing Data In and Clock with other peripherals. When Enable is in an inactive high state, Data Out is forced to a known (low) state, shifting is inhibited, and the port is held in the initialized state. To transfer data to the device, Enable (which initially must be inactive high) is taken low, a serial transfer is made via Data In and Clock, and Enable is taken high. The low–to–high transition on Enable transfers data to either the configuration or display register, depending on the data stream length. Every rising edge on Enable initiates a blanking interval while data is loaded. Thus, continually loading the device with the same data may cause the LEDs on some banks to appear dimmer than others. NOTE Transitions on Enable must not be attempted while Clock is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs when Enable is high and Clock is low. This input is also Schmitt–triggered and switches near 50% of VDD, thereby minimizing the chance of loading erroneous data in the registers. See the last paragraph of Data In for more information. Data Out (Pin 18) Serial Data Output. Data is transferred out of the shift register through Data Out on the high–to–low transition of Clock. This output is a no connect, unless used in one of the manners discussed below. When cascading MC14489’s, Data Out feeds Data In of the next device per Figures 11, 12, 13, and 14. Data Out could be fed back to an MCU/MPU to perform a wrap–around test of serial data. This could be part of a system check conducted at power–up to test the integrity of the system’s processor, pc board traces, solder joints, etc. The pin could be monitored at an in–line Q.A. test during board manufacturing. Finally, Data Out facilitates troubleshooting a system. DISPLAY INTERFACE Rx (Pin 8) External Current–Setting Resistor. A resistor tied between this pin and ground (VSS) determines the peak segment drive current delivered at pins a through h. Pin 8’s resistor ties into a current mirror with an approximate current gain of 10 when bit D23 = high (brighten). With D23 = low, the peak current is reduced about 50%. Values for Rx range from 700 Ω to infinity. When Rx = ∞ (open circuit), the display is extinguished. For proper current control, resistors having ± 1% tolerance should be used. See Figure 9. CAUTION Small Rx values may cause the chip to overheat if precautions are not observed. See Thermal Considerations. MOTOROLA a through h (Pins 1, 2, 4 – 7, 19, 20) Anode–Driver Current Sources. These outputs are closely–matched current sources which directly tie to the anodes of external discrete LEDs (lamps) or display segment LEDs. Each output is capable of sourcing up to 35 mA. When used with lamps, outputs a, b, c, and d are used to independently control up to 20 lamps. Output h is used to control up to 5 lamps dependently. (See Figure 17.) For lamps, the No Decode mode is selected via the configuration register, forcing e, f, and g inactive (low). When used with segmented displays, outputs a through g drive segments a through g, respectively. Output h is used to drive the decimals. If unused, h must be left open. Refer to Figure 10. Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17) Diode–Bank FET Switches. These outputs are low–resistance switches to ground (VSS) capable of handling currents of up to 320 mA each. These pins directly tie to the common cathodes of segmented displays or the cathodes of lamps (wired with cathodes common). The display is refreshed at a nominal 1 kHz rate to achieve optimum brightness from the LEDs. A 20% duty cycle is utilized. MOTOROLA Special design techniques are used on–chip to accommodate the high currents with low EMI (electromagnetic interference) and minimal spiking on the power lines. POWER SUPPLY VSS (Pin 14) Most–negative supply potential. This pin is usually ground. Resistor Rx is externally tied to ground (VSS). Therefore, the chip’s VSS pin does not contain the Rx current component. VDD (Pin 13) Most–positive supply potential. To guarantee data integrity in the registers and to ensure the serial interface is functional, this voltage may range from 3 to 6 volts with respect to VSS. For example, within this voltage range, the chip could be placed in and out of the low– power mode. To adequately drive the LEDs, this voltage must be 4.5 to 6 volts with respect to VSS. The V DD pin contains the Rx current component plus the chip’s current drain. In the low–power mode, the current mirror and clock oscillator are turned off, thus significantly reducing the VDD current, IDD. MC14489 7 MC14489 8 CLOCK ENABLE 1 C6 2 C5 3 C4 4 C3 5 C2 6 C1 7 8 CLCOK ENABLE DATA IN 1 2 C0 C7 3 4 5 6 7 8 9 10 11 12 13 14 15 (a) Configuration Register Format (1 Byte) 16 17 18 19 D4 20 D3 21 D2 22 D1 23 24 L = LOW POWER MODE (BLANKS THE DISPLAY), FORCED LOW (L) BY POWER ON RESET H = NORMAL MODE CONTROLS BANK 1: L = HEX DECODE, H = DEPENDS ON C6 NOTE: The low–power (standby) mode places the device CONTROLS BANK 2: L = HEX DECODE, H = DEPENDS ON C6 in a static state, thus eliminating EMI and mux switching noise. Therefore, during precision analog measurements, CONTROLS BANK 3: L = HEX DECODE, H = DEPENDS ON C6 the low–power mode could be invoked by a system’s MCU. CONTROLS BANK 4: L = HEX DECODE, H = DEPENDS ON C7 Also, the low–power mode blanks the display, and could CONTROLS BANK 5: L = HEX DECODE, H = DEPENDS ON C7 be used to flash the LEDs on and off. L = NO DECODE, H = SPECIAL DECODE (REFER TO C1, C2, AND C3) L = NO DECODE, H = SPECIAL DECODE (REFER TO C4 AND C5) SEE TABLE 1 LSB MSB ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ DATA IN L L H H L L H H L H L H L H L H D17 BANK 5 NIBBLE D18 D16 D15 D13 BANK 4 NIBBLE D14 D11 D9 BANK 3 NIBBLE D10 D8 D7 D5 SEE TABLE 1 BANK 2 NIBBLE D6 THE LSBs OF EACH BANK NIBBLE ARE D0, D4, D8, D12, AND D16. D12 NOTE: L = Low Voltage Level (Logic 0), H = High Voltage Level (Logic 1) (b) Display Register Format (3 Bytes) = ACTIVATE h IN BOTH BANKS 1 AND 2 = ACTIVATE h IN ALL BANKS = ACTIVATE h IN BANK 1 = ACTIVATE h IN BANK 2 = ACTIVATE h IN BANK 3 = ACTIVATE h IN BANK 4 = ACTIVATE h IN BANK 5 = ALL h OUTPUTS INACTIVE D19 L = DIM LEDs, H = BRIGHTEN LEDs L L L L H H H H D20 BANK 1 NIBBLE D0 D21 D23 D22 LSB MSB ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ Figure 7. Timing Diagrams for Non–Cascaded Devices MOTOROLA Table 1. Triple–Mode Segment Decoder Function Table Lamp Conditions Bank Nibble Value Hexadecimal No Decode (Invoked via Bits C1 to C7) 7–Segment Display Characters Binary MSB LSB Hex Decode (Invoked via Bits C1 to C5) Special Decode (Invoked via Bits C1 to C7) d c b $0 L L L L $1 L L L H $2 L L H L on $3 L L H H on $4 L H L L on $5 L H L H on $6 L H H L on on $7 L H H H on on $8 H L L L on $9 H L L H on $A H L H L on on $B H L H H on on $C H H L L on on $D H H L H on on $E H H H L on on on $F H H H H on on on a on on on on on on on on NOTES: 1. In the No Decode mode, outputs e, f, and g are unused and are all forced inactive (low). Output h decoding is unaffected, i.e., unchanged from the other modes. The No Decode mode is used for three purposes: a. Individually controlling lamps. b. Controlling a half digit with sign. c. Controlling annunciators - examples: AM, PM, UHF, kV, mm Hg. 2. Can be used as capital S. 3. Can be used as capital B. 4. Can be used as small g. MOTOROLA MC14489 9 C7 C6 C5 C4 C3 C2 1ST BYTE SHIFTED IN C1 C0 2ND BYTE CONFIGURATION REGISTER OF DEVICE 2 IN FIGURE 11 DON’T CARE 3RD BYTE 4TH BYTE DON’T CARE CONFIGURATION REGISTER OF DEVICE 1 IN FIGURE 11 (a) Configuration Registers D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 1ST BYTE SHIFTED IN 2ND BYTE BANK 5 NIBBLE h BITS AND DIMMER BIT BANK 4 NIBBLE D10 D9 D8 3RD BYTE BANK 3 NIBBLE BANK 2 NIBBLE D7 D6 D5 D4 4TH BYTE D2 5TH BYTE h BITS BANK BANK BANK AND 1 4 5 NIBBLE DIMMER NIBBLE NIBBLE BIT DISPLAY REGISTER OF DEVICE 2 IN FIGURE 11 D3 BANK 3 NIBBLE D1 D0 6TH BYTE BANK 2 NIBBLE BANK 1 NIBBLE DISPLAY REGISTER OF DEVICE 1 IN FIGURE 11 (b) Display Registers NOTE: ENABLE (which initially must be inactive high) is kept active–low during the entire 4–byte configuration transfer or 6–byte display transfer. When ENABLE is brought back high, either a 4– or 6–byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer. Figure 8. Bit Stream Formats for Two Devices Cascaded i OH, PEAK DRIVE CURRENT (mA) 35 5 V SUPPLY BIT D23 = HIGH (BRIGHTEN LEDs) WITH D23 = LOW, iOH IS CUT BY ∼50%. 30 25 20 15 10 5 400 800 1.2 k 1.6 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k Rx, EXTERNAL RESISTOR (Ω) NOTE: Drive current tolerance is approximately ± 15%. Figure 9. a through h Nominal Current per Output versus Rx MC14489 10 MOTOROLA APPLICATIONS INFORMATION +5V a MC14489 VDD b VSS c d 8 e OPTIONAL +5V DATA OUT f g Rx h 8 8 8 8 8 a • Rx #5 #4 #3 #2 f e g d #1 b c BANK 5 DATA IN CMOS MCU/MPU BANK 4 CLOCK BANK 3 ENABLE BANK 2 BANK 1 Figure 10. Non–Cascaded Application Example: 5 Character Common Cathode LED Display with Two Intensities as Controlled via Serial Port BANK 1 TO BANK 5 a TO h MC14489 #1 DATA IN CLOCK ENABLE BANK 1 TO BANK 5 a TO h MC14489 #2 DATA OUT DATA IN CLOCK ENABLE DATA OUT CMOS MCU/MPU OPTIONAL Figure 11. Cascading Two Devices MOTOROLA MC14489 11 MC14489 12 1ST BYTE SHIFTED IN C1 3RD BYTE C2 DATA OUT DON’T CARE C3 ENABLE BANK 1 TO BANK 5 4TH BYTE BANK 4 NIBBLE BANK 3 NIBBLE D9 D8 D6 5TH BYTE D7 D2 (c) Display Registers D0 7TH BYTE D1 DON’T CARE 7TH BYTE CLOCK DATA OUT 8TH BYTE CONFIGURATION REGISTER OF DEVICE #1 8TH (LAST) BYTE ENABLE MC14489 #3 BANK 1 TO BANK 5 9TH BYTE 10TH (LAST) BYTE DISPLAY REGISTER OF DEVICE #1 BANK BANK BANK h BITS BANK BANK BANK BANK BANK AND 3 2 1 5 4 3 2 1 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT 6TH BYTE D4 BANK 4 NIBBLE D5 D3 DON’T CARE 6TH BYTE DATA IN a TO h DISPLAY REGISTER OF DEVICE #2 h BITS BANK BANK AND 1 5 DIMMER NIBBLE NIBBLE BIT 4TH BYTE BANK 2 NIBBLE DISPLAY REGISTER OF DEVICE #3 BANK 5 NIBBLE 3RD BYTE CONFIGURATION REGISTER OF DEVICE #2 5TH BYTE (b) Configuration Registers DON’T CARE C0 (a) Cascading Three Devices OPTIONAL DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #2 CLOCK a TO h DATA IN D17 D16 D15 D14 D13 D12 D11 D10 2ND BYTE D18 C4 2ND BYTE C5 CLOCK MC14489 #1 CONFIGURATION REGISTER OF DEVICE #3 C6 h BITS AND DIMMER BIT D21 D20 D19 DON’T CARE DON’T CARE (OPTIONAL, SEE NOTE) D23 D22 C7 1ST BYTE SHIFTED IN CMOS MCU/MPU DATA IN a TO h NOTE: When the leading “don’t care” bytes are included, ENABLE (which initially must be inactive high) is kept active–low during the entire 8–byte configuration transfer or 10–byte display transfer. When ENABLE is brought back high, either an 8– or 10–byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the one “don’t care” byte can be eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t w (H) spec, (4) transfer last 3 bytes, and (5) take ENABLE inactive high. Figure 12. Bit Stream Formats for Three Devices Cascaded MOTOROLA MOTOROLA 2ND BYTE C7 C4 3RD BYTE C5 ENABLE C2 4TH BYTE C3 DATA OUT CONFIGURATION REGISTER OF DON’T CARE DEVICE #4 C6 CLOCK MC14489 #1 BANK 1 TO BANK 5 C0 2ND BYTE DON’T CARE (OPTIONAL, SEE NOTE) 1ST BYTE SHIFTED IN DON’T CARE (OPTIONAL, SEE NOTE) 4TH BYTE DISPLAY REGISTER OF DEVICE #4 DON’T CARE 7TH BYTE D7 6TH BYTE D8 D6 D4 7TH BYTE D5 D1 8TH BYTE D2 D0 (c) Display Registers DISPLAY REGISTER OF DEVICE #3 DATA OUT 13TH BYTE 14th (LAST) BYTE CONFIGURATION REGISTER OF DEVICE #1 12TH (LAST) BYTE ENABLE BANK 1 TO BANK 5 DISPLAY REGISTER OF DEVICE #1 h BITS BANK BANK BANK BANK BANK AND 4 3 2 1 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT 12TH BYTE DON’T CARE CONFIGURATION REGISTER OF DON’T CARE DEVICE #2 BANK h BITS BANK BANK BANK BANK BANK 1 5 4 3 1 AND 2 NIBBLE DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT D9 D3 DON’T CARE CLOCK MC14489 #4 11TH BYTE DATA IN a TO h 10TH BYTE 9TH BYTE DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #3 CLOCK 8TH BYTE (b) Configuration Registers CONFIGURATION REGISTER OF DEVICE #3 6TH BYTE 5TH BYTE h BITS BANK BANK BANK BANK AND 5 4 3 2 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE BIT 3RD BYTE DATA IN a TO h (a) Cascading Four Devices OPTIONAL DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #2 CLOCK DON’T CARE 5TH BYTE C1 DATA IN a TO h D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 DON’T CARE DON’T CARE 1ST BYTE SHIFTED IN CMOS MCU/MPU DATA IN a TO h NOTE: When the leading “don’t care” bytes are included, ENABLE (which initially must be inactive high) is kept active–low during the entire 12–byte configuration transfer or 14–byte display transfer. When ENABLE is brought back high, either a 12– or 14–byte transfer occurs in the cascaded devices. Alternatively, when updating the display registers, the two “don’t care” bytes can be eliminated as follows: (1) take ENABLE active low, (2) transfer 6 bytes, (3) pulse ENABLE inactive high, see t w (H) spec, (4) transfer last 6 bytes, and (5) take ENABLE inactive high. Figure 13. Bit Stream Formats for Four Devices Cascaded MC14489 13 Figure 14. Bit Stream Formats for Five Devices Cascaded MC14489 14 MOTOROLA 2ND BYTE C7 C6 C5 C4 ENABLE 3RD BYTE CLOCK MC14489 #1 C2 4TH BYTE C3 DATA OUT BANK 1 TO BANK 5 C1 DATA IN 6TH BYTE 7TH BYTE 8TH BYTE 9TH BYTE 10TH BYTE DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #3 CLOCK a TO h (a) Cascading Five Devices OPTIONAL DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #2 CLOCK 5TH BYTE C0 DATA IN a TO h 12TH BYTE 13TH (LAST) BYTE DATA OUT BANK 1 TO BANK 5 ENABLE MC14489 #5 CLOCK 11TH BYTE DATA IN a TO h 2ND BYTE D7 4TH BYTE D8 D6 D4 5TH BYTE D5 D3 D1 D0 6TH BYTE D2 (c) Display Registers DISPLAY REGISTER OF DEVICE #4 14TH BYTE 15TH (LAST) BYTE DISPLAY REGISTER OF DEVICE #1 h BITS BANK BANK BANK BANK BANK AND 4 3 2 1 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BIT 13TH BYTE NOTE: ENABLE (which initially must be inactive high) is kept active–low during the entire 13–byte configuration transfer or 15–byte display transfer. When ENABLE is brought back high, either a 13– or 15–byte transfer occurs in the cascaded devices, depending on the number of bytes in the transfer. DISPLAY REGISTER OF DEVICE #5 D9 h BITS BANK BANK BANK BANK BANK BANK AND 4 3 2 1 5 1 DIMMER NIBBLE BIT NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE 3RD BYTE h BITS BANK BANK BANK BANK AND 4 3 2 5 DIMMER NIBBLE NIBBLE NIBBLE NIBBLE BIT 1ST BYTE SHIFTED IN D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 (b) Configuration Registers CONFIGURATION CONFIGURATION CONFIGURATION CONFIGURATION CONFIGURATION REGISTER OF DON’T CARE DON’T CARE REGISTER OF DON’T CARE DON’T CARE REGISTER OF DON’T CARE DON’T CARE REGISTER OF DON’T CARE DON’T CARE REGISTER OF DEVICE #3 DEVICE #1 DEVICE #2 DEVICE #5 DEVICE #4 1ST BYTE SHIFTED IN CMOS MCU/MPU DATA IN a TO h LED DISPLAY +5V 8 5 +5V VDD R1 CMOS MCU/MPU Rx MC14489 R2 VSS NOTE: R1 limits the maximum current to avoid damaging the display and/or the MC14489 due to overheating. See the Thermal Considerations section. An 1/8 watt resistor may be used for R1. R2 is a 1 kΩ or 5 kΩ potentiometer (≥ 1/8 watt). R2 may be a light–sensitive resistor. Figure 15. Common–Cathode LED Display with Dial–Adjusted Brightness UNIVERSAL OVERFLOW (“1” OR “HALF–DIGIT”) 5–DIGIT DISPLAY 7 USE TO DRIVE LAMP OR MINUS SIGN h 1 2 3 4 5 BANK OUTPUTS a TO g MC14489 3 INPUT LINES NOTE: A Universal Overflow pins out all anodes and cathodes. Figure 16. Driving 5 1/2 Digits MOTOROLA MC14489 15 THESE LAMPS INDEPENDENTLY CONTROLLED WITH BITS D0 TO D19 a b MC14489 c d e NC f NC g NC h BANK 1 BANK 2 THESE LAMPS DEPENDENTLY CONTROLLED WITH BITS D20, D21, AND D22* BANK 3 BANK 4 BANK 5 3 CMOS MCU/MPU * If required, this group of lamps can be independently controlled. To accomplish independent control, only connect lamps to BANK 1 and BANK 2 for output h (two lamps). Then, use bits D20, D21, and D22 for control of these two lamps. Figure 17. 25–Lamp Application MC14489 16 MOTOROLA 4 • 4 4 4 a TO d e TO h BANK 1 TO BANK 4 BANK 5 MC14489 3 CMOS MCU/MPU Figure 18. 4–Digit Display Plus Decimals with Four Annunciators or 4–1/2–Digit Display Plus Sign MUXED 5–DIGIT MONOLITHIC DISPLAY (CLUSTER) HEWLETT–PACKARD 5082–7415 OR EQUIVALENT 8 14 12 3 6 2 10 8 5 1 13 4 9 7 7 6 5 4 2 1 20 19 17 16 15 13 9 MC14489 3 INPUT LINES Figure 19. Compact Display System with Three Components MOTOROLA MC14489 17 THERMAL CONSIDERATIONS The MC14489 is designed to operate with a chip–junction temperature (TJ) ranging from – 40 to 130°C, as indicated in the electrical characteristics tables. The ambient operating temperature range (TA) is dependent on RθJA, the internal chip current, how many anode drivers are used, the number of bank drivers used, the drive current, and how the package is cooled. The maximum ratings table gives the thermal resistance, junction–to–ambient, of the MC14489 mounted on a pc board using natural convection to be 90°C per watt for the plastic DIP. The SOG thermal resistance is 100°C per watt. The following general equation (1) is used to determine the power dissipated by the MC14489. PT = PD + PI (1) where PT = Total power dissipation of the MC14489 PD = Power dissipated in the driver circuitry (mW) PI = Power dissipated by the internal chip circuitry (mW) The equations for the two terms of the general equation are: PI = (1.5)(5.25) + 2[5.25 – 2(2)] = 10 mW Ref. (3) Therefore, PT = 552 + 10 = 562 mW Ref. (1) and ∆Tchip = RθJAPT = (90°C/W)(0.562) = 51°C Finally, the maximum allowable TA = TJmax – ∆Tchip = 130 – 51 = 79°C That is, if TA = 79°C, the maximum junction temperature is 130°C. The chip’s average temperature for this example is lower than 130°C because all segments are usually not illuminated simultaneously for an indefinite period. Worst–Case Analysis Example 2: 16 lamps (4 banks and 4 anode drivers) SOG without heat sink on PC board iOH = 30 mA max VLED = 1.8 V min VDD = 5.5 max PD = (30)(4)(5.5 – 1.8)(4/5) = 355 mW Ref. (2) PI = (1.5)(5.5) + 3[5.5 – 3(1.0)] = 16 mW Ref. (3) Therefore, PT = 355 + 16 = 371 mW Ref. (1) PD = (iOH) (N)(VDD – VLED)(B/5) (2) and ∆Tchip = RθJAPT = (100°C/W)(0.371) = 37°C PI = (1.5 mA)(VDD) + IRx(VDD – IRxRx) (3) Finally, the maximum allowable TA = TJmax – ∆Tchip = 130 – 37 = 93°C where iOH = Peak anode driver current (mA) IRx = iOH /10, with iOH = the peak anode driver current (mA) when the dimmer bit is high N = Number of anode drivers used B = Number of bank drivers used Rx = External resistor value (kΩ) VDD = Maximum supply voltage, referenced to VSS (volts) VLED = Minimum anticipated voltage drop across the LED 1.5 mA = Operating supply current of the MC14489 To extend the allowable ambient temperature range or to reduce TJ, which extends chip life, a heat sink such as shown in Figure 20 can be used in high–current applications. Alternatively, heat–spreader techniques can be used on the PC board, such as running a wide trace under the MC14489 and using thermal paste. Wide, radial traces from the MC14489 leads also act as heat spreaders. The following two examples show how to calculate the maximum allowable ambient temperature. Worst–Case Analysis Example 1: 5–digit display with decimals (5 banks and 8 anode drivers) DIP without heat sink on PC board iOH = 20 mA max VLED = 1.8 V min VDD = 5.25 max PD = (20)(8)(5.25 – 1.8)(5/5) = 552 mW MC14489 18 Ref. (2) AAVID #5804 or equivalent (Tel. 603/524–4443, FAX 603/528–1478) Motorola cannot recommend one supplier over another and in no way suggests that this is the only heat sink supplier. Figure 20. Heat Sink MOTOROLA Table 2. LED Lamp and Common–Cathode Display Manufacturers Supplier Contact Information QT Optoelectronics Phone: (800) 533–6786 FAX: (214) 447–0784 Hewlett–Packard (HP), Components Group Contact your local HP Components Sales Office Industrial Electronic Engineers (IEE), Component Products Div. Phone: (818) 787–0311 FAX: (818) 901–9046 Purdy Electronics Corp., AND Product Line Phone: (408) 523–8210 FAX: (408) 733–1287 NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of LED suppliers. PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 738–03 -A20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B C -T- L K SEATING PLANE M E G N F J 20 PL 0.25 (0.010) D 20 PL 0.25 (0.010) MOTOROLA M T A M M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15° 0° 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0° 15° 1.01 0.51 MC14489 19 DW SUFFIX SOG PACKAGE CASE 751D–04 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R C –T– 18X G SEATING PLANE K X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14489 20 ◊ *MC14489/D* MC14489/D MOTOROLA