FREESCALE MC145181

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19
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The MC145181 is a dual frequency synthesizer containing very–low
supply voltage circuitry. The device supports two independent loops with a
single input reference and operates down to 1.8 V. Phase noise reduction
circuitry is incorporated into the device.
The MC145181 operates up to 550 MHz on the main loop and up to
60 MHz on the secondary loop. The device has a 32/33 prescaler for the
main loop. Lock detection circuitry for both loops is multiplexed to a single
output.
Two 8–bit DACs are powered through a dedicated pin. The DAC supply
range is 1.8 to 3.6 V; this voltage may differ from the main supply.
An on–chip voltage multiplier supplies power to the phase/frequency
detectors. Thus, in a 2 V application, the detectors are supplied with 4 V
power. In 2.6 to 3.6 V applications, the multiplied voltage is regulated at
approximately 5 V. The current source/sink phase/frequency detector for the
main loop is designed to achieve faster lock times than a conventional
detector. Both high and low current outputs are available along with a timer,
double buffers, and a MOSFET switch to adjust the external low–pass filter
response.
There are several levels of standby which are controllable with a 1–byte
transfer through the serial port. Either of the PLLs and/or the reference
oscillator may be independently placed in the low–power standby state. In
addition, any of the phase/frequency detector outputs may be placed in the
floating state to facilitate modulation of the external VCOs. Either DAC may
be placed in standby via a 4–byte transfer.
The MC145181 facilitates designing the receiver’s first and second local
oscillators for ReFLEX two–way paging applications. Also, the device
accommodates generation of the transmit carrier.
• Operating Frequency
Main Loop: 100 to 550 MHz
Secondary Loop: 10 to 60 MHz
• Operating Supply Voltage: 1.8 to 3.6 V
•
•
•
•
•
•
•
•
•
•
•
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Nominal Supply Current, Both Loops Active: 3 mA
BiCMOS COMPONENT
FOR 2 OR 3 VOLT
SYSTEMS
SEMICONDUCTOR
TECHNICAL DATA
32
1
(Scale 2:1)
PLASTIC PACKAGE
CASE 873C
(LQFP–32, Tape & Reel Only)
VERY–SMALL 5 x 5 mm BODY
DEVELOPMENT SYSTEM
The MC145230EVK, which contains hardware and
software, is strongly recommended for system
development. (The user must provide the VCOs for
evaluating the MC145181.) The software supports
all features and modes of operation of the device. Up
to four boards or devices can be controlled and the
user is alerted to error conditions. The control
program may be used with any board based on the
MC145181, MC145225, or MC145230.
Maximum Standby Current, All Systems Shut Down: 10 µA
ORDERING INFORMATION
Phase Detector Output Current:
1.8 V Supply — PDout–Hi: 2.8 mA, PDout–Lo: 0.7 mA
2.5 V Supply — PDout–Hi: 4.4 mA, PDout–Lo: 1.1 mA
Two Independent 8–Bit DACs with Separate Supply Pin (Up to 3.6 V)
w
Device
Main/Secondary
Loop
Maximum
Frequency
Package
MC145181FTAR2
550/60 MHz
LQFP–32
Lock Detect Output with Adjustable Lock Indication Window
Independent R Counters Allow Independent Step Sizes for Each Loop
Main Loop Divider Range: 992 to 262,143
Secondary Loop Divider Range: 7 to 8,191
Fractional Reference Counters Divider Range: 20 to 32,767.5
Auxiliary Reference Divider with Small–Signal Differential
Output — Ratios: 8, 10, 12.5
Three General–Purpose Outputs
Direct Interface to Motorola SPI Data Port Up to 10 Mbps
ReFLEX and BitGrabber are trademarks of Motorola, Inc.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
 Motorola, Inc. 1999
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
Go to: www.freescale.com
Rev 1
1
Freescale Semiconductor,
Inc.
MC145181
CONTENTS
1. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2. PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
3. PARAMETER TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Freescale Semiconductor, Inc...
3A.
3B.
3C.
3D.
3E.
3F.
3G.
3H.
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDout–Hi and PDout–Lo Phase/Frequency Detector Characteristics . . . . . .
PDouti Phase/Frequency Detector Characteristics . . . . . . . . . . . . . . . . . . . . .
DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Multiplier and Keep–alive Oscillator Characteristics . . . . . . . . . . . . .
Dynamic Characteristics of Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Characteristics of Loop and fout Pins . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
5
5
6
6
6
8
4. DEVICE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4A.
4B.
4C.
4D.
4E.
4F.
4G.
4H.
Serial Interface and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Input and Counters Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Divider Inputs and Counter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Multiplier and Keep–alive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase/Frequency Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General–purpose Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
9
9
10
10
10
10
5. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5A.
5B.
5C.
5D.
5E.
5F.
Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
13
13
14
15
15
6. DETAILED REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6A.
6B.
6C.
6D.
6E.
6F.
C Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ri Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hni Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
19
20
22
25
26
7. APPLICATIONS INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7A.
7B.
7C.
7D.
7E.
Crystal Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Loop Filter Design — Conventional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Loop Filter Design — Adapt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary Loop Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Multiplier Stall Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
34
41
50
57
8. PROGRAMMER’S GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8A.
8B.
8C.
8D.
8E.
Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initializing the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Without Adapt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Utilizing Horseshoe With Adapt . . . . . . . . . . . . . . . . . . . . . . . . . .
Controlling the DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
65
66
66
67
9. APPLICATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10. OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
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Freescale Semiconductor,
Inc.
MC145181
1. BLOCK DIAGRAM
16
Output C
Out C
25
Out B/Ref
Output B
PLL Stby
Out A
C Register
8 Bits
fR
fRi
Ph Det Pulse
PLL Stby
PLLi Stby
PD Float
PDi Float
Osc Stby
N Register
24 Bits
Output A
Mux
Freescale Semiconductor, Inc...
Amp
Timer
3
fV
N Counter
18 Stages
fR
R Counter
16 Stages
High–
current
Charge
Pump
Phase /
Frequency
Detector,
Timer,
and Control
16
Hr Register
16 Bits
Low–
current
Charge
Pump
V–Mult
Control
8
Supply Current
Minimization
Circuit
2
16
LD
Lock
Detectori
Test
fRi
Ri Counter
16 Stages
Ratio
10
Amp
PDout–Lo
21 C
mult
22
Creg
Voltage
Multiplier
and Regulator
3
Ri Register
24 Bits
fini 30
20
Lock
Detector
1
Mode
Rx
Osc
Window
2
PDout–Hi
Polarity
R Register
16 Bits
Oscillator
19
17
Lo–I Gain
16
Osce
32
Oscb
Output A
Function
18
fin 12 +
13
–
fin
9
fVi
Ni Counter
13 Stages
Phase /
Frequency
Detectori
23
PDouti
Polarity
13
i
Ni Register
13 Bits
28
27
Auxiliary
Divider
3 Stages
13 MSBs
Hni Register
16 Bits
DAC
8 Bits
8
D Register
16 Bits
8
3
2
Enb
5
Din
6
Clk
7
Shift Register and
Address Generator
Power Connections:
Pin 2 = DAC Vpos
Pins 11, 24, 26, and 29 = Vpos
Pins 14, 15, 18, and 31 = Gnd
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DAC
8 Bits
4
fout/Poli
fout/Pol
DAC1
DAC Vpos
DAC2
3
Freescale Semiconductor,
Inc.
MC145181
2. PIN CONNECTIONS
Oscb Gnd
32
31
fin′
30
fout/
Vpos Pol′
29
28
fout/
Output
Pol Vpos B
27
26
25
Osce 1
Freescale Semiconductor, Inc...
DAC Vpos
24 Vpos
23 PDout′
2
DAC1 3
22 Creg
DAC2 4
21 Cmult
Enb
5
20 PDout–Lo
Din
6
19 PDout–Hi
Clk
7
18 Gnd
LD
8
17 Rx
9
10
11
Output Mode Vpos
A
12
13
fin
fin
14
15
16
Gnd Gnd Output
C
This device contains 15,260 active transistors.
3. PARAMETER TABLES
3A. MAXIMUM RATINGS (Voltages Referenced to Gnd, unless otherwise stated)
Parameter
Symbol
Value
Unit
Vpos,
DAC Vpos
–0.5 to 3.6
V
DC Input Voltage — Osce, fin, fini, Mode,
Din, Clk, Enb, fout/Poli , fout/Pol
Vin
–0.5 to Vpos + 0.5
V
DC Output Voltage
Vout
–0.5 to Vpos + 0.5
V
Iin
±10
mA
Iout
±20
mA
I
25
mA
DC Supply Voltages
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, Vpos and Gnd Pins
Power Dissipation, per Package
PD
100
mW
Storage Temperature
Tstg
–65 to 150
°C
TL
260
°C
Lead Temperature, 1 mm from Case for
10 Seconds
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any
voltage higher than maximum rated voltages
to this high–impedance circuit.
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables
or Pin Descriptions section.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) up to 2000 V.
Additional ESD data available upon request.
4
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MC145181
3B. DC ELECTRICAL CHARACTERISTICS
Vpos = 1.8 to 3.6 V, Voltages Referenced to Gnd, TA = –40 to 85°C, unless otherwise statedtt
Parameter
Condition
Guaranteed
Limit
Unit
Maximum Low–Level Input Voltage
(Din, Clk, Enb, Mode, fout/Poli , fout/Pol)
fout/Poli and fout/Pol Configured as Inputs
VIL
0.3 x Vpos
V
Minimum High–Level Input Voltage
(Din, Clk, Enb, Mode, fout/Poli , fout/Pol)
fout/Poli and fout/Pol Configured as Inputs
VIH
0.7 x Vpos
V
VHys
100
mV
Minimum Hysteresis Voltage
Freescale Semiconductor, Inc...
Symbol
(Clk)
Maximum Low–Level Output Voltage
(LD, Output A, Output B)
Iout = 20 µA
VOL
0.1
V
Minimum High–Level Output Voltage
(LD, Output A, Output B)
Iout = –20 µA
VOH
Vpos – 0.1
V
Minimum Low–Level Output Current
(LD, Output A, Output B)
Vout = 0.3 V
IOL
0.7
mA
Minimum High–Level Output Current
(LD, Output A, Output B)
Vout = Vpos – 0.3 V
IOH
–0.7
mA
Minimum Low–Level Output Current
Vout = 0.2 V
IOL
2.8
mA
Maximum Input Leakage Current
(Din, Clk, Enb, Mode, fout/Poli , fout/Pol)
Vin = Vpos or Gnd; fout/Poli and fout/Pol
Configured as Inputs
Iin
±1.0
µA
Maximum Output Leakage Current
(Output B, Output C)
Vout = Vpos or Gnd; Output in High–Impedance
State
IOZ
±1
µA
Maximum ON Resistance
1.8 V ≤ Vpos < 2.5 V Supply
2.5 V ≤ Vpos ≤ 3.6 V Supply (Note 1)
Ron
75
50
Ω
ISTBY
10
µA
(Output C)
(Output C)
Maximum Standby Supply Current
(Vpos and DAC Vpos Tied Together)
Vin = Vpos or Gnd; Outputs Open; Both PLLs in
Standby Mode; Oscillator in Standby Mode;
DAC1 and DAC2 Output = Zero; Keep–alive
Oscillator Off (Notes 2, 3, and 4)
NOTES: 1. For supply voltages restricted to 2.5 to 2.9 V and an ambient temperature range of –10 to 60°C, Output C has a guaranteed ON resistance range of 23
to 44 Ω .
2. The total supply current drain for the keep–alive oscillator, voltage multiplier, and regulator is approximately 250 µA.
3. When the Mode pin is tied high, bit C6 must be programmed to a 0 for minimum supply current drain. Otherwise, if C6 = 1, the current drain is approximately
8 µA for a 1.8 V supply and approximately 40 µA for a 3.6 V supply. This restriction on bit C6 does not apply when the Mode pin is tied low.
4. To ensure minimum standby supply current drain, the voltage potential at the Cmult pin must not be allowed to fall below the potential at the Vpos pins.
See discussion in Section 5E under Cmult.
3C. PDout–Hi AND PDout–Lo PHASE/FREQUENCY DETECTOR CHARACTERISTICS
Nominal Output Current, Vpos = 1.8 V: PDout–Hi = 2.8 mA, PDout–Lo = 0.7 or 0.35 mA
Nominal Output Current, Vpos ≥ 2.5 V: PDout–Hi = 4.4 mA, PDout–Lo = 1.1 or 0.55 mA
Rx = 2.0 kΩ, Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85°C
Condition
Parameter
Guaranteed
Limit
Unit
Maximum Source Current Variation Part–to–Part
(See Note) Vout = 0.5 x VCmult
±14
%
Maximum Sink–versus–Source Mismatch
(See Note) Vout = 0.5 x VCmult
20
%
Output Voltage Range
(See Note) Iout Variation ≤ 27%
0.6 to VCmult – 0.6 V
V
±50
nA
Guaranteed
Limit
Unit
Maximum Three–State Leakage Current
Vout = 0 or VCmult
NOTE: Percentages calculated using the following formula: (Maximum Value – Minimum Value) / Maximum Value.
3D. PDouti PHASE/FREQUENCY DETECTOR CHARACTERISTICS
Vpos = 1.8 to 3.6 V, Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85°C
Parameter
Condition
Minimum Low–Level Output Current
Vout = 0.3 V
0.3
mA
Minimum High–Level Output Current
Vout = VCmult – 0.3 V
–0.3
mA
Maximum Three–State Leakage Current
Vout = 0 or VCmult
±50
nA
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5
Freescale Semiconductor,
Inc.
MC145181
3E. DAC CHARACTERISTICS
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Vpos = 1.8 to 3.6 V, DAC Vpos = 1.8 to 3.6 V; TA = –40 to 85°C
Freescale Semiconductor, Inc...
Parameter
Guaranteed
Limit
Condition
Unit
Resolution
8
Bits
Maximum Integral Nonlinearity
±1
LSB
Maximum Offset Voltage from Gnd
No External Load
1
LSB
Maximum Offset Voltage from DAC Vpos
No External Load
2
LSB
Maximum Output Impedance
Over Entire Output Range, Including Zero
Output (which is Low–power Standby)
130
kΩ
Maximum Standby Current
Zero Output, No External Load
Maximum Supply Current per DAC @ DAC Vpos pin
Except with Zero Output, No External Load
(See ISTBY in Section 3B)
(DAC Vpos) / 36
mA
Guaranteed
Limit
Unit
3F. VOLTAGE MULTIPLIER AND KEEP–ALIVE OSCILLATOR CHARACTERISTICS
Voltages Referenced to Gnd, TA = –40 to 85°C
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Parameter
Condition
Voltage Multiplier Output Voltage
Keep–alive Refresh Frequency
5 MHz Refresh Rate, 100 µA Continuous
Sourcing, Measured at Cmult pin
Vpos = 1.8 V
Vpos = 3.6 V
3.32 to 3.78
4.75 to 5.35
V
Vpos = 1.8 to 3.6 V
300 to 700
kHz
3G. DYNAMIC CHARACTERISTICS OF DIGITAL PINS
Vpos = 1.8 to 3.6 V, TA = –40 to 85°C, Input tr = tf = 10 ns, CL = 25 pF
Figure
No.
Symbol
Guaranteed
Limit
Unit
1
fclk
dc to 10
MHz
2, 7
tPLH, tPHL
200
ns
Maximum Propagation Delay, Enb to Output B
2, 3, 7, 8
tPLH, tPHL,
tPZL, tPLZ,
tPZH, tPHZ
200
ns
Maximum Propagation Delay, Enb to Output C
4, 8
tPZL, tPLZ
200
ns
Maximum Output Transition Time, Output A; Output B with Active Pullup and Pulldown
2, 7
tTLH, tTHL
75
ns
Minimum Setup and Hold Times, Din versus Clk
5
tsu, th
30
ns
Minimum Setup, Hold, and Recovery Times, Enb versus Clk
6
tsu, th, trec
100
ns
Minimum Pulse Width, Inactive (High) Time, Enb
6
tw
*
cycles
Minimum Pulse Width, Clk
1
tw
50
ns
Cin
10
pF
Parameter
Serial Data Clk Frequency
NOTE: Refer to Clk tw Below
Maximum Propagation Delay, Enb to Output A (Selected as General–Purpose Output)
Maximum Input Capacitance — Din, CLK, Enb
* For Hr register access, the minimum limit is 20 Osce cycles.
For Hni register access, the minimum limit is 27 fini cycles.
For N register access, the minimum limit is 20 Osce cycles + 99 fin cycles.
When the timer is used for adapt, the minimum limit after the second N register access and before the next register access is the time–out interval + 99 fin cycles.
6
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Figure 1.
tf
Figure 2.
tr
Vpos
90%
Clk 50%
10%
50%
Enb
Vpos
Gnd
Gnd
tw
tw
tPLH
1/fclk
Output A
Output B
tPHL
90%
10%
tTLH
Figure 3.
tTHL
Figure 4.
Vpos
Freescale Semiconductor, Inc...
Vpos
50%
Enb
50%
Enb
Gnd
Gnd
tPZL
tPZL
90%
Output B
90%
Output C
tPLZ
High
Impedance
tPLZ
Output B
10%
High
Impedance
Output C
10%
tPZH
Output B
10%
tPHZ
90%
Output B
Figure 5.
Figure 6.
tw
Valid
Vpos
Din
Enb
Vpos
50%
50%
Gnd
Gnd
tsu
th
tsu
th
trec
Vpos
50%
Clk
Gnd
Clk
First
Clock
Figure 7.
Last
Clock
Figure 8.
Test Point
Device
Under
Test
Test Point
CL*
* Includes all probe and fixture capacitance.
Vpos
50%
Device
Under
Test
Gnd
Source current and
limit voltage to Vpos
for tPLZ and tPZL.
Sink current and
limit voltage to Gnd
for tPHZ and tPZH.
250 µA
CL*
* Includes all probe and fixture capacitance.
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3H. DYNAMIC CHARACTERISTICS OF LOOP AND fout PINS
Vpos = 1.8 to 3.6 V, TA = –40 to 85°C
Symbol
Condition
Figure
No.
Min
Max
Unit
vin
Input Voltage Range, fin
100 MHz ≤ fin < 550 MHz
9
100
300
mVpp
vini
Input Voltage Range, fini
10 MHz ≤ fin < 60 MHz
10
100
400
mVpp
Input Frequency Range, Osce
vin = 350 to 600 mVpp,
Device in External Reference Mode
11
9
80
MHz
fXtal
Crystal Frequency, Oscb and Osce
Device in Crystal Mode
*
9
80
MHz
Cin
Input Capacitance of Pins Oscb and
Osce
—
—
pF
fout
Output Frequency Range, fout and fout
1
6.2
MHz
fφ
Operating Frequency Range of the
Phase/Frequency Detectors, PDout–Hi,
PDout–Lo, PDouti
dc
600
kHz
fOsce
Freescale Semiconductor, Inc...
Parameter
Output Signal Swing > 300 mVpp per
pin (600 mVpp differential)
12
* Refer to the Crystal Oscillator Considerations section.
Figure 9.
Figure 10.
100 pF
Sine Wave
Generator
Zout = 50 Ω
RF
Meter
RL = 50 Ω
Device
Under
Test
Vin
fin
Gnd
100 pF
Sine Wave
Generator
Zout = 50 Ω
fin
Vpos
Vpos
fini
Device
Under
Test
Vin
RF
Meter
RL = 50 Ω
Gnd
Vpos
Vpos
100 pF
Figure 11.
Figure 12.
0.1 µF
Sine Wave
Generator
Osce
Vin
50 Ω
fout
Device
Under
Test
Device
Under
Test
Oscb
Gnd
Vpos
Vpos
V
20 pF
Peak–to–peak
Voltage
Measurement
V
fout
20 pF
No
Connection
8
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Reference Counter for Main Loop
4. DEVICE OVERVIEW
Main reference counter R divides down the frequency at
Osce and feeds the phase/frequency detector for the main
loop. The detector feeds the two charge pumps with outputs
PDout–Hi and PDout–Lo. The division ratio of the R counter is
determined by bits in the R register.
Refer to the Block Diagram in Section 1.
Freescale Semiconductor, Inc...
4A. SERIAL INTERFACE AND REGISTERS
The serial interface is comprised of a Clock pin (Clk), a
Data In pin (Din), and an Enable pin (Enb). Information on the
data input pin is shifted into a shift register on the low–to–high
transition of the serial clock. The data format is most
significant bit (MSB) first. Both Clk and Enb are
Schmitt–triggered inputs.
The R and N registers contain counter divide ratios for the
main loop, PLL. The Ri and Ni registers contain counter
divide ratios for the secondary loop, PLLi. Additional contol
bits are located in the Ri, N, and C registers. The D register
controls the digital–to–analog converters (DACs). Random
access is allowed to the N, Ri, Hr, Hni, D, and C registers.
Two 16–bit holding registers, Hr and Hni, feed registers R
and Ni, respectively. [The three least significant bits (LSBs)
of the Hni register are not used.] The R and Ni registers
determine the divide ratios of the R and Ni counters,
respectively. Thus, the information presented to the R and Ni
counters is double–buffered. Using the proper programming
sequence, new divide ratios may be presented to the N, R,
and Ni counters; simultaneously.
Enb is used to activate the data port and allow transfer of
data. To ensure that data is accepted by the device, the Enb
signal line must initially be a high voltage (not asserted), then
make a transition to a low voltage (asserted) prior to the
occurrence of a serial clock, and must remain asserted until
after the last serial clock of the burst. Serial data may be
transferred in an SPI format (while Enb remains asserted).
Data is transferred to the appropriate register on the rising
edge of Enb (see Table 1). “Short shifting”, depicted as
BitGrabber in the table, allows access to certain registers
without requiring address bits. When Enb is inactive (high),
Clk is inhibited from shifting the shift register.
The serial input pins may NOT be driven above the supply
voltage applied to the Vpos pins.
Reference Counter for Secondary Loop
Secondary reference counter R i divides down the
frequency at Osce and feeds the phase/frequency detector
for the secondary loop. The detector output is PDouti. The
division ratio of the Ri counter is determined by the 16 LSBs
of the Ri register.
The Ri counter has a special mode to provide a frequency
output at pins fout and fout (differential outputs). These are
low–jitter ECL–type outputs. With the Mode pin low, software
control allows the Osce frequency to be divided–by–8, –10,
or –12.5 and routed to the fout pins. This output is derived by
tapping off of a front–end stage of the Ri counter and feeding
the auxiliary counter which provides the divided–down
frequency. The chip must have the Mode pin low, which
activates the fout pins. The actual Ri divide ratio must be
divisible by 2 or 2.5 when the fout pins are activated. There is
no such restriction when the Mode pin is high. See
Section 6D, Ri Register.
4C. LOOP DIVIDER INPUTS AND COUNTER CIRCUITS
fin Inputs and Counter Circuit
fin and fin are high–frequency inputs to the amplifier which
feeds the N counter. A small signal can feed these inputs
either differentially or single–ended.
The N counter divides down the external VCO frequency
for the main loop. (The divide ratio of the N counter is also
known as the loop multiplying factor.) The divide ratio of this
counter is determined by the 18 LSBs of the N register. The
output of the N counter feeds the phase/frequency detector
for the main loop.
fini Input and Counter Circuit
4B. REFERENCE INPUT AND COUNTERS CIRCUITS
Reference (Oscillator) Circuit
For the Colpitts reference oscillator, one pin ties to the
base (Oscb, pin 32) and the other ties to the emitter (Osce,
pin 1), of an on–chip NPN transistor. In addition, the
reference circuit may be operated in the external reference
(XRef) mode as selectable via bit C6 when the Mode pin is
high.
The Oscb and Osce pins support an external fundamental
or overtone crystal. The output of the oscillator is routed to
both the reference counter for the main loop (R counter) and
the reference counter for the secondary loop (Ri counter).
In a second mode, determined by bit C6 being 1 and the
Mode pin being high, Osce is an input which accepts an
ac–coupled signal from a TCXO or other source. Oscb must
be floated. If the Mode pin is low, this “XRef mode” is not
allowed.
fini is the high–frequency input to the amplifier which feeds
the N i counter. A small signal can feed this input
single–ended.
The Ni counter divides down the external VCO frequency
for the secondary loop. (The divide ratio of the Ni counter is
also known as the loop multiplying factor.) The divide ratio of
this counter is determined by bits in the Ni register. The
output of the Ni counter feeds the phase/frequency detector
for the secondary loop.
4D. VOLTAGE MULTIPLIER AND KEEP–ALIVE
CIRCUITS
The voltage multiplier produces approximately two times
the voltage present at the Vpos pins over a supply range of
1.8 V to about 2.5 V. With a supply range of approximately
2.5 V to 3.6 V, the elevated voltage is regulated/limited to
approximately 5 V. The elevated voltage, present at the Cmult
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pin, is applied to both phase detectors. An external capacitor
to Gnd is required on the Cmult pin. The other capacitors
required for the multiplier are on–chip.
A capacitor to Gnd is also required on the Creg pin. The
voltage on this pin is equal to the voltage on the Vpos pins
over a supply range of 1.8 V to about 2.5 V. The voltage on
Creg is limited to approximately 2.5 V maximum when the
Vpos pins exceed 2.5 V.
The refresh rate determines the repetition rate that the
capacitors for the voltage multiplier are charged. Refresh is
normally derived off of the signal present at the Osce pin,
through a divider which is part of the voltage multiplier and
regulator circuitry. The refresh rate is controlled via bits in the
Ri register.
When the reference oscillator circuit is placed in standby,
an on–chip keep–alive oscillator assists in maintaining the
elevated voltage on the phase detectors. The keep–alive
refresh rate is per the spec table in Section 3F.
If desired, the keep–alive oscillator can be inhibited from
turning on, by placing the multiplier in the inactive state via Ri
register bits. This causes the phase/frequency detector
voltage to bleed off while in standby, but has the advantage of
achieving the lowest supply current if all other sections of the
chip are shut down.
4E. PHASE/FREQUENCY DETECTORS
Detector for Main Loop
The detector for the main loop senses the phase and
frequency difference between the outputs of the R and N
counters. The detector feeds both a high–current charge
pump with output PDout–Hi and a low–current charge pump
with output PDout–Lo.
The charge pumps can be operated in three conventional
manners as controlled by bits in the N register. PDout–Lo can
be enabled with PDout–Hi inhibited. Conversely, PDout–Hi
can be enabled with PDout–Lo inhibited. Both outputs can be
enabled and tied together externally for maximum charge
pump current. Finally, both outputs can be inhibited. In this
last case, they float. The outputs can also be forced to the
floating state by a bit in the C register. This facilitates
introduction of modulation into the VCO input.
The charge pumps can be operated in an adapt mode as
controlled by bits in the N register. The bits essentially
program a timer which determines how long PDout–Hi is
active. After the time–out, PDout–Hi floats and PDout–Lo
becomes active. In addition, a second set of R and N counter
values can be engaged after the time–out. For more
information, see Table 16 and Section 8, Programmer’s
Guide.
10
Detector for Secondary Loop
The detector for the secondary loop senses the phase and
frequency difference between the outputs of the Ri and Ni
counters. Detector output PDouti is a voltage–type output
with a three–state push–pull driver.
The output can be forced to the floating state by a bit in the
C register. This facilitates introduction of modulation into the
VCO input.
4F. LOCK DETECTORS
Window counters in each of the lock detector circuits
determine the lock detector phase threshold for PLL and
PLLi. The window counter divide ratio for the main loop’s lock
detector is controlled via a bit in the N register. The window
counter divide ratio for the secondary loop is not controllable
by the user.
The lock detector window determines a minimum phase
difference which must occur before the Lock Detect pin goes
high. Note that the lock detect signals for each loop drive an
AND gate, which then feeds the LD pin. The LD pin indicates
the condition of both loops, or the one active loop if the other
is in standby. If both loops are in standby, LD is low indicating
unlocked.
4G. DACs
The two independent 8–bit DACs facilitate crystal
oscillator trimming and PA output power control. They are
also suitable for any general–purpose use.
Each DAC utilizes an R–2R ladder architecture. The
output pins, DAC1 and DAC2, are directly connected to the
ladder; that is, there is no on–chip buffer.
The DAC outputs are determined by the contents of the D
register. When a DAC output is zero scale, it is also in a
low–power mode. The power–on reset (POR) circuit
initializes the DACs in the low–power mode upon power up.
4H. GENERAL–PURPOSE OUTPUTS
There are three outputs which may be used as port
expanders for a microcontroller unit (MCU).
Output A is actually a multi–purpose output with a
push–pull output driver. See Table 2 for details.
Output B is a three–state output. The state of Output B
depends on two bits; one of these bits also controls whether
the main PLL is in standby or not. See Table 5 for details.
Output C is an open–drain output. The state of this output
is controlled by one bit per Table 4. Output C is specified with
a guaranteed ON resistance, and thus, may be used in an
analog fashion.
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5A. DIGITAL PINS
Data is retained in the registers over a supply range of 1.8
to 3.6 V. The bit–stream formats are shown in Figures 13
through 18.
Enb, Din, and Clk
Pins 5, 6, and 7 — Serial Data Port Inputs
LD
Pin 8 — Lock Detectors Output
The Enb input is used to activate the serial interface to
allow the transfer of data to the device. To transfer data to the
device, the Enb pin must be low during the interval that the
data is being clocked in. When Enb is taken back high
(inactive), data is transferred to the appropriate register
depending either on the data stream length or address bits.
The C, Hr, and N registers can be accessed using either a
unique data stream length (BitGrabber) or by using address
bits (Conventional). The D, Hni, and Ri registers can only be
accessed using address bits. See Table 1.
The bit stream begins with the MSB and is shifted in on the
low–to–high transition of Clk. The bit pattern is 1 byte (8 bits)
long to access the C register, 2 bytes (16 bits) to access the
Hr register, or 3 bytes (24 bits) to access the N register. A bit
pattern of 4 bytes (32 bits) is used to access the registers
when using address bits. The device has double buffers for
storage of the Ni and R counter divide ratios. One double
buffer is composed of the Hr register which feeds the R
register. An Hr to R register transfer occurs whenever the N
register is written. The other double buffer is the Hni register
which feeds the Ni register. An Hni to Ni register transfer
occurs whenever the N register is written. Thus, new divide
ratios may be presented to the R, Ni, and N counters
simultaneously.
Transitions on Enb must not be attempted while Clk is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs whenever Enb is
high (inactive) and Clk is low.
This signal is the logical AND of the lock detect signals
from both PLL and PLLi. For the main PLL, the phase
window that defines “lock” is programmable via bit N22. The
phase window for the secondary PLLi is not programmable.
If either PLL or PLLi is in standby, LD indicates the lock
condition of the active loop only. If both loops are in standby,
the LD output is a static low level.
Each PLL’s lock detector is in the high state when the
respective loop is locked (the inputs to the phase detector
being the same phase and frequency). The lock detect signal
is in the low state when a loop is out of lock. See Figure 19.
Upon power up, the LD pin indicates a not locked
condition. The LD pin is a push–pull CMOS output. If unused,
LD should be left open.
Freescale Semiconductor, Inc...
5. PIN DESCRIPTIONS
Output A
Pin 9 — Multiple–Purpose Digital Output
Depending on control bits Ri21 and Ri20, Output A is
selectable by the user as a general–purpose output (either
high or low level), fR (output of main reference counter), fRi
(output of secondary reference counter), or a phase detector
pulse indicator for both loops. When selected as
general–purpose output, bit C7 determines whether the
output is a high or low level per Table 2. When configured as
fR, fRi, or phase detector pulse, Output A appears as a
normally low signal and pulses high.
Output A is a slew–rate limited CMOS totem–pole output.
If unused, Output A should be left open.
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Table 1. Register Access
(LSBs are C0, R0, N0, D0, Ri0, and Ni0)
Access
Type
Number
of
Clocks
Accessed
Register
Address
Nibble
Register Bit
Nomenclature
Figure
No.
BitGrabber
C
—
8
C7, C6, C5, ..., C0
13
BitGrabber
Hr
—
16
R15, R14, R13, ..., R0
14
BitGrabber
N
—
24
N23, N22, N21, ..., N0
15
Conventional
C
$0
32
C7, C6, C5, ..., C0
13
Conventional
Hr
$1
32
R15, R14, R13, ..., R0
14
Conventional
N
$2
32
N23, N22, N21, ..., N0
15
Conventional
D
$3
32
D15, D14, D13, ..., D0
18
Conventional
Ri
$5
32
Ri23, Ri22, Ri21, ..., Ri0
16
Conventional
Hni
$4
32
Ni15, Ni14, Ni13, ..., Ni0
17
NOTE: $0 denotes hexadecimal zero, $1 denotes hexadecimal one, etc.
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ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
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Table 2. Output A Configuration
Bit
Ri21
Bit
Ri20
Bit
C7
0
0
0
Function of Output A
General–Purpose Output,
Low Level
0
0
1
General–Purpose Output,
High Level
0
1
x
fR
1
0
x
fRi
1
1
x
Phase Detector Pulse
Indicator
Freescale Semiconductor, Inc...
Mode
Pin 10 — Mode Input
When the Mode pin is tied low (approximately Gnd), the
pair of pins named fout/Poli and fout/Pol become outputs fout
and fout. As such, these pins are the divided down reference
frequency. The division ratio is controlled by bits per Table 6.
In addition, when Mode is low, the Ri counter is preceded by
a fixed–divide prescaler. Also, only a crystal may be used at
pins Oscb and Osce; an external reference, such as a TCXO,
should not be used to drive either pin. The default on the
phase detector polarity is positive. See the summary in
Table 3.
When the Mode pin is tied high (approximately Vpos), the
pair of pins named fout/Poli and fout/Pol become inputs Poli
and Pol. As such, these pins control the polarity of the
phase/frequency detectors for PLLi and PLL, respectively. In
addition, when Mode is high, the Ri counter is preceded by a
dual–modulus prescaler. Therefore, the R i counter is
completely programmable per Figure 16. Also, either a
crystal or TCXO may be used with the device. See the
summary in Table 3.
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Table 3. Mode Pin Summary
Attribute
Mode Pin = Low Level
Mode Pin = High Level
fout/Poli pin
Pin is fout output;
polarity of phase
detectori is positive
Pin is Poli input and
controls polarity of
phase detectori
fout/Pol pin
Pin is fout output;
polarity of phase
detector is positive
Pin is Pol input and
controls polarity of
phase detector
Oscillator
circuit
Supports a crystal only
Supports crystal or
accommodates TCXO
Ri counter
Programmable in
increments of 2 or 2.5
Programmable in
increments of 0.5
State of pin controlled
by Bit C6
Pin not used, Bit C6
controls whether
crystal or TCXO is
accommodated
Output B
pin
Output C
Pin 16 — General–Purpose Digital Output
This pin is controllable by bit C5 as either low level or high
impedance per Table 4.
The output driver is an open–drain N–channel MOSFET
connected to Gnd. The ESD (electrostatic discharge)
protection circuit for this pin is tied to Gnd and Vpos. Thus,
12
voltages above Vpos are clipped at approximately 0.7 V
above Vpos. If unused, Output C should be left open.
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Table 4. Output C Programming
Bit C5
State of Output C Pin
0
Low level
(ON resistance per
Electrical Table)
1
High impedance
(leakage per Electrical Table)
Output B
Pin 25 — General–Purpose Digital Output
This pin is controllable by bits C6 and C1 as either low
level, high level, or high impedance per Table 5. Note that
whenever the main PLL is placed in standby by bit C1, Output
B is forced to high impedance. The three–state MOSFET
output is slew–rate limited. If unused, Output B should be left
open.
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Table 5. Output B Programming
Bit C6
Bit C1
State of
Output B Pin
Condition of
Main PLL
0
0
Low level
Active
0
1
High impedance*
Standby*
1
0
High level
Active
1
1
High impedance
Standby
*Power–up default.
fout/Poli and fout/Pol
Pins 28 and 27 — Dual–purpose Outputs/Inputs
These pins are outputs when the Mode pin is low and
inputs when the Mode pin is high.
When the Mode pin is low, these pins are small–signal
differential outputs fout and fout with a frequency derived from
the signal present at the Osce pin. The frequency of the
output signal is per Table 6. If this function is not needed, the
Mode pin should be tied high, which minimizes supply
current. In this case, these inputs must be tied high or low per
Tables 7 and 8.
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Table 6. fout and fout Frequency
(Mode Pin = Low)
Bit N23
Bit Ri1
Bit Ri0
Output Frequency
0
0
0
Osce divided by 10
0
0
1
Osce divided by 12.5
0
1
0
Osce divided by 12.5
0
1
1
Osce divided by 12.5
1
0
0
Osce divided by 8
1
0
1
Osce divided by 10
1
1
0
Osce divided by 10
1
1
1
Osce divided by 10
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When the Mode pin is high, these pins are digital inputs
Poli and Pol which control the polarity of the phase/frequency
detectors. See Tables 7 and 8. Positive polarity is used when
an increase in an external VCO control voltage input causes
an increase in VCO output frequency. Negative polarity is
used when a decrease in an external VCO control voltage
input causes an increase in VCO output frequency.
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Table 7. Main Phase/Frequency Detector Polarity
(Mode Pin = High)
Mode Pin
Pol Pin
Main Detector Polarity
(PDout–Lo and PDout–Hi)
High
Low
Positive
High
High
Negative
Low
*
Positive
Freescale Semiconductor, Inc...
*Pin configured as an output; should not be driven.
Table 8. Secondary Phase/Frequency
Detector Polarity
(Mode Pin = High)
Mode Pin
Poli Pin
Secondary Detector
Polarity
(PDouti)
High
Low
Positive
High
High
Negative
Low
*
Positive
*Pin configured as an output; should not be driven.
5B. REFERENCE PINS
Osce and Oscb
Pins 1 and 32 — Reference Oscillator Transistor Emitter
and Base
These pins can be configured to support an external
crystal in a Colpitts oscillator configuration. The required
connections for the crystal circuit are shown in the Crystal
Oscillator Considerations section.
Additionally, the pins can be configured to accept an
external reference frequency source, such as a TCXO. In this
case, the reference signal is ac coupled into Osce and the
Oscb pin is left floating. See Figure 11.
Bit C6 and the Mode input pin control the configuration of
these pins per Table 9.
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Table 9. Reference Configuration
Mode
Input
Pin
Bit C6
Low
X
Reference
Configuration
Comment
Supports Crystal
(default)
C6 used to control
Output B*
High
0
Supports Crystal
Output B not useful
High
1
Requires External
Reference
Output B not useful
*See Table 5.
5C. LOOP PINS
fin and fin
Pins 12 and 13 — Frequency Input for Main Loop (PLL)
These pins feed the on–chip RF amplifier which drives the
high–speed N counter. This input may be fed differentially.
However, it is usually used in a single–ended configuration
with fin driven while fin is tied to a good RF ground (via a
capacitor). The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fin input is specified as a level across a 50 Ω
load driven by a 50 Ω source. A VCO that can drive a load
within the data sheet limits can also drive fin. Usually, to avoid
load pull and resultant frequency modulation of the VCO, fin is
lightly coupled by a small value capacitor and/or a resistor.
See the applications circuit of Figure 65.
fini
Pin 30 — Frequency Input for Secondary Loop (PLLi)
This pin feeds the on–chip RF amplifier which drives the
high–speed Ni counter. This input is used in a single–ended
configuration. The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fini input is specified as a level across a
50 Ω load driven by a 50 Ω source. A VCO that can drive a
load within the data sheet limits can also drive fini. Usually, to
avoid load pull and resultant frequency modulation of the
VCO, fini is lightly coupled by a small value capacitor and/or
a resistor. See the applications circuit of Figure 65.
If the secondary loop is not used, PLLi should be placed in
standby and fini should be left open.
PDout–Hi and PDout–Lo
Pins 19 and 20 — Phase/Frequency Detector Outputs
for Main Loop (PLL)
Each pin is a three–state current source/sink/float output
for use as a loop error signal when combined with an external
low–pass loop filter. Under bit control, PDout–Lo has either
one–quarter or one–eighth the output current of PDout–Hi per
Table 10. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 20.
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Table 10. Current Ratio of PDout–Hi
and PDout–Lo
Bit
N18
Output Current Ratio
PDout–Hi:PDout–Lo
(Gain Ratio)
0
4:1
1
8:1
When the Mode pin is high, positive polarity occurs when
the Pol pin is low. Also, when the Mode pin is low, polarity
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defaults to positive. Positive polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
the output of the main loop’s reference divider (R counter).
(a) Frequency of f V > f R or phase of f V leading f R :
current–sinking pulses from a floating state.
(b) Frequency of f V < f R or phase of f V lagging f R :
current–sourcing pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
Freescale Semiconductor, Inc...
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
the output of the main loop’s reference divider (R counter).
(a) Frequency of f V > f R or phase of f V leading f R :
current–sourcing pulses from a floating state.
(b) Frequency of f V < f R or phase of f V lagging f R :
current–sinking pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
These outputs can be enabled and disabled by bits in the
C and N registers. Placing the main PLL in standby (bit C1
= 1) forces the detector outputs to a floating state. In addition,
setting the PD Float bit (bit C4 = 1) forces the detector
outputs to a floating state while allowing the counters to run
for the main PLL. For selection of the outputs, see Table 11.
The phase detector gain (in amps per radian) = PDout
current (in amps) divided by 2π.
If a detector output is not used, that pin should be left
open.
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Table 11. Selection of Main Detector Outputs
Bit
N21
Bit
N20
Bit
N19
0
0
0
Both outputs not enabled
0
0
1
PDout–Lo enabled
0
1
0
PDout–Hi enabled
0
1
1
Both PDout–Lo and PDout–Hi
enabled
1
0
0
PDout–Hi enabled for 16 fR cycles
only, then PDout–Lo enabled
1
0
1
PDout–Hi enabled for 32 fR cycles
only, then PDout–Lo enabled
1
1
0
PDout–Hi enabled for 64 fR cycles
only, then PDout–Lo enabled
1
1
1
PDout–Hi enabled for 128 fR
cycles only, then PDout–Lo
enabled
Result
NOTES: 1. When a detector output is not enabled, it is floating.
2. Setting bit N21 = 1 places the IC in an adapt mode and engages a
timer.
14
PDouti
Pin 23 — Phase/Frequency Detector Output for
Secondary Loop (PLLi)
This pin is a three–state voltage output for use as a loop
error signal when combined with an external low–pass loop
filter. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 21.
When the Mode pin is high, positive polarity occurs when
the Poli pin is low. Also, when the Mode pin is low, polarity
defaults to positive. Positive polarity is described below. fVi is
the output of the secondary loop’s VCO divider (Ni counter).
fRi is the output of the secondary loop’s reference divider (Ri
counter.)
(a) Frequency of fVi > fRi or phase of fVi leading fRi:
negative pulses from high impedance.
(b) Frequency of fVi < fRi or phase of fVi lagging fRi:
positive pulses from high impedance.
(c) Frequency and phase of f V i = f R i : essentially a
high–impedance state, voltage at pin determined by
loop filter.
When the Mode pin is high, negative polarity occurs when
the Poli pin is high. Negative polarity is described below. fVi
is the output of the secondary loop’s VCO divider (Ni
counter). fRi is the output of the secondary loop’s reference
counter (Ri counter.)
(a) Frequency of fVi > fRi or phase of fVi leading fRi:
positive pulses from high impedance.
(b) Frequency of fVi < fRi or phase of fVi lagging fRi:
negative pulses from high impedance.
(c) Frequency and phase of f V i = f R i : essentially a
high–impedance state, voltage at pin determined by
loop filter.
This output can be enabled and disabled by bits in the C
register. Placing the secondary PLLi in standby (bit C0 = 1)
forces the detector output to a high–impedance state. In
addition, setting the PDi Float bit (bit C3 = 1) forces the
detector output to a high–impedance state while allowing the
counters to run for PLLi.
The phase detector gain (in volts per radian) = Cmult
voltage (in volts) divided by 4π.
If the secondary loop is not used, PLLi should be placed in
standby and PDouti should be left open.
5D. ANALOG OUTPUTS
DAC1 and DAC2
Pins 3 and 4 — Digital–to–Analog Converter Outputs
These are independent outputs of the two 8–bit D/A
converters. The output voltage is determined by bits in the D
register. Each output is a static level with an output
impedance of approximately 100 kΩ .
The DACs may be used for crystal oscillator trimming, PA
(power amplifier) output power control, or other
general–purpose use.
If a DAC output is not used, the pin should be left open.
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5E. EXTERNAL COMPONENTS
5F. SUPPLY PINS
Rx
Pin 17 — Current–Setting Resistor
DAC Vpos
Pin 2 — Positive Supply Potential for DACs
An external resistor to Gnd at this pin sets a reference
current that is used to determine the current at the
phase/frequency detector outputs PDout–Hi and PDout–Lo.
A value of 2 kΩ is required.
This pin supplies power to both DACs and determines the
full–scale output of the DACs. The full–scale output is
approximately equal to the voltage at DAC Vpos. The voltage
applied to this pin may be more, less, or equal to the potential
applied to the Vpos pins. The voltage range for DAC Vpos is
1.8 to 3.6 V with respect to the Gnd pins.
If both DACs are not used, DAC Vpos should be tied to the
same potential as Vpos.
Freescale Semiconductor, Inc...
Cmult
Pin 21 — Voltage–Multiplier Capacitor
An external capacitor to Gnd at this pin is used for the
on–chip voltage multiplier circuit. The value of this capacitor
must be greater than 20 times the value of the largest loop
filter capacitor. For example, if the largest loop filter capacitor
on either the main loop or the secondary loop is 0.01 µF, then
a 0.22 µF capacitor could be used on the Cmult pin.
To ensure minimum standby supply current drain, the
voltage potential at the Cmult pin must not be allowed to fall
below the potential at the Vpos pins. Therefore, if the
keep–alive oscillator is shut off, the user should tie a large
value resistor (> 10 MΩ) between the Cmult pin and Vpos. This
resistor should be sized to overcome leakage from Cmult to
Gnd due to the printed circuit board and the external
capacitor. The consequence of not using the resistor is
higher supply current drain in standby. If standby is not used,
the resistor is not necessary. Also, if the keep–alive oscillator
is used, the resistor can be omitted.
Vpos
Pins 11, 24, 26, and 29 — Principal Positive Supply
Potential
These pins supply power to the main portion of the chip.
All Vpos pins must be at the same voltage potential. The
voltage range for Vpos is 1.8 to 3.6 V with respect to the Gnd
pins.
For optimum performance, all Vpos pins should be tied
together and bypassed to a ground plane using a
low–inductance capacitor mounted very close to the device.
Lead lengths and printed circuit board traces between the
capacitor and the IC package should be minimized. (The
very–fast switching speed of the device can cause excessive
current spikes on the power leads if they are improperly
bypassed.)
Creg
Pin 22 — Regulator Capacitor
Gnd
Pins 14, 15, 18, and 31 — Ground
An external capacitor to Gnd at this pin is required for the
on–chip voltage regulator. A value of 1 µF is recommended.
Common ground for the device. All Gnd pins must be at
the same potential and should be tied to a ground plane.
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15
16
Figure 13.
2
X
1
X
X
3
X
4
A2
0
0
6
A3
5
0
A1
7
0
A0
8
X
9
X
10
X
11
X
12
C6
C7
D in
X
13
C5
3
X
14
C4
4
X
15
C3
5
NOTES:
1. To access the C register, either 8 or 32 clock cycles can be used.
2. For the 8–bit stream, no address bits are needed.
3. For the 32–bit stream, address bits A3 through A0 are required.
4. At this point, the new byte is transferred to the C register. No other register is affected.
5. X signifies a don’t care bit.
Din
Clk
Enb
2
1
Clk
Enb
X
16
C2
6
X
17
C1
7
8
C0
X
18
Note 4
X
19
Figure 13. C Register Access and Formats
X
20
X
21
X
22
X
23
X
24
Freescale Semiconductor, Inc...
C7
25
C6
26
C5
27
C4
28
C3
29
C2
30
C1
31
32
C0
Note 4
Freescale Semiconductor,
Inc.
MC145181
6. DETAILED REGISTER DESCRIPTIONS
6A. C REGISTER
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com
Freescale Semiconductor,
Inc.
MC145181
C REGISTER BITS
PDi Float (C3)
See Figure 13 for C register access and serial data
formats.
This bit controls the phase/frequency detector for the
secondary loop, output PDouti. When this bit is 0, the
secondary phase detector operates normally. When the bit is
1, the output is forced to the floating state which opens the
loop and allows modulation to be introduced into the external
VCO input. During this time, the counters are still active. This
bit is inhibited from affecting the phase detector during a
PDouti pulse.
If the loop is locked prior to C3 being set to 1, the lock
detect signal from the secondary loop continues to indicate
“lock” immediately after PDi Float is set to 1. If the phase of
the loop drifts outside the lock detect window, then the lock
detect signal indicates “not locked”. If the loop is not locked,
and PDi Float is set to 1, then the lock detect signal from the
secondary loop continues to indicate “not locked”.
Out A (C7)
When the Output A pin is selected as a General–Purpose
Output (via bits Ri21 = Ri20 = 0), bit C7 determines the state
of the pin. When C7 is 1, Output A is forced to a high level.
When C0 is 0 Output A is forced low.
When Output A is not selected as a General–Purpose
Output, bit C7 has no function; i.e., C7 is a “don’t care” bit.
Freescale Semiconductor, Inc...
Out B/XRef (C6)
Bit C6 is a dual–purpose bit.
When the Mode pin is tied low, C6 and C1 (PLL Stby), can
be used to control Output B. See Table 12. (The reference
circuit defaults to crystal configuration.)
When the Mode pin is tied high, additional control of the
reference circuit is allowed. See Table 13.
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Table 12. Out B/XRef Bit with Mode Pin = Low
Bit C6
Bit C1
State of
Output B Pin
Condition of
Main PLL
0
0
Low level
Active
0*
1*
High impedance*
Standby*
1
0
High level
Active
1
1
High impedance
Standby
*Power up default.
Table 13. Out B/XRef Bit with Mode Pin = High
Bit C6
Reference Configuration
0*
Supports Crystal*
1
Accommodates External Reference
*Power up default.
Out C (C5)
This bit determines the state of the Output C pin. When C5
is 1, Output C is forced to a high–impedance state. When C5
is 0, Output C is forced low.
PD Float (C4)
This bit controls the phase detector for the main loop,
outputs PDout–Hi and PDout–Lo. When this bit is 0, the main
phase detector operates normally. When the bit is 1, the
outputs are forced to the floating state which opens the loop
and allows modulation to be introduced into the external VCO
input. During this time, the counters are still active. This bit is
inhibited from affecting the phase detector during a PDout–Hi
or PDout–Lo pulse.
If the loop is locked prior to C4 being set to 1, the lock
detect signal from the main loop continues to indicate “lock”
immediately after PD Float is set to 1. If the phase of the loop
drifts outside the lock detect window, then the lock detect
signal indicates “not locked”. If the loop is not locked, and PD
Float is set to 1, then the lock detect signal from the main loop
continues to indicate “not locked”.
Osc Stby (C2)
This bit controls the crystal oscillator and external
reference input circuit. When this bit is 0, the circuit is active.
When the bit is 1, the circuit is shut down and is in the
low–power standby mode. When this circuit is shut down, a
keep–alive oscillator for the voltage doubler is activated,
unless the doubler is shut off via bits in the Ri register. In the
crystal oscillator mode, when C2 transitions from a 1 to a 0
state, a kick–start circuit is engaged for a few milliseconds.
The kick–start circuit ensures self–starting for a
properly–designed crystal oscillator
NOTE
Whenever C2 is 1, both bits C1 and C0 must be
1, also.
To minimize standby supply current, the voltage multiplier
may be shut down (by bits Ri19, Ri18, and Ri17 being all
zeroes). If this is the case and the voltage multiplier feature is
being used, the user must allow sufficient time for the
phase/frequency detector supply voltage to pump up when
the multiplier is brought out of standby. This “pump up” time is
dependent on the Cmult capacitor size. Pump current is
approximately 100 µA. During the pump up time, either the
PLL standby bits C1 and C2 must be 1 or the phase/
frequency detector float bits C3 and C4 must be 1.
PLL Stby (C1)
When set to 1, this bit places the main PLL in the standby
mode for reduced power consumption. PDout–Hi and
PDout–Lo are forced to the floating state, the N and R
counters are inhibited from counting, the main loop’s input
amp is shut off, the Rx current is inhibited, and the main
phase/frequency detector is shut off. The reference oscillator
circuit is still active and independently controlled by bit C2.
When this bit is programmed to 0, the main PLL is taken
out of standby in two steps. First, the input amplifier is
activated, all counters are enabled, and the Rx current is no
longer inhibited. Any fR and fV signals are inhibited from
toggling the phase/frequency detectors and lock detector at
this time. Second, when the fR pulse occurs, the N counter is
loaded, and the phase/frequency and lock detectors are
initialized via both flip–flops being reset. Immediately after
the load, the N and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
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17
Freescale Semiconductor,
Inc.
MC145181
and lock detectors, and the phase/frequency detector output
is enabled to issue an error correction pulse on the next fR
and fV pulses. (Patent issued on this method.)
During standby, data is retained in all registers and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
PLLi Stby (C0)
Freescale Semiconductor, Inc...
When set to 1, this bit places the PLLi section of the chip,
which includes the on–chip fini input amp, in the standby
mode for reduced power consumption. PDouti is forced to the
floating state. The Ri and Ni counters are inhibited from
counting and placed in the low–current mode. The exception
is the Ri counter’s prescaler when the Mode pin is low. The
Ri counter’s prescaler remains active along with the fout and
fout pins when PLLi is placed in standby (Mode pin = low).
When the Mode pin is low, the fout pin, fout pin, and Ri
counter’s prescaler are shut down only when Osc Stby bit C2
is set to 1.
When C0 is reset to 0, PLLi is taken out of standby in two
steps. All PLLi counters and the input amp are enabled. Any
fRi and fVi signals are inhibited from toggling the associated
phase/frequency detector at this time. Second, when the fRi
pulse occurs, the Ni counter is loaded and the phase/
frequency detector is initialized via both flip–flops being
reset. Immediately after the load, the Ni and Ri counters
begin counting down together. At this point, the fRi and fVi
pulses are enabled to the phase and lock detectors, and the
phase/frequency detector output is enabled to issue an error
correction pulse on the next fRi and fVi pulses. (Patent issued
on this method.)
During standby, data is retained in all registers, and any
register may be accessed. When setting or clearing the PLLi
Stby bit, other bits in the C register may be changed
simultaneously.
18
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
Go to: www.freescale.com
D in
Clk
2
X
1
X
X
3
X
4
A2
0
0
6
A3
5
0
A1
7
2
1
A0
8
X
9
4
X
10
X
11
R13 R12
3
See Below
R15 R14
1
6
X
12
R9
7
X
13
X
14
See Below
R11 R10
5
X
15
R8
8
X
16
R7
9
R5
11
R15
17
19
R4
12
20
R3
13
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
19
R1
15
0
0
.
.
.
2
2
2
2
2
2
2
.
.
.
F
F
R11
21
0
1
.
.
.
6
7
8
9
A
B
C
.
.
.
E
F
R10
22
16
R8
24
R7
25
R6
26
27
R5
Decimal (Note 7)
R Counter Ratio = 32,767
R Counter Ratio = 32,767.5
Not Allowed
Not Allowed
R Counter Ratio = 20
R Counter Ratio = 20.5
R Counter Ratio = 21
R Counter Ratio = 21.5
R Counter Ratio = 22
Not Allowed
Not Allowed
R9
23
R0
Note 4
See Below
R2
14
Hexadecimal
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
R14 R13 R12
18
See Below
R6
10
NOTES:
1. To access the Hr register (the holding register or first buffer of the double–buffered Hr and
R combination), either 16 or 32 clock cycles can be used.
2. For the 16–bit stream, no address bits are needed.
3. For the 32–bit stream, address bits A3 through A0 are required.
4. At this point, the two new bytes are transferred to the Hr register. Therefore, the R counter
divide ratio is not altered yet and retains the previous ratio loaded. No other register is affected.
5. A transfer from Hr (holding) register to the R register occurs with each N register access.
6. X signifies a don’t care bit.
7. The decimal value multiplied by 2 = the hexadecimal value.
Figure 14.
Enb
D in
Clk
Enb
Figure 14. Hr Register Access and Formats
Freescale Semiconductor, Inc...
R4
28
R3
29
R2
30
R1
31
32
R0
Note 4
Freescale Semiconductor,
Inc.
MC145181
6B. Hr REGISTER
20
D in
Clk
Enb
Figure 15.
X
X
X
3
X
4
N23
1
A2
0
0
6
7
1
4
8
0
A0
N20
A1
See Below
A3
5
3
N22 N21
2
6
10
11
LD
Window
Control
N23 N22 N21
9
8
9
Phase
Detector
Program
N20
12
11
13
14
See Below
N14 N13
10
15
Current
Ratio
12
13
14
N9
15
17
19
N8
16
20
N7
17
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
1
1
N5
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
23
N4
N1
25
27
Not Allowed
Not Allowed
N Counter Ratio = 992
N Counter Ratio = 993
N Counter Ratio = 994
N Counter Ratio = 995
N Counter Ratio = 996
Decimal
N4
28
Hexadecimal
Not Allowed
Not Allowed
N6
26
24
N0
N5
23
N Counter Ratio = 262,142
N Counter Ratio = 262,143
0
0
.
.
.
D
D
E
E
E
E
E
.
.
.
F
F
N2
22
See Below
N7
21
N3
24
N8
20
Note 4
0
1
.
.
.
E
F
0
1
2
3
4
.
.
.
E
F
0
0
.
.
.
3
3
3
3
3
3
3
.
.
.
F
F
N10
22
N9
19
See Below
21
Binary
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
1
1
18
N6
N14 N13 N12 N11
18
See Below
N10
N16 N15
16
N12 N11
N19 N18 N17
N17 N16 N15
7
See Below
N19 N18
5
NOTES:
1. To access the N register, either 24 or 32 clock cycles can be used.
2. For the 24–bit stream, no address bits are needed.
3. For the 32–bit stream, address bits A3 through A0 are required.
4. At this point, the three new bytes are transferred to the N register. In addition, an Hr to
R and Hn’ to N’ transfer occurs.
5. X signifies a don’t care bit.
2
1
D in
Clk
Enb
Figure 15. N Register Access and Formats
Freescale Semiconductor, Inc...
N3
29
N2
30
N1
31
32
N0
Note 4
Freescale Semiconductor,
Inc.
MC145181
6C. N REGISTER
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com
Freescale Semiconductor,
Inc.
MC145181
See Figure 15 for N register access and serial data
formats.
Control (N23)
When the Mode pin is low, Control bit N23 determines the
divide ratio of the auxiliary divider which feeds the buffers for
the fout and fout pins. See Table 14 for the overall ratio
between Osce and fout/fout.
When the Mode pin is high, N23 must be programmed
to 1.
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
Table 14. Osce to fout Frequency Ratio,
Mode = Low
Freescale Semiconductor, Inc...
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Table 16. Main Phase Detector Control
N REGISTER BITS
N23
Ri 1
Ri 0
Osce to fout
Frequency Ratio
0
0
0
10:1
0
0
1
12.5:1
0
1
0
12.5:1
0
1
1
12.5:1
1
0
0
8:1
1
0
1
10:1
1
1
0
10:1
1
1
1
10:1
LD Window (N22)
Bit N22 determines the lock detect window for the main
loop. Refer to Table 15 and Figure 19.
ÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Table 15. Lock Detect Window
N22
LD Window
(Approximated)
0
32 Osce periods
1
128 Osce periods
Phase Detector Program (N21, N20, N19)
These bits control which phase detector outputs are active
for the main loop. These bits also control the timer interval
when adapt is utilized for the main loop. See Table 16.
N21
N20
N19
Result
0
0
0
Both PDout–Hi and PDout–Lo floating
0
0
1
PDout–Hi floating, PDout–Lo enabled
0
1
0
PDout–Hi enabled, PDout–Lo floating
0
1
1
Both PDout–Hi and PDout–Lo enabled
1
0
0
PDout–Hi enabled and PDout–Lo
floating for 16 fR cycles, then PDout–Hi
floating and PDout–Lo enabled
1
0
1
PDout–Hi enabled and PDout–Lo
floating for 32 fR cycles, then PDout–Hi
floating and PDout–Lo enabled
1
1
0
PDout–Hi enabled and PDout–Lo
floating for 64 fR cycles, then PDout–Hi
floating and PDout–Lo enabled
1
1
1
PDout–Hi enabled and PDout–Lo
floating for 128 fR cycles, then
PDout–Hi floating and PDout–Lo
enabled
Current Ratio (N18)
This bit allows for MCU control of the PDout–Hi to
PD out –Lo current (or gain) ratio on the main loop
phase/frequency detector outputs. See Table 17.
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
Table 17. PDout–Hi to PDout–Lo Current Ratio
N18
PDout–Hi to
PDout–Lo
Current Ratio
PDout–Hi
Current
Cmult
Pin = 5 V
(Nominal)
PDout–Lo
Current
Cmult
Pin = 5 V
(Nominal)
0
4:1
4.4 mA
1.1 mA
1
8:1
4.4 mA
0.55 mA
N Counter Divide Ratio (N17 to N0)
These bits control the N Counter divide ratio or loop
multiplying factor. The minimum allowed value is 992. The
maximum value is 262,143. For ease of programming, binary
representation is used. For example, if a divide ratio of 1000
is needed, the 1000 in decimal is converted to binary
00 0000 0011 1110 1000 and is loaded into the device for
N17 to N0. See Figure 15.
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21
22
D in
X
X
X
3
X
4
A2
1
0
6
A3
5
0
A1
7
1
A0
8
10
11
12
13
14
15
16
17
18
19
20
21
22
Y
Coefficient
Output A
Function
V–Mult
Control
Tst/Rst
(User must
Program to 0)
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
0
0
.
.
.
2
2
2
2
2
2
2
.
.
.
F
F
R’9
23
24
0
1
.
.
.
6
7
8
9
A
B
C
.
.
.
E
F
R’8
Hexadecimal
R’23 R’22 R’21 R’20 R’19 R’18 R’17 R’16 R’15 R’14 R’13 R’12 R’11 R’10
9
NOTES:
1. To access the R’ register, 32 clock cycles must be used.
2. Address bits A3 through A0 are required.
3. At this point, the three new bytes are transferred to the R’ register. No other register is affected.
4. The decimal value multiplied by 2 = the hexadecimal value. Counter divide ratios shown apply when
the Mode pin is tied high. For ratios when the Mode pin is tied low, see Table 21.
5. X signifies a don’t care bit.
2
1
Figure 16.
Clk
Enb
Figure 16. R’ Register Access and Format
Freescale Semiconductor, Inc...
R’6
26
R’5
27
R’4
28
R’3
29
Decimal (Note 4)
R’ Counter Ratio = 32,767
R’ Counter Ratio = 32,767.5
Not Allowed
Not Allowed
R’ Counter Ratio = 20
R’ Counter Ratio = 20.5
R’ Counter Ratio = 21
R’ Counter Ratio = 21.5
R’ Counter Ratio = 22
Not Allowed
Not Allowed
R’7
25
R’2
30
R’1
31
32
R’0
Note 3
Freescale Semiconductor,
Inc.
MC145181
6D. Ri REGISTER
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com
Freescale Semiconductor,
Inc.
MC145181
Ri REGISTER BITS
See Figure 16 for Ri register access and serial data
format.
Y Coefficient (Ri23 and Ri22)
These bits are programmed per Table 18. Note that for the
MC145181, the bits are always programmed as 0 0. For
compatibility, the other combinations are reserved for use
with the MC145225 and MC145230.
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Freescale Semiconductor, Inc...
Table 18. Y Coefficient
Ri23
Ri22
Maximum Allowed
Frequency at fin Pin
0
0
550 MHz
0
1
(not used)
1
0
(not used)
1
1
(not used)
Output A Function (Ri21 and Ri20)
These bits control the function of the Output A pin per
Table 19. When selected as a general–purpose output, bit C7
controls the state of the pin. The signals fR and fRi are the
outputs of the R and Ri counters, respectively. The selection
as a detector pulse is a test feature.
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Table 19. Output A Function Selection
Ri21
Ri20
Function Selected
for Output A
0
0
General–Purpose Output
0
1
fR
1
0
fRi
1
1
Phase/Frequency Detector
Pulse from either loop
V–Mult Control (Ri19, Ri18, Ri17)
These bits control the voltage multiplier per Table 20.
When the multiplier is in the active state, the bits determine
the voltage multiplier’s refresh rate of the capacitor tied to the
Cmult pin.
When active, the bits should be programmed for the
lowest possible maximum frequency shown in the table. This
ensures that the voltage multiplier is operating at optimum
efficiency. For example, for a system utilizing a 16.8 MHz
reference, bits Ri19, Ri18, and Ri17 should be programmed
as 0 0 1 if the user desires to use the voltage multiplier. If the
user does not want to use the multiplier, the bits should be
programmed as 0 0 0. In the latter case, only a 0.1 µF bypass
capacitor is needed at the Cmult pin and an external
phase/frequency detector supply voltage of 3.6 to 5.25 V
must be provided to the Cmult pin.
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Table 20. Voltage Multiplier Control
Maximum Allowed
Frequency at
Osce Pin
Ri19
Ri18
Ri17
Multiplier
State
0
0
0
Inactive
80 MHz
0
0
1
Active
20 MHz
0
1
0
Active
40 MHz
0
1
1
Active
80 MHz
1
X
X
—
(for factory evaluation)
Test/Rst (Ri16)
This bit must be programmed to 0 by the user.
Ri Counter Divide Ratio (Ri15 to Ri0)
These bits control the Ri counter divide ratio. Thus, these
bits determine the secondary loop’s minimum step size. This
step size is the same as the phase/frequency detector’s
operating frequency which must not exceed 600 kHz.
With the Mode pin tied high, the minimum allowed value is
20. The maximum value is 32,767.5. For ease of
programming, binary representation is used. However, the
binary value must be multiplied by 2. For example, if a divide
ratio of 1000 is needed, the 1000 in decimal is converted to
binary 0000 0011 1110 1000. This value is multiplied by 2
and becomes 0000 0111 1101 0000 and is loaded into the
device for Ri15 to Ri0. See Figure 16.
With the Mode pin tied low, Table 21 shows the divide
ratios available. There are two formulas for the divide ratio
when Mode is low.
If Ri1 Ri0 are 0 0: Ri Ratio = (Value of Ri15 to Ri2) x 2.
If Ri1 Ri0 are 0 1, 1 0, 1 1: Ri Ratio = (Value of Ri15 to Ri2)
x 2.5.
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
Go to: www.freescale.com
23
Freescale Semiconductor,
Inc.
MC145181
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ÁÁ
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ÁÁ
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ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
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ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 21. Ri Counter Divide Ratios with Mode Pin Tied Low*
Ri15
Ri14
Ri13
Ri12
Ri11
Ri10
Ri 9
Ri 8
Ri 7
Ri 6
Ri 5
Ri 4
Ri 3
Ri 2
Ri 1
Ri 0
Ri Counter
Divide Ratio
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Allowed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Not Allowed
Freescale Semiconductor, Inc...
L
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
Not Allowed
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
20
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
25
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
X
25
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
22
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
27.5
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
X
27.5
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
24
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
30
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
X
30
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
26
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
32.5
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
X
32.5
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
32,766
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
40,957.5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
40,957.5
* Divide ratios with the Mode pin tied high are shown in Figure 16.
24
For More Information On This Product, MOTOROLA RF/IF DEVICE DATA
Go to: www.freescale.com
D in
Clk
Enb
Figure 17.
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
Go to: www.freescale.com
X
X
X
3
X
4
A2
1
0
6
A3
5
0
A1
7
0
A0
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
X
16
18
19
20
21
22
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
F
F
0
0
.
.
.
9
9
9
9
9
9
9
.
.
.
F
F
N’9
23
24
0
1
.
.
.
6
7
8
9
A
B
C
.
.
.
E
F
N’8
Hexadecimal
N’15 N’14 N’13 N’12 N’11 N’10
17
NOTES:
1. To access the Hn’ register (the holding register or first buffer of the double–buffered Hn’ and N’ combination),
32 clock cycles must be used.
2. Address bits A3 through A0 are required.
3. At this point, the two new bytes are transferred to the Hn’ register. Therefore, the N’ counter divide ratio is not
altered yet and retains the previous ratio loaded. No other register is affected.
4. A transfer from the Hn’ (holding) register to the N’ register occurs with each N register access.
5. X signifies a don’t care bit.
6. The decimal value multiplied by 8 = the hexadecimal value.
2
1
Figure 17. Hn’ Register Access and Format
Freescale Semiconductor, Inc...
N’6
26
N’5
27
N’4
28
N’3
29
Decimal (Note 6)
N’ Counter Ratio = 8,190
N’ Counter Ratio = 8,191
Not Allowed
Not Allowed
N’ Counter Ratio = 19
N’ Counter Ratio = 20
N’ Counter Ratio = 21
N’ Counter Ratio = 22
N’ Counter Ratio = 23
Not Allowed
Not Allowed
N’7
25
N’2
30
N’1
31
32
N’0
Note 3
Freescale Semiconductor,
Inc.
MC145181
6E. Hni REGISTER
25
26
D in
Clk
Enb
Figure 18.
X
X
0
0
0
0
.
.
.
F
F
F
X
4
0
1
2
3
.
.
.
D
E
F
Hexadecimal
X
3
0
0
1
A1
7
1
A0
8
X
9
X
10
X
11
X
12
Decimal
Full Scale – 2 LSB Output, Vout = (DAC Vpos) (253/256)
Full Scale – 1 LSB Output, Vout = (DAC Vpos) (254/256)
Full Scale Output, V out = (DAC Vpos) (255/256)
X
13
Zero Output, Vout = (DAC Vpos ) (0/256) (Note 4)
Zero + 1 LSB Output, Vout = (DAC Vpos ) (1/256)
Zero + 2 LSB Output, Vout = (DAC Vpos ) (2/256)
Zero + 3 LSB Output, Vout = (DAC Vpos ) (3/256)
A2
6
A3
5
X
14
X
15
X
16
D15
17
DAC2
NOTES:
1. To access the D Register, 32 clock cycles are used.
2. Address bits A3 through A0 are required.
3. At this point, the two new bytes are transferred to the D register. No other register is affected.
4. Low–power standby state.
5. X signifies a don’t care bit.
2
1
D14
18
D13
19
21
D12 D11
20
Figure 18. D Register Access and Format
0
0
0
0
.
.
.
F
F
F
D9
23
0
1
2
3
.
.
.
D
E
F
D8
24
Hexadecimal
D10
22
Freescale Semiconductor, Inc...
D6
26
D5
27
D4
28
D3
29
D2
30
D1
31
D0
32
DAC1
Decimal
Full Scale – 2 LSB Output, Vout = (DAC Vpos) (253/256)
Full Scale – 1 LSB Output, Vout = (DAC Vpos) (254/256)
Full Scale Output, Vout = (DAC Vpos) (255/256)
Zero Output, Vout = (DAC Vpos ) (0/256) (Note 4)
Zero + 1 LSB Output, Vout = (DAC Vpos ) (1/256)
Zero + 2 LSB Output, Vout = (DAC Vpos ) (2/256)
Zero + 3 LSB Output, Vout = (DAC Vpos ) (3/256)
D7
25
Note 3
Freescale Semiconductor,
Inc.
MC145181
6F. D REGISTER
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MC145181
Figure 19. Lock Detector Operation
One fR Period
fR vs fV
Phase
Relationship
< LD
< LD
< LD
< LD
< LD
< LD
> LD
> LD
> LD
Window Window Window Window Window Window Window Window Window
Locked
Freescale Semiconductor, Inc...
LD
Output
Unlocked
NOTES:
1. Illustration shown is for the main loop and applies when the secondary loop is either phase locked or in
standby. The actual detector outputs for each loop are ANDed together at the LD pin.
2. The secondary loop is similar to the above illustration.
3. The approximate lock detect window for the main loop is either 64 or 256 Osce cycles and is programmable
via bit N22. The approximate window for the secondary loop is 64 Osce cycles and is not programmable.
4. The LD output is low whenever the phase difference is more than the lock detect window.
5. The LD output is high whenever the phase difference is less than the lock detect window and continues to
be less than the window for 3 fR periods or more.
LOCK DETECTOR OUTPUT CONDITIONS
fR versus fV Relation
Lock Detector Output
Microcontroller Action
Frequency is the same with phase inside the
LD window
Static high level output
Senses high level and no edges, therefore loop
is locked
Frequency is the same with phase outside
the LD window
Static low level output
Senses low level, therefore loop is unlocked
Frequency is slightly different, thus phase is
changing
Dynamic “chattering” output, output has
transitions
Senses edges, therefore loop is unlocked
Frequency is grossly different
Static low level output
Senses low level, therefore loop is unlocked
NOTE: For simplicity, this table applies to the main loop. The secondary loop is similar. The detector outputs feed an AND gate whose output is the LD pin.
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Freescale Semiconductor,
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Figure 20. PDout–Hi and PDout–Lo Detector Output Characteristics
fR
Reference
Osce ÷ R)
fV
VCO Feedback
(fin ÷ N)
*
PDout–Hi,
PDout–Lo
Source Current
Float
Sink Current
Freescale Semiconductor, Inc...
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the fout / Pol pin is low and the Mode pin is high.
3. When the fout / Pol pin is high and Mode is high, the PDout–Hi and PDout–Lo waveform is inverted.
4. The waveform shown is also the default when the Mode pin is low.
Figure 21. PDouti Detector Output Characteristics
fRi
Reference
Osce ÷ Ri)
fVi
VCO Feedback
(fini ÷ Ni)
PDouti
*
High Voltage
High Z
Low Voltage
*At this point, when both fRi and fVi are in phase, the output source and sink circuits are turned on for a short interval.
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance
and the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the fout / Poli pin is low and the Mode pin is high.
3. When the fout / Poli pin is high and Mode is high, the PDouti waveform is inverted.
4. The waveform shown is also the default when the Mode pin is low.
28
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Due to the series/parallel arrangement of the equivalent
components, the crystal exhibits two resonances. The first,
sometimes just called resonance, is the series resonance of
the Rs, Cs, Ls branch. The other, sometimes called the
anti–resonance, is the parallel resonance including Co. For
the series resonance the formula is
7. APPLICATIONS INFORMATION
Freescale Semiconductor, Inc...
7A. CRYSTAL OSCILLATOR CONSIDERATIONS
The oscillator/reference circuit may be connected to
operate in either of two configurations. With the Mode pin
plac ed “ high” a n d b i t C 6 p ro g ra mme d to 1, the
oscillator/reference circuit of the MC145181 will accept an
external reference input. The external reference signal
should be capacitive, connected to Osce with Oscb left
floating. Commercially available temperature compensated
crystal oscillators (TCXOs) or crystal–controlled data clock
oscillators provide a very stable reference frequency. For
additional information about TCXOs and data clock
oscillators, please consult the Electronic Engineers Master
Catalog, internet web page, or similar publication/service.
The on–chip Colpitts reference oscillator can be selected
by either tying the Mode pin low or by programming the C6 bit
to zero when Mode is high. The oscillator may be operated in
either the fundamental mode, as show by Figure 22, or as an
overtone oscillator. The “kick start” feature ensures reduced
“stalling” of hard–starting crystals.
fs =
1
.
Ls Cs
For parallel resonance, the formula is
2π
1
fp =
.
Ls Cs Co
C o + Cs
2π
As can be seen from this equation, the anti–resonant
frequency is higher than the series resonant frequency. The
ratio between the resonant and anti–resonant frequency can
be found using the formula
∆f
f
=
Cs
2 (Co + Cs)
where
Crystal Resonators
∆f = fs – fp
The equivalent circuit of a crystal resonator most
commonly used is shown in Figure 23. The crystal itself is a
specially cut (usually AT for overtone operation) block of
quartz. The dimensions, (shape, thickness, length, and
width) determine the operating characteristics of the crystal.
When deformed and allowed to return naturally to its resting
shape, it is observed to oscillate. This oscillation has the
typical characteristics of a damped oscillation and an
equivalent electrical signal can be found on the surface of the
crystal. In addition, if an equivalent electrical signal is applied
to the crystal, it will be observed to oscillate. The equivalent
values for Rs, Ls, Cs, and Co can be used to predict the
operation of the crystal when used as an electronic oscillator.
and
f +f
f= s p .
2
By exploiting this characteristic, the crystal oscillator
frequency can be tuned slightly. If a capacitor is connected in
series with the crystal operating in the resonance mode, the
frequency will shift upward. If a capacitance is added in
parallel with a crystal operating in an anti–resonant mode, the
frequency will be shifted down.
Figure 22. Fundamental Mode Oscillator Circuit
M1
+V
R1
C3
Q1
Oscb
C2
Frequency Synthesizer
Osce
X1
C1
R2
0
0
M2
I1
200/800 µA
0
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Figure 23. Crystal Resonator Equivalent Circuit
Ls
Rs
1
X1
2
Figure 24. Overtone Crystal Equivalent Circuit
Cs
1
2
1
L1s
R1s
2
Co
L3s
R3s
Xe
Re
1
Freescale Semiconductor, Inc...
Fundamental Mode
The equivalent circuit for the Colpitts oscillator operating in
the fundamental mode is shown in Figure 25.
C3 is selected to provide a small reduction in the inductive
property of the crystal. In this manner, the frequency of the
oscillator can be “pulled” slightly. The biasing combination of
C5s
Co
NOTE: Values are supplied by crystal manufacturer (parallel
resonant crystal).
Because of the acoustic properties of the crystal
resonator, the crystal “tank” responds to energy not only at its
fundamental frequency, but also at specific multiples of the
fundamental frequency. In the same manner that a shorted or
open transmission line responds to multiples of the
fundamental frequency, the crystal “tank” responds similarly.
A shorted half–wave transmission line (or closed acoustic
chamber) will not only resonate at its fundamental frequency,
but also at odd multiples of the fundamental. These are called
the overtones of the crystal and represent frequencies at
which the crystal can be made to oscillate. The equivalent
circuit of an overtone crystal is shown is Figure 24.
The components for the appropriate overtone are
represented by 1, 3, and 5. The fundamental components are
represented by 1, and those of importance for the third and
fifth overtones, by 3 and 5.
C3s
L5s
R5s
2
C1s
M1R1 and M2R2 provide the ability to start operation with a
higher than normal operating current to stimulate crystal
activity. This “kick start” current is nominally four times the
normal current. An internal counter times the application of
the “kick start” and returns the current to normal after the time
out period.
The mutual conductance (transconductance) of the
transistor Q1 is useful in determining the conditions
necessary for oscillation. The nominal value for the
transconductance is found from the formula
I
gm = e
26
where Ie is the emitter current in mA.
The operation of the oscillator can be described using the
concept of “negative resistance”. In a normal tuned circuit,
any excitation tends to be dissipated by the resistance of the
circuit and oscillation dies out. The resistive part of the crystal
along with the resistance of the wiring and the internal
resistance of C1, C2, and C3, make up this “damping”
resistance. Some form of energy must be fed back into the
circuit to sustain oscillation. This is the purpose of the
amplifier.
Figure 25. Fundamental Mode Colpitts Oscillator Equivalent Circuit
M1
+V
R1
Rst
C3
Q1
Oscb
C2
Frequency Synthesizer
C1s
L1s
Co
R1s
Osce
C1
R2
0
M2
I1
200/800 µA
0
0
30
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If we define the damping as resistive, we can define the
opposite or regenerative property as negative resistance.
Figure 26 shows the basic circuit of the Colpitts oscillator. C3
has been combined with the crystal elements for simplicity.
For the circuit to oscillate, there must be at least as much
“negative resistance” (regeneration) as there is resistance
(damping). We can define this by deriving the input
impedance for the amplifier.
Figure 26. Colpitts Oscillator Basic Circuit
Freescale Semiconductor, Inc...
Iin
Q1
C2
Vin
C1
If a driving signal is defined as Vin, the resultant current
that flows can be identified as Iin. The relationship of Vin to Iin
is
Vin = Iin (Zc1 + Zc2) – Ib (Zc2 – βZc1)
and
0 = Iin (Zc2) + Ib (Zc2 + rb)
where Ib is the base current of transistor Q1. Solving the two
equations and assuming Zc2 << rb, the input impedance can
be expressed as
1
–gm
+
Zin
ω2 C1 C2
C1 C2
Ǔ
jω ǒ
C1 + C2
where ω = 2πf. This is equivalent to the series combination of
a real part whose value is
–gm
REAL =
2
ω C1 C2
and the imaginary part whose value is
1
IMAG =
C1 C2
Ǔ
jω ǒ
C1 + C2
In determining values for C1, C2, and C3, two limits are
considered. At one end is the relationship of C3 to C2 and
C1. If C3 is made 0 or the reactance of C3 is small compared
to the reactance of C1 and C2, no adjustment of the crystal
frequency is possible. The other limit is the relationship
gm Zc1 Zc2 > Rsum
where Rsum is the sum of resistances in the resonant loop.
Since this equation must be true for the circuit to oscillate, it
is obvious that as the values of C1 and C2 are increased, the
series resistances must be reduced and/or gm increased.
Since gm is a function of device current and there is a
physical limit on how small Rsum can be made, at some point
oscillation can no longer be sustained.
Normally, it is desirable to choose the “negative
resistance” to be several times greater than the “damping”
resistance to ensure stable operation. A factor of four or five
is a good “rule of thumb” choice.
To determine crystal power, the equivalent circuit shown in
Figure 27 can be used. In this case, we are addressing a
condition where the transistor amplifier is operating at the
limit of class A; that is, the device is just at cutoff during the
peak negative excursions. At this point,
Re = gm Xc1 Xc2
if the amplitude is constant and the oscillator is stable. For
this to occur, the sum of all resistances in the resonant loop
will be equal to Re, where Re represents the effective
resistance of I1. This can be written as
Rsum = Rs + Rst = Re
where Rs is the crystal resistance and Rst is the additional
distributed resistances within the resonant loop. At the point
where the transistor enters cutoff we have the equation
–Iin =
v1 + v2
Xls + Re
=
(Iin – Ib) Zc2+ (Iin + βib) Zc1
Xls + Re
.
β = current gain of the transistor. Rewriting:
Iin =
Ib (Zc2 – βZc1)
Zc1 + Zc2 + Xls + Re
.
For oscillation to occur, we must have
Zc1 + Zc2 + Xls
0 .
If we assume βZc1 is normally much greater than Zc2 then
Iin
–Ie Zc1
Re
.
For the condition we have specified,
To sustain oscillation, the amplifier must generate a
“negative resistance” equal or greater than the REAL part of
the above equation and opposite in polarity.
–gm
Rneg =
2
ω C1 C2
As long as the relation
–Rneg = –SUM (Rs + Rst + Rc1 + Rc2 + Rc3) ,
the circuit will oscillate and the frequency of oscillation will be
defined as
1
fo =
2π
Ls (C1 || C2 || C3)
where C3 is the series frequency adjusting capacitor.
Ie(bias) + Ie(instantaneous ac) = 0
the transistor is just cutting off and the peak current, Iin is
equal to the bias current. The peak input current is
represented as
I |Z |
Iin(peak) = e c1 .
Re
The power dissipation of the series resistances in the
resonant loop can be written as
Iin(peak)2 R
(Ie|Zc1|)2
=
P=
2
2 Rsum
where Rsum = Re.
The power dissipation for the crystal itself becomes
(Ie|Zc1|)2
Pcrystal =
.
2 Rs
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Figure 27. Equivalent Circuit for Crystal Power Estimation
Iin
R1 || R2
lb
Ls
VCC x R2 / (R1 + R2)
C2
Blb
X1
Rs
Freescale Semiconductor, Inc...
C1
Overtone Operation
For overtone operation, the circuit is modified by the
addition of an inductor, L1; and a series capacitor, C4. C4 is
inserted as a dc blocking capacitor whose capacitance is
chosen sufficiently large so that its reactance can be ignored.
This circuit is shown in Figure 28.
For oscillation to occur at the overtone frequency, the
condition
gm Zc1 Zc2 > Rs
must exist.
Zc1 represents the impedance across C1 and can be
defined as
Zc1 = jXc1 || (Rl1 + jXl1)
where Rl1 is the dc resistance of the inductor L1.
For overtone operation, this must occur at the desired
harmonic. For example, if the crystal is chosen to oscillate at
the third overtone, C1 and C2 must be chosen so that the
above condition exists for Zc1 and Zc2 at the third harmonic of
the fundamental frequency for the crystal. In addition, care
must be taken that the “negative resistance” of the amplifier is
not sufficient at the fundamental frequency to induce
oscillation at the fundamental frequency. It may be necessary
to add additional filtering to reduce the gain of the amplifier at
the fundamental frequency. The key to achieving stable
overtone oscillator operation is ensuring the existence of the
above condition at the desired overtone while ensuring its
failure at all other frequencies.
L1 and C1 are chosen so that
1
> Ff
2π L1 C1
where Ff is the fundamental frequency of the crystal
resonator. If L1 and C1 are chosen to be net capacitive at the
desired overtone frequency and if the condition
gm Zc1 Zc2 > Rs
is true only at the desired overtone frequency, the oscillator
will oscillate at the frequency of the overtone. Normally, L1
and C1 are not chosen to be resonant at the overtone
frequency but at a lower frequency to ensure that the parallel
32
VCC
I1
Re
200/800 µA
combination of L1 and C1 is capacitive at the overtone
frequency and inductive at the fundamental frequency.
1
< Fo
L1 C1
The net inductance of the rest of the resonant loop then
balances this capacitance at the overtone frequency.
Ff <
2π
1
1
Xls – Xcs
–
+ Xl2 + Xl(stray) – Xc3
1
Xc0
1
+
1
–
=0
1
Xc1
L2 and C3 are chosen to provide the desired adjustment to
the resonant overtone frequency. This is normally computed
by calculating the expected ppm change at the resonant
frequency and using this to define the value of the reactance
necessary to produce this change.
Xl1
∆Ff (ppm) =
X (of L2 and C3)
Z (crystal at resonance)
∆Ff (ppm) = X(of L2 and C3)/Z(crystal at resonance)
The values needed for this calculation can be derived from
the value of the fundamental frequency and Co. If Co is
known or can be measured, Cs is defined as
Cs =
Co
200
for an AT cut crystal.
The fundamental frequency can be used to calculate the
value for Ls using either the series resonant or parallel
resonant formulas given earlier. Since the Q of the crystal,
Q= X
R
is usually sufficiently large at the resonant frequency so that
Rs << Z(crystal)
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MC145181
Rs can be ignored. The value for C3 and L2 are chosen so
that
Xc3 = Xl2
then
Xc3(max) >= 2[∆Ff (ppm)] Z(crystal)
and
when C3 is adjusted to approximately half its maximum
capacitance. At this setting, the combination produces a zero
change in the overtone frequency. If C3 is then chosen so
that Xc3 at minimum capacitance is
Xc(min)=
4
This results in an adjustable change in the operating
frequency of +[∆Ff (ppm)] and –[∆Ff (ppm)] / 2. If ratios nearer
to 1:1 are used for Xc3(max) and Xl2, the tuning range will be
skewed with a wider –[∆Ff (ppm)] but at the expense of less
adjustability over the +[∆Ff (ppm)] range.
[Xc3(max)] – Xl2 >= ∆Ff (ppm) Z(crystal)
and L2 is approximately
XI2 =
Xc(max)
Xc3(max)
2
Freescale Semiconductor, Inc...
Figure 28. Colpitts Oscillator Configured for Overtone Operation
M1
+V
R1
L2
C3
Q1
Oscb
C2
Frequency Synthesizer
X1
Osce
0
C1
L1
R2
0
M2
I1
200/800 µA
C4
0
0
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7B. MAIN LOOP FILTER DESIGN — CONVENTIONAL
Freescale Semiconductor, Inc...
The current output of the charge pump allows the loop
filter to be realized without the need of any active
components. The preferred topology for the filter is illustrated
in Figure 29.
The Ro / Co components realize the primary loop filter. Ca
is added to the loop filter to provide for reference sideband
suppression. If additional suppression is needed, the Rx / Cx
realizes an additional filter. In most applications, this will not
be necessary. If all components are used, this results in a
fourth order PLL, which makes analysis difficult. To simplify
this, the loop design will be treated as a second order loop
(Ro / Co), and additional guidelines are provided to minimize
the influence of the other components. If more rigorous
analysis is needed, mathematical/system simulation tools
should be used.
Component
Guideline
Ca
<0.1 x Co
Rx
>10 x Ro
Cx
<0.1 x Co
The focus of the design effort is to determine what the
loop’s natural frequency, ωo, should be. This is determined by
Ro, Co, Kp, Kv, and Nt. Because Kp, Kv, and Nt are given, it is
only necessary to calculate values for Ro and Co. There are
three considerations in selecting the loop bandwidth:
1. Maximum loop bandwidth for minimum tuning speed.
2. Optimum loop bandwidth for best phase noise
performance.
3. Minimum loop bandwidth for greatest reference
sideband suppression.
Usually a compromise is struck between these three
cases, however, for a fixed frequency application, minimizing
the tuning speed is not a critical parameter.
To specify the loop bandwidth for optimal phase noise
performance, an understanding of the sources of phase
noise in the system and the effect of the loop filter on them is
required. There are three major sources of phase noise in the
phase–locked loop — the crystal reference, the VCO, and
the loop contribution. The loop filter acts as a low–pass filter
to the crystal reference and the loop contribution. The loop
filter acts as a high–pass filter to the VCO with an in–band
gain equal to unity. The loop contribution includes the PLL IC,
as well as noise in the system; supply noise, switching noise,
etc. For this example, a loop contribution of 15 dB has been
selected.
The crystal reference and the VCO are characterized as
high–order 1/f noise sources. Graphical analysis is used to
determine the optimum loop bandwidth. It is necessary to
have noise plots from the manufacturers of both devices.
This method provides a straightforward approximation
suitable for quickly estimating the optimal bandwidth. The
loop contribution is characterized as white–noise or
low–order 1/f noise, given in the form of a noise factor which
combines all the noise effects into a single value. The phase
noise of the crystal reference is increased by the noise factor
of the PLL IC and related circuitry. It is further increased by
the total divide–by–N ratio of the loop. This is illustrated in
Figure 30. The point at which the VCO phase noise crosses
the amplified phase noise of the crystal reference is the point
of the optimum loop bandwidth. In the example of Figure 30,
the optimum bandwidth is approximately 15 kHz.
To simplify analysis further, a damping factor of 1 will be
selected. The normalized closed loop response is illustrated
in Figure 31 where the loop bandwidth is 2.5 times the loop
natural frequency (the loop natural frequency is the
frequency at which the loop would oscillate if it were
unstable). Therefore, the optimum loop bandwidth is
15 kHz/2.5 or 6.0 kHz (37.7 krads) with a damping
coefficient, ζ
1. T(s) is the transfer function of the loop
filter.
X
where
Nt = Total PLL Divide Ratio — 8 x N
where (N = 25 ... 40),
Kv = VCO Gain – 2π Hz/V,
Kp = Phase Detector/Charge Pump Gain – A
= ( |IOH | + |IOL | ) / 4π.
Technically, Kv and Kp should be expressed in radian units
[Kv (rad/V), Kp (A/rad)]. Since the component design
equation contains the Kv x Kp term, the 2π cancels and the
value can be expressed as AHz/V (amp hertz per volt).
Figure 29. Loop Filter
Xtl
Osc
R Counter
Ph/Frq
Det
Charge
Pump
Ro
Co
N Counter
PLL
34
VCO
Rx
Ca
0
Cx
0
0
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Figure 30. Graphical Analysis of
Optimum Bandwidth
Figure 31. Closed Loop Frequency Response
for ζ = 1
–60
10
3 dB Bandwidth
Closed Loop Response
–80
0
VCO
–90
–10
–100
–20
20 x log (Nt)
–110
dB
dB
Natural Frequency
Optimum Bandwidth
–70
–30
–120
–40
–130
15 dB NF of the Noise
Contribution from Loop
–140
–50
Crystal Reference
–150
Freescale Semiconductor, Inc...
10
100
1k
10 k
100 k
1M
–60
0.1
1.0
Hz
In summary, follow the steps given below:
Step 1: Plot the phase noise of crystal reference and the
VCO on the same graph.
Step 2: Increase the phase noise of the crystal reference by
the noise contribution of the loop.
Step 3: Convert the divide–by–N to dB (20log 8 x N) and
increase the phase noise of the crystal reference by
that amount.
Step 4: The point at which the VCO phase noise crosses the
amplified phase noise of the crystal reference is the
point of the optimum loop bandwidth. This is
approximately 15 kHz in Figure 30.
Step 5: Correlate this loop bandwidth to the loop natural
frequency per Figure 31. In this case the 3.0 dB
bandwidth for a damping coefficient of 1 is 2.5 times
the loop’s natural frequency. The relationship
between the 3.0 dB loop bandwidth and the loop’s
“natural” frequency will vary for different values of ζ.
Making use of the equations defined in Figure 32, a
math tool or spread sheet is useful to select the
values for Ro and Co.
Appendix: Derivation of Loop Filter Transfer Function
The purpose of the loop filter is to convert the current from
the phase detector to a tuning voltage for the VCO. The total
transfer function is derived in two steps.
Step 1 is to find the voltage generated by the impedance of
the loop filter.
Step 2 is to find the transfer function from the input of the
loop filter to its output. The “voltage” times the “transfer
function” is the overall transfer function of the loop filter. To
use these equations in determining the overall transfer
function of a PLL, multiply the filter’s impedance by the gain
constant of the phase detector, then multiply that by the
filter’s transfer function. Figure 33 contains the transfer
function equations for the second, third, and fourth order PLL
filters.
PSpice Simulation
The use of PSpice or similar circuit simulation programs
can significantly reduce laboratory time when refining a PLL
10
Hz
100
1.0 k
design. The following describes the use of behavioral
modeling to develop useful models for studying loop filter
performance. In many applications the levels of sideband
spurs can also be studied.
Behavioral modeling is chosen, as opposed to discrete
device modeling, to improve performance and reduce
simulation time. PLL devices can contain several thousand
individual transistors. To simulate at this level can result in
generation of an enormous amount of data when compared
to a simpler behavioral model. For example, a logic NAND
gate can contain several transistors. Each of these requires a
data set for each of the transistor terminals. If a half dozen
transistors are used in the gate design, both current and
voltage measurements for each terminal of each device for
every node in the circuit is calculated. The gate can be
expressed as a behavioral model, which is treated and
simulated as a single device. Since PSpice sees this as a
single rather than multiple devices, the amount of
accumulated data is much less, resulting in a faster
simulation.
For applications using integrated circuits such as PLLs, it
is desirable to investigate the performance of the circuitry
added externally to the integrated circuit. By using behavioral
modeling rather than discrete device modeling to represent
the integrated circuit, the engineer is able to study the
performance of the design without the overhead contributed
by simulating the integrated circuit.
Phase Frequency Detector Model
The model for the phase frequency detector is derived
using the waveforms shown in Figure 20. Two signals are
present at the input of the phase frequency detector. These
are the reference input and the feedback from the VCO
and/or prescaler. The two signals are compared to determine
the lag/lead relationship between the two signals and pulses
generated to represent the leading edge of each signal. A
pulse whose width equals the lead of one input signal over
the other is generated by an RS flip–flop (RSFF). One RSFF
generates a pulse whose width equals the lead of the
reference signal over the feedback signal, and a second
RSFF generates a signal whose width is the lead of the
feedback signal over the reference signal. The logical model
for the phase frequency detector is shown in Figure 34.
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Figure 32. Design Equations for the Second Order System
ǒ Ǔ
ǒ Ǔ
ǒ Ǔ ǒ Ǔ
ǒ Ǔ ǒ Ǔ³
ǒ Ǔ
³
ǒ Ǔ³ ǒ Ǔ ³ ǒ Ǔ
RoCos + 1
T(s) =
NCo
KpKv
NCo
=
KpKv
ωo =
2ζ
ωo
ζ=
Freescale Semiconductor, Inc...
RoCo =
=
s+1
1
s2 +
ωo2
s2 + RoCos + 1
1
ωo2
2ζ
ωo
2ζ
s+1
ωo
KpKv
NCo
Co =
KpKv
Nωo2
ωoRoCo
2
Ro =
2ζ
ωoCo
Figure 33. Overall Transfer Function of the PLL
For the Second Order PLL: Vp
Vt
ZLF(s) =
RoCos + 1
Cos
TLF(s) =
Vt(s)
=1 ,
Vp(s)
ZLF(s) =
RoCos + 1
CoRoCas2 + (Co + Ca)s
TLF(s) =
Vt(s)
=1 ,
Vp(s)
Ro
Co
For the Third Order PLL:
Vp
Vt
Ro
Ca
Co
For the Fourth Order PLL:
Vp
Vp(s) = Kp(s)ZLF(s)
Vp(s) = Kp(s)ZLF(s)
Vt
Ro
Ca
Cx
Co
ZLF(s) =
TLF(s) =
36
(RoCos + 1) (RxCxs + 1)
CoRoCaRxCxs3 + [(Co + Ca)RxCx + CoRo (Cx + Ca)] s2 + (Co + Ca + Cx)s
Vt(s)
1
=
,
Vp(s)
(RxCxs + 1)
Vp(s) = Kp(s)ZLF(s)
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Figure 34. Phase Frequency Detector Logic Diagram
PG1
Ref
RSFF1
In
Out
S
P1
Rφ
P1
Vφ
R
Pulse Generator
RSFF2
Freescale Semiconductor, Inc...
PG2
In
R
In
Out
S
Pulse Generator
The behavioral model of the phase frequency detector
shown in Figure 35 is derived using the phase frequency
detector logic diagram. Behavioral models for the pulse
generator, AND gate (Figure 36), and RS flip–flops
(Figure 37) are created using analog behavioral blocks. The
pulse generator is created using a delay block and a “gate”
defined by the behavioral expression:
If [V(v1) ≥ 1 & V(v2) , 1, 5, 0]
v1 and v2 represent the two inputs to the block.
This is the behavioral expression for an AND gate with one
input inverted. The addition of the delay element produces a
pulse whose width equals the delay element.
The pulses appearing at the output of HB1 and HB2
(Figure 35) are used to set the flip–flops, RSFF1, and
RSFF2. The leading pulse will set the appropriate flip–flop
resulting in a high at the output of that flip–flop. The output of
this flip–flop will remain high until the arrival of the second (or
lagging) pulse sets the second RS flip–flop. The presence of
a high on both RS flip–flop outputs results in the generation of
the reset pulse. The reset pulse is generated by the analog
behavioral block (configured as an AND gate) and the delay
element. The delay element is necessary to eliminate the
zero delay paradox of input to output to input.
The output of the phase frequency detector is two pulse
trains appearing at Rφ and Vφ. When the PLL is locked, the
pulses in both pulse trains will be of minimum width. When
the phase frequency detector is out of lock, one pulse train
will consist of pulses of minimum width while the width of the
pulses in the second train will be equal to the lead/lag
relationship of the input signals. If the Ref input leads ‘In’, the
pulse train at Rφ will consist of pulses whose width equals the
lead of Ref. If Ref lags ‘In’, the width of the pulses appearing
at Vφ will equal this lag.
The terms lead and lag used in this explanation represent
an occurrence in time rather than a phase relationship. At any
condition other than locked, one input (either In or Ref), will
be of a higher frequency. This results in the arrival of the
pulse at that input ahead of the pulse at the other input, or
leading. The second then is lagging.
To simulate the operation of the phase frequency detector
in an actual circuit, a charge pump needs to be added. The
behavioral model for this is shown in Figure 38. Two
voltage–to–current behavioral models are used to produce
the charge pump output. Two voltage–controlled switches
with additional behavioral models, monitor the voltage of the
output of the charge pump and clamp to 0 or VCC to simulate
a real circuit.
To ensure the model conforms to the PLL, the delay blocks
in the phase frequency detector should be set to the
expected value as specified by the MC145181 data sheet. In
addition, the charge pump sink and source current behavioral
model should also be set to deliver the desired current and
VCC specified to ensure correct clamping.
Modeling the VCO
The VCO (Figure 39) is also modeled using Analog
Behavioral Modeling (ABM). The model used in the following
examples assumes a linear response; however, the control
voltage equation can be modified as desired. The circuit is
modeled as a sine generator controlled by the control
voltage. The sine generator can be modeled using the
EVALUE function or the ABM function. In Figure 39, the
EVALUE function is used to generate the divided output and
the ABM function is used for the undivided output. Either the
GVALUE or the ABM/I function can be used for the control
voltage.
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Figure 35. Behavioral Model of the Phase Frequency Detector
HB1
V1
RSFF1
Delay
In
Ref
S
Out
Out
Rφ
P1
V2
R
Pulse Generator
If [V(Q1)>=1 & V(Q2)>=1, 5, 0]
Delay
Out
Freescale Semiconductor, Inc...
Delay
In
In
In
RSFF2
HB2
R
V2
Out
Vφ
P1
Out
S
V1
Pulse Generator
Figure 36. Behavioral Block Used for the
Pulse Generator
v1
v1
If (V(v1) ≥ 1 | V(v2) < 1, 5, 0)
Out
v2
v2
Figure 37. Behavioral Block Used as an RS Flip–flop
If [V(In1)>=1 & V(In2)<1 | V(In2)<1, 5]
If [V(In2)>=1, 0]
If [V(In3)>=1 & V(In2)<1, 5, 0]
S
R
In1
In2
Qout
In3
If [V(Q)>=1, 5, 0]
38
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Figure 38. Charge Pump Model
If [V(In1)>=1 j V(In2)<1, 1 x 10–3, 0]
In1
Rφ
In2
Vφ
0
PDout
idrive
If [V(In2)>=1 j V(In1)<1, 1 x 10–3, 0]
0
Freescale Semiconductor, Inc...
If [V(idrive) > 0, 0, 1]
If [V(idrive) < 5, 0, 1]
S1
+ +
– –
Sbreak
0
0
S2
+ +
– –
0
Sbreak
+ V1
5
–
0
Figure 39. VCO Behavioral Model
tw
fc
k1
6.283
250 x 106
525 x 106
VCOout
1
Parameters:
sin {tw [fc time + N v(int)]}
E1
Parameters:
N
Qc
In+
5000
1 x 10–6
In–
5V
1 x 103
Out+
Out
0V
Out–
evalue
sin ƪ tw
fc
time + v(int)ƫ
N
0
ctrl
ctrl
G1
+
In+
In–
gvalue
k1
tw N v(ctrl) Qc
IC = 0
int
C1
1 x 10–6
R1
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desired frequency. This frequency should be chosen to
represent the frequency present at the output of the N
counter of the PLL frequency synthesizer.
The second output represented by the ABM function is a
sine wave output of the frequency expected from the actual
VCO. The primary purpose of this output is to allow full
frequency simulation for spectrum analysis. By running a
transient analysis of sufficient time, it is possible to determine
spur content and level. If sufficient resolution is used in the
simulation, the PSpice probe FFT transform can be used to
provide the typical spectrum analyzer display.
The equation for the sine generator is:
f
e = sin ƪtw c time + v(int)ƫ .
N
fc is defined as the output frequency when the control voltage
is 0. This is the expected VCO frequency before frequency
division. For the purpose of simulation, the counter value, N,
has been written into the equation to ensure the correlation
between the modeled circuit and the mathematical loop filter
calculations. tw is 2π; additional decimal places can be added
as needed. v(int) is the control voltage effect and is defined in
these examples as:
Freescale Semiconductor, Inc...
v(int) =
Loop Filter Simulation
k1
v(cntl) 1 x 10–6 .
twN
The circuit shown in Figure 40 is used to simulate the
closed loop operation for a single charge pump output.
Component values for the loop filter should be computed
using information from the previous section. Initial conditions
can be set using the “IC1” symbol with starting values
specifying the initial condition.
By adjusting component values for the loop filter,
performance of the closed loop operation can be monitored.
The control voltage to the input of the VCO can be monitored
for a variety of conditions including settling time, lock time,
and ripple present at the VCO input. In addition, the output of
the VCO can be monitored for spur sidebands caused by
ripple on the loop filter output; however, expected operation
at high frequencies may be difficult due to the excessive data
that can be generated.
As the divider ratio, N, increases for a fixed step
frequency, the number of data points required to obtain
sufficient information to overcome aliasing problems may
become excessively large. In addition, the number of
samples required should be three or more per cycle. For
VCO frequencies in the range of 500 MHz, this means the
step ceiling needs to be in the range of 100 to 500 ps. If a
simulation time of 1 ms is needed, the actual computer time
can be several hours with data accumulation in the 1– to
2–Gbyte range.
where k1 is the VCO gain in rad/V.
The value C1 in the schematic of the VCO can be
arbitrarily changed; however, the value must match that of
Qc. Qc determines the value of the current to be integrated by
the capacitor C1. R1 is arbitrarily set to 1 x 1099 and is not an
active part of the circuit; however, it must be included to
prevent open pin errors from the PSpice software. The
GVALUE function is used to perform the generation of v(int).
There is some interaction between the integrator, (GVALUE
output and C1) and R1. V(int) is a continuous ramp that is
loaded by the resistance of R1. Unless the GVALUE output
current is sufficiently large for the value chosen for R1, the
VCO control voltage required to maintain lock will increase
throughout the simulation producing nonlinear operation.
Modifications to the circuit can be performed either by
changing the values in the parameter list or for major
changes to the VCO characteristics, the equations for the
sine generator, or control voltage can be altered.
The output of the sine generator is amplified by 1000 to
produce a sharp rise/fall time and the output limited to swing
between the values of 0 V and 5 V to convert it to a digital
output. The resultant circuit/symbol accepts a voltage input
from the loop filter and produces a square wave output at the
Figure 40. PLL Closed Loop Model
HB2
+
–
In
Rφ
Rφ
Ref
Vφ
Vφ
V1
0
40
HB1
+
+
IC = 3.5
ctrl
PDout
C3
2n
R1
7.5 k
75 k
0.2 n C1
C2
0
U3
IC = 3.5
R3
VCOout
Out
0.1 n
0
R4
1k
0
0
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Sz = amount the N counter is being increased (or
decreased) by,
St = number of fr cycles that CPH is active; this value
is either 16, 32, 64, or 128,
VCPHH = charge pump voltage – high,
VCPHL = charge pump voltage – low,
K1 = VCO gain (Hz/volt),
fc = VCO frequency at 0 V control voltage,
H = reference spur scaling factor.
7C. MAIN LOOP FILTER DESIGN — ADAPT
Freescale Semiconductor, Inc...
Introduction
For PSpice simulation, the schematic model shown in
Figure 41 was chosen. The classical PLL model employing a
phase–frequency detector, a VCO, and an adaptive loop filter
is used to simplify visualization of circuit operation. The
parameter tables allow for modification of circuit performance
by providing an easy method for altering critical values
without necessitating changes to sub–level schematics. The
definition for the terms are:
tw = 2π,
fr = reference frequency,
td = time delay; allows delay of the start of the high
current mode (used to perform reference spur
measurements),
CPL = charge pump low current,
CPH = charge pump high current,
N = N counter value,
Modeling the Phase–frequency Detector
Figure 42 is a schematic of the phase–frequency detector.
It includes the reference oscillator model, phase–frequency
detector model, and charge pump models. V1 is the control
element used to generate the step time for switching between
CPL and CPH. The signal source VPULSE, is used to
simulate the timer that controls when CPL and CPH are
turned on. PW calculates the pulse width that simulates the
counter from the values for St and fr that are entered in the
parameter tables on the top level schematic.
Figure 41. Top Level PLL Model
HB1
Parameters:
tw
fr
H
6.283185308
25 k
1
Parameters:
N
Sz
St
+
HB2
In
PDout–Lo
PDout–Hi
29320
400
32
f N – fc
IC = r
K1
60.4 k
C1
R1
IC =
K1
+
20 k
R3
Out
R10
C4
1k
50 p
0
C2
5
0
727.6 x 106
330 p
fr N – fc
IC =
K1
C5
+
Parameters:
C6
0
33 p
C3
10%
3300 p
0
Parameters:
td
VCO
ctrl
330 p
1 x 10–3
4 x 10–3
4 x 106
VCPHH
VCPHL
fc
+
R2
40.2 k
330 p
fr N – fc
Parameters:
CPL
CPH
K1
f N – fc
IC = r
K1
0
0
Figure 42. Phase–frequency Detector with Dual Charge Pumps
In
HB3
HB1
Ref
Shift
HB2
fin
Rφ
Rφ
PDout–Lo
PDout–Lo
Ref
Vφ
Vφ
PDout–Hi
Shift
PDout–Hi
Shift
St
PW =
4 fr
4 td
td =
fr
V1
+
–
0
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Reference Oscillator
The reference oscillator is shown in Figure 43. The
oscillator is modeled using an analog behavioral block. The
function for the block is written as an “If” condition. If the
signal shift is low, the reference frequency fr will be generated
if shift is high, a signal of four times fr will be generated. The
limiter/gain block converts the low level sine wave output of
the analog behavioral block into a square wave. The values
of 0 for the low value and 5 for the high value are used
throughout. These values are chosen out of habit and are not
critical in an analog behavioral environment, providing the
conformity is universal throughout the design.
Figure 43. Reference Oscillator
Freescale Semiconductor, Inc...
Shift
Shift
5V
Ref
1k
0V
If [V(shift) < 1, sin (tw fr time), sin (tw fr time) 4]
Phase–frequency Detector
The actual phase–frequency detector model minus
reference oscillator and charge pumps is shown in Figure 44.
The detector is composed of three delay modules: a
behavioral AND gate, and two RS flip–flops. The STP
function resets the phase/frequency detector logic on
initiation of the simulator. The circuit for the behavioral RS
flip–flop is shown in Figure 45.
The RS flip–flop equation illustrates the benefit of using
the behavioral block instead of using a primitive logic
element. A delay block and the behavioral gate equation
generate a pulse whose width is equal to the value of the
delay block. To generate the output using a primitive logic
element such as a NAND gate, an inverter would be
necessary to invert one of the NAND inputs. This approach
requires three elements to be used instead of the two of the
behavioral approach just for the pulse generator. In the
behavioral approach, the equation for the behavioral AND
gate is folded into the RS flip–flop, eliminating a separate
gate altogether. Constructing the model with classic logic
elements would require two NOR gates for the flip–flop, a
delay element, an inverter, and an AND gate; five elements
as compared with three for the behavioral approach. Since
the RS flip–flop is used in two places in the model, four less
components are needed for simulation. Since the speed of
the simulation is directly impacted by the number of
components being simulated, any reduction in the total
number of components is a savings in simulation time and
computer memory.
The RS flip–flops generate the lead or lag outputs that are
used to “steer” the VCO. The pulse generator equation
produces narrow pulses coincident with the leading edge of
each of the input signals. These pulses set the appropriate
RS flip–flop. Once set, the leading flip–flop must wait until the
lagging flip–flop is also set. The behavioral AND gate
provides the necessary output pulse to reset the flip–flops.
The delay element placed at the output of the behavioral
AND gate prevents an undefined state for the detector. The
value 5 ns is chosen to correspond with the data sheet. The
logic functions as a three state phase/frequency detector with
an operating range of ±2π. Rφ and Vφ deliver positive pulses,
whose width represents the amount of the lead of each input
over the other input.
Figure 44. Phase–frequency Detector Logic
HB1
Ref
In1
Q1
Qout
Rφ
In2
If [V(Q1)>=1 & V(Q2)>=1 | V(delay)>=1, 5, 0]
Delay
5 ns
HB2
In1
Q2
Qout
In
Vφ
In2
Delay
5 STP (5 ns – Time)
42
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Figure 45. Behavioral RS Flip–flop
If [V(v1)>=1 & V(v2)<1 & V(In2)<1, 5]
U1
V1
In1
Delay
1 ns
If [V(In2)>=1, 0]
V2
If [V(In3)>=1 & V(In2)<1, 5, 0]
In2
In2
Q
Qout
In3
If [V(Q)>=1, 5, 0]
Freescale Semiconductor, Inc...
Charge Pump Model
The schematic used for the charge pump in the
phase–frequency detector model is shown in Figure 46. Each
charge pump is made from two analog behavioral blocks.
The blocks chosen are three input behavioral blocks with
current outputs. The two blocks are connected in push–pull
to generate the appropriate source and sink output. The
output of each block is defined using an “If” statement to
monitor the input signals and generate the correct output at
the appropriate time.
One note about this type of design. SPICE does not limit
the output voltage swing necessary to generate the
programmed current. It is possible to implement values for
the loop filter, which will cause the charge pump to exceed
the rail voltage. To limit the output voltage to prevent
exceeding the value of the rails, the two behavioral blocks,
voltage–controlled switches S1 and S2, and constants
VCPHH and VCPHL are added. S1 and S2 on/off resistance
is set to 1 Ω and 1 x 1012 Ω , and the off/on voltage is set to
0 V and 1 V to correspond to the behavioral blocks. The
values defined by the constants are accessible from the
parameter tables on the top level schematic.
VCO Model
The model used for simulating the VCO is shown in
Figure 47. The VCO is composed of a sine wave generator
and a control element. An analog behavioral block is used as
a sine wave generator and a GVALUE element is used as a
control element. The GVALUE is operated as an integrator.
The output of the integrator is defined as
v(int) = k1 v(ctrl) Qc .
The block designated to provide the feedback to the
phase–frequency detector uses a single input analog
behavioral block. The signal shift generated by V1 in the
phase–frequency detector block is used to define the output
frequency of the behavioral block. In this manner, the
switching of the N and R values for the programmable
counters can be simulated. In the implementation shown, the
two frequencies will be either 25 kHz or 100 kHz when locked
to the reference oscillator.
The other behavioral block is used to generate a VCO
output dependent on the loop, but not contributing to the
operation of the loop. This is used to emulate the actual VCO
output with one modification. “H” has been added to the
equation generating the sine wave. If H is defined as 1, the
sine wave generated will be the same as the expected VCO
output. If H is chosen as some value greater than 1, the
frequency of the output will be reduced accordingly. This is
useful when running simulations designed to show reference
spur levels.
In cases where it is desirable to view reference spur levels,
simulation can become difficult or impossible. For example,
consider the circuit that is being discussed. This circuit
represents the evaluation kit (MC145230EVK) using a VCO
tunable between 733 MHz to 742 MHz, with a step frequency
of 25 kHz.
NOTE
This example is for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. Operation of the VCO at
frequencies greater than 550 MHz requires the
inclusion of additional external division such as a
prescaler.
To obtain useful information from the simulation, a
sampling rate greater than the Nyquist limit must be used
(three to five samples per cycle). This dictates a step size
less than 1/2 nanosecond. Additionally, the reference
frequency is only 25 kHz. To accurately represent the
conditions for spur generation, the simulation time must be
long enough to include a sufficient number of fr periods.
Otherwise, no spurs are generated. In addition, the data file
system is limited to 2 Gbyte, either in the NT 4.0 operating
system or in PSpice itself. If the file exceeds 2 Gbyte, the
data is discarded. To simulate reference spur generation at
730 MHz, a 1 ms simulation time was chosen. The simulation
ran for several hours and generated a data file just under
2 Gbyte. The result is shown in Figure 48. The plot obtained
from the EVK is shown in Figure 49 for comparison.
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Figure 46. CPL and CPH Charge Pumps
If [V(In1)>=1 & V(In2) <1 & V(shift) <1, CPL, 0]
Vφ
Rφ
Shift
In1
In2
0
Shift
PDout–Lo
0
If [V(In2)>=1 & V(In1) <1 & V(shift) <1, CPL, 0]
Freescale Semiconductor, Inc...
If [V(In1)>=1 & V(In2) <1 & V(shift) >= 1, CPH, 0]
0
drv
PDout–Hi
0
If (V(In2)>=1 & V(In1)<1 & V(shift) >= 1, CPH, 0)
If [V(idrv) > VCPHH, 1, 0]
S4
+ +
Sbreak
– –
0
VCPHH
If [V(drv) < VCJPHL, 1, 0]
S5
+ +
– –
0
VCPHL
44
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Figure 47. VCO Model
Parameters:
1 x 10–6
Qc
VCO
sin ƪ tw ǒ
fc time + v(int)
Ǔƫ
H
tw
If (V(turbo) <1, sin ƪ ǒ N + S Ǔ fc time + v(int)ƫ ,
z
4 tw
sin ƪ ǒ N + S Ǔ fc time + v(int)ƫ
z
Shift
5V
Turbo
Out
0V
Freescale Semiconductor, Inc...
1 x 106
ctrl
G1
ctrl
In+
+
int
In–
gvalue
C1
0
IC = 0
1 x 10–6
R1
1 x 1099
K1 v(ctrl) Qc
Figure 48. Reference Spur Simulation at 730 MHz
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Figure 49. Sybil EVK Reference Spur Measurements
Ref Lvl
10 dBm
– 73.32 dB
25.00000000 MHz
10
SWT
1
130 ms
Unit
dBm
–0
–10
–20
–30
1AVG
1SA
Freescale Semiconductor, Inc...
–40
–50
–60
1
–70
–80
–90
–100
–110
Center 737.5000009 MHz
It should be noted that the reference spur values obtained
from the simulation are lower than the values obtained from
the actual EVK. This is because the simulation model is an
“ideal” modeling of the PLL. To obtain results closer to the
actual implementation, the models should be “massaged” to
be more representative of the actual circuit. For example,
spur levels more consistent with actual circuitry can be
obtained by adding a resistance to ground at the input of the
VCO to represent leakage. The value chosen should be
consistent with VCO and circuit component performance.
To reduce simulation time, the H value may be used. By
reducing the frequency of the VCO output, the number of
samples required for simulation can also be reduced. The
output shown in Figure 50 shows the result of dividing the
VCO output of 730 MHz by 7.3 to produce a 100 MHz output.
The reference spurs are better represented since adequate
simulation time is possible.
To generate these outputs, the parameter values used
were those shown on the top level schematic. The simulator
was set to run a transient sweep, with td set for a delay that
would prevent the 4X frequency from being started. The initial
conditions were set to 1 V and the simulation run for 1 ms.
VCO was monitored and the probe display button FFT was
initiated. The X and Y axis were adjusted to those shown.
Note: These simulations are presented as the result of
“ideal” models and may not accurately display real hardware.
It would be best to load the VCO input with additional leakage
devices such as a large resistance, to accurately display real
46
6.4 kHz
Span 64 kHz
conditions. These models are starting points for more
accurate implementations.
Loop filter analysis is more accurate, since the
predominate factors are in the loop filter itself. To simulate the
performance of the loop filter, td is set for 0, N is set to the
desired divider value, and Sz is set to the desired step. For
this example, 733 MHz was chosen.
NOTE
These values are for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. For VCO frequencies greater than
550 MHz, an added external divider such as a
prescaler is necessary.
With the VCO model shown, V(ctrl) = 0 produces an output
of 727.6 MHz and at V(ctrl) = 1.35 V, the VCO frequency
would be 733 MHz; the minimum MC145230EVK default
operating frequency. To show the response of the loop filter to
a 10 MHz step at this operating frequency, Sz = 10 MHz /
25 kHz = 400. The simulation is run for 1 ms with a step
ceiling of 100 ns. The result is shown in Figure 51.
If the simulation is examined over a longer period of time,
the long term settling can be compared to the performance of
the actual circuitry. The plot shown in Figure 52 shows the
VCO control voltage with the display resolution set to 1 mV.
This compares to the plot of frequency variation
measurements made on the actual EVK. This plot is shown in
Figure 53.
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Figure 50. H Set to Generate a 100 MHz Output
Figure 51. 10 MHz Step for an Operating Frequency of 729 MHz
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Figure 52. VCO Settling
Figure 53. Frequency Settling of the EVK
VERTICAL
Freq C
tlk only
waiting for trigger
Center/
Span
742.003715MHz
Top/
Bottom
Center
741.999715MHZ
Span
8.000k HZ
741.999715MHz
1.000k HZ /div
741.995715MHz
0.00 s
T 742.2 µs
1
1.000 ms
200.0 µs/div
T 0.00s
2
2.0000 ms
Find Center
∆ –742.2 µs
Find Center
And Span
ref int
48
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performed on all, or selected components. By limiting the
circuit to minimum necessary components, simulation can be
performed using only the PSpice evaluation copy. In addition,
the optional PSpice program Optimizer should allow refining
the loop filter more easily.
While PSpice is a powerful tool, it is not without limits.
Since it was designed to run on large mainframe computers,
the PC is just now becoming powerful enough to make use of
the capability of the simulator. A fast Pentium class processor
with a large RAM and a hard drive of the Gbyte size is a
necessity. Even with the most judicious planning, some
simulations will “bump” the limits of the system.
Freescale Semiconductor, Inc...
It is noted that the results obtained from the simulation
compare favorably to those obtained from the measurements
of the EVK. The simulation display resolution is adjusted to
represent the same ± 4 kHz deviation as shown in Figure 53.
Since variation in VCO control voltage is equal to the VCO
frequency divided by the VCO gain, this axis may be
redefined to show change in frequency rather than change in
control voltage.
The models shown represent a “skeleton” that may be
used to develop extensive and reliable simulations that can
greatly reduce actual breadboarding and testing. In addition
to the basic simulations shown, PSpice provides a method by
which worst case and Monte Carlo evaluation can be
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7D. SECONDARY LOOP FILTER DESIGN
Low Pass Filter Design for PDouti
The design of low pass filtering for PDouti for the device
can be accomplished using the following design information.
In addition to the example included here, Motorola
Application Note AN1207, also includes examples of active
filtering which may be used to supplement this information.
PDout
VCO
R1
R2
C
Seidman, Arthur H., Integrated Circuits Applications
Handbook, Chapter 17, pp. 538–586. New York, John Wiley
& Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a
Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals,
Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola
Semiconductor Products, Inc., Reprinted with permission
from Electronic Design, 1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators,
Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola
Semiconductor Products, Inc., 1998.
Freescale Semiconductor, Inc...
Example:
KφKVCO
NC(R1 + R2)
ωn =
ζ = 0.5 ωn ǒR2C +
F(s) =
N
Ǔ
KφKVCO
R2sC + 1
(R1 + R2)sC + 1
Definitions:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = VDD / 4π V/radian for PDouti
Kφ (Phase Detector Gain) = VDD /2π V/radian for φV
and φR
2π∆fVCO
KVCO (VCO Gain) =
∆VVCO
For a nominal design starting point, the user might consider a
damping factor ζ ≈ 0.7 and a natural loop frequency ωn ≈
(2πfR / 50), where fR is the frequency at the phase detector
input. Larger ωn values result in faster loop lock times and, for
similar sideband filtering, higher fR–related VCO sidebands.
Recommended Reading:
The VCO is assumed to have a linear response
throughout the range used in this example. The gain for the
VCO has been given as 3.4 MHz/V and is multiplied by
2π rad/s/Hz for calculating loop filter values.
KVCO = 2π rad/s/Hz x 3.4 MHz/V = 2.136 x 107 rad/s/V .
The gain for the phase detector is defined as
Kφ =
VDD
V/rad for PDouti .
4π
Using a value for VDD (phase detector supply voltage) of
3.6 V with the output voltage multiplier turned off, the value is
Kφ =
3.6
= 0.2865 V/rad .
4π
Let
ωn =
2π fr
= 628.3 rad/s
50
and
N=
Gardner, Floyd M., Phaselock Techniques (second
edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory
and Design (second edition). New York, Wiley–Interscience,
1980.
Blanchard, Alain, Phase–Locked Loops: Application to
Coherent Receiver Design. New York, Wiley–Interscience,
1976.
Egan, William F., Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers
Theory and Design. Englewood Cliffs, NJ, Prentice–Hall,
1983.
Berlin, Howard M., Design of Phase–Locked Loop
Circuits, with Experiments. Indianapolis, Howard W. Sams
and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue
Ridge Summit, PA, Tab Books, 1980.
50
Given the following information:
VCO frequency = 45.555 MHz,
Frequency step size = 5 kHz,
VCO gain = 3.4 MHz/V.
Design a loop filter with a damping factor of 0.707.
FVCO
45.555 MHz
= 9111 .
=
Fstep size
5 kHz
Choosing C = 0.05 µF and calculating R1 + R2,
R1 + R2 =
Kφ KVCO
N C ωn2
= 34 kΩ .
With a damping factor of 0.707,
0.707
R2 =
0.5 ωn
N
–
Kφ KVCO
C
= 15 kΩ ,
R1 = (R2 + R1) – R2 = 34 k – 15 k = 19 kΩ
20 kΩ
.
The choice for C is somewhat arbitrary, however, its value
does impact the performance of the loop filter. If possible, a
range of choices for C should be used to calculate potential
loop filters and the resultant filters simulated, as will be
shown below, to determine the best balance.
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If additional filtering is desired, R1 may be split into two
equal resistors and a capacitor to ground inserted. Since the
closest resistance to one–half of 9 k is 4.7 kΩ , this value is
chosen for R1a and R1b. The maximum value for the added
capacitance is based on the bandwidth of the original loop
filter.
The general form for the transfer function for the passive
filter shown in Figure 54, can be shown to have the form:
F(s) = Kh ƪ
s + ω2
junction of R1a and R1b. Using the values defined above, Cc
is determined to be
Cc =
1
ƪ
R1a R1b + R1a R2
(R1 + R2) ω3
ƫω
1
=
3
= 10.83 nfd
R1a R1b + R1a R2
ƫω .
B
10 nfd
ƫ
ƪ
,
Figure 54. Passive Loop Filter for PDouti
(s + ω1) (s + ω3)
(R1 + R2) 10
where
ω1 =
1
(R1a + R1b + R2) C
Freescale Semiconductor, Inc...
ω2 =
ω3 =
+
1
,
R1a
R2C
V1
1
R1 R1b + R1a R2
ƪ a
ƫ C
c
(R1 + R2)
10 k
V
10 k
Cc
,
IC = 0
R1b
10 n
R2
15 k
0
where
0
C
50 n
R1 = R1a + R1b
0
and
ω3 > ω2 .
Since splitting R1 into two equal values, R1a and R1b, and
inserting the capacitance between the junction of R1a and
R1b does not change the position of the pole located at ω1,
the value of ω1 remains
1
1
ω1 =
=
.
(R1a + R1b + R2) C
(R1 + R2) C
The 0 identified at ω2 = 1/R2 C is also unaffected by the
addition of Cc if ω3 > ω2.
Since
R1a = R1b =
R1
2
.
the value of Cc can be determined by specifying the value for
ω3 and using the values already determined for R1 and R2.
The rule of thumb is to choose ω3 to be 10 x ωB so as not to
impact the original filter. ωB can be found as
ωB = ωn
[1 + 2ζ2 +
ωB = 628.3 rad/s
+
(2 + 4ζ2 + 4ζ4)]
[1 + 2 (0.707)2
(2+ 4 (0.707)2 + 4 (0.707)4)]
= 1.293 x 103 rad/s .
10 ωB = 12.93 x 103 rad/s .
The circuit for the passive loop filter is shown in Figure 54.
R1 is split into two equal values and Cc inserted at the
Open Loop AC Analysis of the Loop Filter
AC analysis is chosen for the mode of simulation for
PSpice and VSIN is chosen for V1 and is set to produce a 1 V
peak output signal. The simulation is then run and the result
shown in Figure 55.
A Bode plot of the loop filter is obtained which describes
the open loop characteristics of the loop filter. The corner
frequencies of the filter can be modified and the simulation
rerun until the desired wave shape is obtained. Since AC
analysis runs much faster than transient analysis, the AC
open loop analysis of the loop filter is much quicker and
requires less resources than the closed loop transient
analysis.
Closed Loop Filter Simulations Using PSpice
The top level schematic for simulating a simple loop filter
for PDouti operating closed loop, is shown in Figure 56. This
filter uses the values calculated above.
The schematic represents the PLL function using the
internal phase detector, PDouti, the loop filter calculated
above, and a VCO. The parameter table allows altering the
divider value of N, the maximum current obtained from
PDouti, and PDout charge pump voltage from the top level
schematic.
The schematic for the VCO is shown in Figure 57. Analog
behavioral modeling is used rather than discrete transistor
modeling to reduce component count and improve simulation
efficiency.
The behavioral VCO is composed of an integrator that
transforms the input ctrl into the voltage control V(int) and a
sine wave generator function whose frequency is controlled
by V(int). EVALUE and GVALUE functions are used to
perform the transforms. The analog behavioral models, ABM
and ABMI, can also be used.
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Figure 55. Bode Plot of the Passive Loop Filter
Figure 56. Passive Loop Filter
+
HB2
Parameters:
CP
N
0.3 mA
9111
Parameters:
VCPH
VCPL
Ref
+
–
V2
In
3.6
0
HB1
V
IC = 0
R1
R6
10 k
10 k
Ctrl
PDout
C4
Out
10 nf
0
R2
15 k
+
IC = 0
0
C2
50 nf
0
52
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Figure 57. VCO Behavioral Model
E1
Parameters:
tw
fc
K1
6.283
38.756 x 106
21.36283005 x 106
Out+
In–
Out–
1 x 106
Out
0V
evalue
fc
sin ƪ tw ǒ Ǔ time + v(int) ƫ
N
Parameters:
Qc
5V
In+
1 x 10–6
0
ctrl
ctrl
G1
+
In+
IC = 0
int
Freescale Semiconductor, Inc...
In–
gvalue
k1
ǒ
Ǔ v(ctrl) Qc
tw N
G1 performs the operation [k1/(tw N)] v(ctrl) Qc. This
integrates the input ctrl to produce a voltage ramp used by E1
to produce the desired output. This input is integrated by C1
whose value should equal Qc for most applications. R1 is
required by SPICE to prevent a floating node error.
E1 performs the calculations necessary to generate a sine
wave of the desired frequency based on the values listed in
the parameter tables and the value of ctrl. The output of E1 is
multiplied by 1 x 106 and limited to 0 and 5 to obtain a square
wave with a fast rise/fall time. Since I/O_STM is a standard
model whose values are 0 and 5, these are used here and in
the phase detector rather than modifying the component
libraries.
The parameter tables provide a convenient method for
setting VCO parameters. tw is 2π, fc is the zero control
voltage VCO frequency, and K1 is the VCO gain in rad/s/V.
The sub–schematic for the phase/frequency detector
section of the drawing is shown in Figure 58. This is
composed of two blocks, HB3 and HB4. HB3 performs the
PDouti function with HB4 performing the actual phase
detector operation.
The circuit for the phase/frequency detector is shown in
Figure 59. The model is made up of two pulse generators,
two RS flip–flops, and appropriate behavioral gates.
HB1 and HB2 are RS flip–flops. These are constructed
from behavioral blocks as shown in Figure 60. A behavioral
AND gate with a 5 ns delay completes the three state (± 2π)
phase/frequency detector. The STP function ensures the RS
flip–flops are reset at initiation.
To perform the phase detector function, the Ref and fin
inputs of the behavioral RS flip–flops are configured to
simulate edge triggered operation. This is achieved by
placing a 1 ns delay in the Ref and fin signal paths. The input
and output of the delay are compared by the input behavioral
block and interpreted as a 1 ns pulse. These pulses are used
to set HB1 and HB2. If fin leads Ref, the In flip–flop, HB2, will
be set first. When Ref leads fin, the Ref flip–flop, HB1, will be
set first. The lagging edge drives the second flip–flop output
high and the behavioral AND gate then resets both flip–flops.
The delay line at the output of the behavioral AND gate
prevents PSpice from being confused and also completes
the simulation of the phase detector. The outputs of the two
RS flip=flops are labeled Rφ and Vφ. The time between the
C1
1 x 10–6
R1
1 x 1099
leading and lagging edges is reflected in the pulse width of
the leading edge flip–flop. The lagging edge flip–flop will
display a narrow pulse equal in width to the value chosen for
the delay at the output of the behavioral AND gate. This
should be programmed to the minimum value as specified by
the data sheet and is usually 5 ns or less.
Since the outputs Rφ and Vφ are pure logic signals,
additional circuitry is necessary to produce the output PDouti.
This output should be high impedance when not driving, and
pull either high or low depending on which function (Rφ or Vφ)
is active. The circuitry shown in Figure 61 performs this
function.
To eliminate the need for discrete modeling of PDouti,
analog behavioral modeling is used. Analog behavioral
blocks ABMI/2, generate a current source/sink output
whenever the appropriate input is high.
A second set of behavioral blocks monitor the output
idrive, and switch on the appropriate voltage controlled
switch whenever the output rises to the value of VDD (phase
detector supply voltage) or drops to 0.
To model PDouti, either a model of the transistors used for
PDouti must be used or this behavioral arrangement can be
used. Since the output is specified by a specific output level
and current capability, this arrangement suffices. The output
swing becomes VCPH in the schematic and the current
capability is CP. If a non–zero value is desired for Vlo, the
value VCPL is adjusted from the parameter table on the top
level schematic.
This arrangement allows setting the output voltage swing
of PDouti by specifying VCPH, the current drive of PDouti by
specifying the desired value for CP, and leakage values can
be simulated by setting the appropriate attributes for S1 and
S4 or by adding additional resistance.
Simulation
Figures 62 and 63 are the simulation results of running a
transient analysis on the example shown above. The time to
lock from power on is simulated by setting the initial condition
(IC1) to 0 and running the simulation. Figure 62 is the time
versus value of the VCO control voltage. Figure 63 shows the
output at the input of the loop filter and can be used to
determine lock time.
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Figure 58. Phase/Frequency Detector
HB4
HB3
In
fin
Rφ
Rφ
Ref
Ref
Vφ
Vφ
PDout′
PDout
Figure 59. Phase Detector Logic
HB1
Ref
In1
Q1
Vφ
Freescale Semiconductor, Inc...
Qout
In2
If [V(Q1)>=1 & V(Q2)>=1 | V(delay)>=1, 5, 0]
U10
Delay
5 ns
HB2
In1
Q2
Rφ
Qout
In
In2
5 STP (5 ns – Time)
Figure 60. Behavioral RS Flip–flop
If [V(v1)>=1 & V(v2)<1 & V(In2)<1, 5]
U5
In1
In2
V1
Delay
1 ns
If [V(In2)>=1, 0]
V2
If [V(In3)>=1 & V(In2)<1, 5, 0]
In2
Q
Qout
In3
If [V(Q)>=1, 5, 0]
54
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Figure 61. Rφ / Vφ to PDouti Conversion
If (V(In1)>=1 & V(In2)<1, CP, 0)
Rφ
In1
Vφ
In2
0
idrive
PDout
If (V(In2)>=1 & V(In1)<1, CP, 0)
0
Freescale Semiconductor, Inc...
If (V(idrive)> 0, 0, 1)
S1
+ +
– –
Sbreak
0
VCPL
If (V(idrive)< 5, 0, 1)
S4
+ +
– –
Sbreak
0
VCPH
Figure 62. VCO Control Voltage versus Time
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Figure 63. PDouti at Input to Loop Filter
Summary
PSpice provides a method by which the performance of
PLL circuitry can be simulated prior to, or in addition to,
laboratory testing. The use of behavioral modeling allows the
creation of simulation circuits that can provide valuable
information for loop filter design and adjustment. By judicious
56
attention to VCO modeling, expected output characteristics
can be verified prior to laboratory testing. While simulation
does not replace laboratory testing, it can be used to find
solutions to “what if” questions without the need for extensive
empirical data gathering.
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There are three important criteria to note, highlighted in
the following sections: Allowing for Voltage Build,
Ensuring Valid Counter Programming, and Allowing for
Overshoot. Violation of any of these may cause the voltage
multiplier to collapse. Once the voltage collapses, the loop
goes out of lock and can not recover until the voltage is
allowed to build up again. For an active loop, the voltage
multiplier is designed to maintain the multiplied voltage on the
phase/frequency detector supply pin (Cmult). If the main loop
is active, the multiplier cannot build the voltage.
Freescale Semiconductor, Inc...
Allowing for Voltage Build
After power up, a sufficient time interval must be provided
for the on–chip voltage multiplier to build up the voltage on
the Cmult pin. During this interval, the phase/frequency
detector outputs for the main loop (PDout–Hi and PDout–Lo)
must be inactive (floating outputs). The POR (power–on
reset) circuit forces this “float” condition, thus allowing the
voltage to build on the Cmult pin.
The duration of the interval to build the voltage is
determined by the external capacitor size tied to the Cmult pin
and the charging current which is 100 µA minimum. The
following formula may be used:
T = CV / I
where
T is the interval in seconds,
C is the Cmult capacitor size in farads,
V is the desired voltage on Cmult in volts, and
I is the charging current, 1 x 10–4 amps.
The desired voltage on Cmult is 4 V for a nominal 2 V
supply and 5 V for any supply above 2.6 V.
After this interval, the chip can maintain the voltage on the
Cmult pin and the phase detectors may be safely placed in the
active state.
The interval above also applies when the voltage multiplier
is turned off (with power applied) via bits Ri19 Ri18 Ri17
being 0 0 0. After the multiplier is turned back on, sufficient
time must be allowed for the voltage to build on Cmult. In this
case, typically an external resistor does not allow the Cmult
voltage to discharge below approximately Vpos (see Section
5E, under Cmult). Note that if the voltage multiplier is NOT
turned off (that is, the above bits are unequal to 0 0 0), the
keep–alive circuit maintains the multiplied voltage on Cmult.
Ensuring Valid Counter Programming
Before the PLLs and/or phase detectors are taken out of
standby, legitimate divide ratios (pertinent to the application)
must be loaded in the registers. For example, proper divide
ratios must be loaded for the R, N, Ri, and Ni counters. Also,
proper values for all other bits must be loaded. For example:
selection of crystal or external reference mode must be made
prior to activation of the loops.
After the IC is initialized with the proper bits loaded, the
main loop may then be safely activated via the phase
detector float bit and/or the PLL standby bit being
programmed to 0.
Allowing for Overshoot
The VCO control voltage overshoot for the main loop must
not be allowed to exceed the capability of the phase/
frequency detectors’ maximum output voltage. The
detectors’ maximum output voltage is determined by the
minimum voltage at Cmult and the headroom required for the
current source. See the following figure.
Voltage at Cmult Pin
Headroom for Current Source
Overshoot
VCO Control Voltage
7E. VOLTAGE MULTIPLIER STALL AVOIDANCE
Steady–state Control Voltage
Time
For example, if the main supply voltage (Vpos) is 3 V and
the voltage multiplier is utilized, the minimum voltage at Cmult
is 4.75 V. Then, to allow for current source headroom, the
maximum output voltage from the parameter table in Section
3C is approximately Cmult – 0.6 V or 4.2 V approximately.
Thus, the maximum output overshoot voltage at the
phase/frequency detector outputs should be no more than
4.2 V.
Continuing the above example, if the loop is designed with
20% overshoot in the VCO control voltage, then the
overshoot must be subtracted off of the 4.2 V shown above.
Therefore, the upper end of the control voltage to the VCO
must be no more than approximately 3.64 V.
The equations below can be used to determine
constraints:
∆V ≤
Vφ – 1.2
2α + 1
SSVmax = Vφ – α (∆V) – 0.6
where
∆V is the VCO control voltage range, the maximum minus
the minimum voltage,
Vφ is the minimum phase detector supply voltage (at the
Cmult pin) per the following table,
α is the control voltage overshoot in decimal; for example,
20% overshoot is 0.2, and
SSVmax is the maximum allowed steady–state VCO
control voltage.
MINIMUM PHASE DETECTOR VOLTAGE
FROM VOLTAGE MULTIPLIER
Supply Voltage,
Vpos
Minimum Phase Detector
Voltage, Vφ
1.8 V
3.32 V
2.0 V
3.72 V
2.5 V
4.75 V
3.6 V
4.75 V
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8. PROGRAMMER’S GUIDE
8A. QUICK REFERENCE
BitGrabber ACCESS OF THE REGISTERS
Freescale Semiconductor, Inc...
Enb
Din
MSB
Clk
1
LSB
2
3
4
8 Clocks to Access the C Register
16 Clocks to Access the Hr Register
24 Clocks to Access the N Register
CONVENTIONAL ACCESS OF THE REGISTERS
Enb
Din
Clk
x
x
1
x
2
x
3
A3
4
A2
5
Address
A1
6
A0
7
LSB
8
9
10
11
12
32
32 Clocks Always Used
$0 Accesses C Register
$1 Accesses Hr Register
$2 Accesses N Register
$3 Accesses D Register
$4 Accesses Hn′ Register
$5 Accesses R′ Register
= when the PLL device loads the data bit.
58
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MC145181
8A. QUICK REFERENCE (continued)
C REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
x
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3
A2 A1 A0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C7
0
C6 C5 C4
C3
See Below
C2 C1 C0
See Below
Freescale Semiconductor, Inc...
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
C7
C6 C5 C4
C3
C2 C1 C0
Out A
Out C
PDi
Float
PLL
Stby
Osc
PLLi
Stby
Stby
Out B/Xref
PD
Float
PD′ Float = Phase Detector′ Float
0 = Active, normal operation (power up default)
1 = PDout′ is forced to high impedance
Out A = Output A Pin Logic State
0 = Pin is forced to 0 (power up default)
1 = Pin is forced to 1
See Note 1
Osc Stby = Oscillator Standby
0 = Active, normal operation (power up default)
1 = Oscillator/reference circuit in standby
See Note 2
Out B/XRef = Output B Pin Logic State/
External Reference Selection
See table below
Out C = Output C Pin Logic State
0 = Pin is forced to 0 (power up default)
1 = Pin is forced to high impedance
PD Float = Phase Detector Float
0 = Active, normal operation (power up default)
1 = PDout–Hi/PDout–Lo are forced to high impedance
PLL Stby = PLL Standby
0 = Active, normal operation
1 = Main PLL in standby (power up default)
See table below
PLL′ Stby = PLL′ Standby
0 = Active, normal operation
1 = Secondary PLL in standby (power up default)
NOTES: 1. For the Out A bit to control the Output A pin as a port expander, bits R′21 R′20 must be 0 0, which selects Output A as a
general–purpose output. If R′21 R′20 are not equal to 0 0, then the Out A bit is a don’t care.
2. Whenever Osc Stby = 1, both PLL Stby and PLL′ Stby must be 1, also.
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Mode Pin and Bit Summary
Mode Pin
Out B/XRef Bit
PLL Stby Bit
Reference Circuit
Output B Pin
Main PLL
0
0
0
Xtal Osc mode
0
Active
0
0
1
Xtal Osc mode
Z
Standby
0
1
0
Xtal Osc mode
1
Active
0
1
1
Xtal Osc mode
Z
Standby
1
0
0
Xtal Osc mode
0
Active
1
0
1
Xtal Osc mode
Z
Standby
1
1
0
External Reference mode
1
Active
1
1
1
External Reference mode
Z
Standby
NOTES: Xtal osc = crystal oscillator. Z = high impedance.
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8A. QUICK REFERENCE (continued)
Hr REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
Freescale Semiconductor, Inc...
x
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3
A2 A1 A0
0
0
0
x
x
x
x
x
x
x
1
x
R15
...
R12
R11
...
R8
R7
...
MSB of R Counter
Divide Value
R4
R3
...
R0
LSB of R Counter
Divide Value
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
R15
...
MSB of R Counter
Divide Value
R12
Least Significant
Nibble
(Shifted in Last)
R11
...
R8
R7
...
R4
R3
...
R0
LSB of R Counter
Divide Value
EXAMPLE: To program the R counter to divide by 1000 in decimal, first multiply 1000 by 2 which is 2000. Convert 2000 to
hexadecimal: $7D0. Then, add leading 0s to form 2 bytes (4 nibbles): $07D0. Finally, load the Hr register bits R15
to R0 with $07D0. When the N register is subsequently loaded, data passes from the first Hr register (buffer) to the
second R register (buffer). (Data is still retained in the Hr register.)
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
NOTE:
60
Hexadecimal numbers are preceded with a dollar sign. For example: hexadecimal 1234 is shown as $1234.
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8A.
QUICK REFERENCE (continued)
N REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
x
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3
A2 A1 A0
0
0
1
N23
...
N19
N20
...
N16
N15
...
0
N12
N11
...
N8
N7
...
N4
N3
...
N0
See Below
Freescale Semiconductor, Inc...
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
N23 N22 N21 N20
N15
...
N12
N11
...
N8
N7
...
Current
Ratio
LD
Window
Control
N19 N18 N17 N16
Phase Detector
Program
N4
N3
...
N0
LSB of N Counter
Divide Value
MSB of N Counter
Divide Value
Control = Control for Auxiliary Divider
See Table A
Phase Detector Program = Detector Program for Main Loop
See Table B
LD Window = Lock Detector Window for Main Loop
0 = 32 Osce periods
1 = 128 Osce periods
Current Ratio = PDout–Hi to PDout–Lo Current Ratio
0 = 4:1
1 = 8:1
EXAMPLE: To program the N counter to divide by 1000 in decimal, first convert to hexadecimal: $3E8. Then, add leading 0s to form
2 leading bits plus 2 bytes (2 bits plus 4 nibbles); this is N17 to N0. Bits N23 to N18 should be appropriate to control the
above functions. Finally, load the N register. Loading the N register also causes data to pass from the Hr register to the
R register and data from the Hn′ register to pass to the N′ register.
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
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Table A. Osce to fout Frequency Ratio,
Mode = Low
N23
Ri 1
Ri 0
Osce to fout
Frequency Ratio
0
0
0
10:1
0
0
1
12.5:1
0
1
0
12.5:1
0
1
1
12.5:1
1
0
0
8:1
1
0
1
10:1
1
1
0
10:1
1
1
1
10:1
NOTE: When the Mode pin is high, the fout pins are configured
as polarity inputs and N23 must be programmed to 1.
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Table B. Main Phase Detector Control
N21
N20
N19
Result
0
0
0
Both PDout–Hi and PDout–Lo floating
0
0
1
PDout–Hi floating, PDout–Lo enabled
0
1
0
PDout–Hi enabled, PDout–Lo floating
0
1
1
Both PDout–Hi and PDout–Lo enabled
1
0
0
PDout–Hi enabled and PDout–Lo floating
for 16 fR cycles, then PDout–Hi floating
and PDout–Lo enabled
1
0
1
PDout–Hi enabled and PDout–Lo floating
for 32 fR cycles, then PDout–Hi floating
and PDout–Lo enabled
1
1
0
PDout–Hi enabled and PDout–Lo floating
for 64 fR cycles, then PDout–Hi floating
and PDout–Lo enabled
1
1
1
PDout–Hi enabled and PDout–Lo floating
for 128 fR cycles, then PDout–Hi floating
and PDout–Lo enabled
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8A.
QUICK REFERENCE (continued)
R′ REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
x
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3
A2 A1 A0
0
1
0
1
R′23 R′22 R′21 R′20
Y
Coefficient
V–Mult
Control
Output A
Function
Freescale Semiconductor, Inc...
R′19 R′18 R′17 R′16
Y Coefficient
0 0 = only programming values allowed
Output A Function = Controls Output A Mux
0 0 = General–Purpose Output
0 1 = fR
1 0 = fR′
1 1 = Phase Detector pulse
Test/Rst
R′15
...
R′12
R′11
...
R′8
R′7
...
R′4
MSB of R′
Counter Divide
Value
R′3
...
R′0
LSB of R′ Counter
Divide Value
V–Mult Control = Voltage Multiplier Control
0 0 0 = Multiplier OFF, 9 MHz ≤ Osce ≤ 80 MHz
0 0 1 = Multiplier ON, 9 MHz ≤ Osce ≤ 20 MHz
0 1 0 = Multiplier ON, 20 MHz < Osce ≤ 40 MHz
0 1 1 = Multiplier ON, 40 MHz < Osce ≤ 80 MHz
Test/Rst = Test/Reset
0 = only programming value allowed
EXAMPLE: When the Mode pin is tied low, see Table 21 for R′ counter programming. When the Mode pin is tied high, to program the
R′ counter to divide by 1000 in decimal, first multiply 1000 by 2, which is 2000. Convert 2000 to hexadecimal: $7D0. Then,
add leading 0s to form 2 bytes (4 nibbles); this becomes bits R′15 to R′0. Bits R′23 to R′16 should be appropriate to control
the above functions. Finally, load the R′ register.
With a conventional load, address bits A3 to A0 must be included.
NOTE:
62
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MC145181
8A.
QUICK REFERENCE (continued)
Hn′ REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
Freescale Semiconductor, Inc...
x
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3
A2 A1 A0
0
1
0
0
x
x
x
x
x
x
x
x
N′15
...
N′12
N′11
...
MSB of N′ Counter
Divide Value
N′8
N′7
...
N′4
N′3
...
N′0
LSB of N′ Counter
Divide Value
EXAMPLE: To program the N′ counter to divide by 1000 in decimal, first multiply 1000 by 8, which is 8000. Convert 8000 to
hexadecimal: $1F40. Then, add leading 0s (if necessary) to form 2 bytes (4 nibbles). Finally, configure address bits A3
to A0 and load the Hn′ register. When the N register is subsequently loaded, data passes from the first Hn′ register (buffer)
to the second N′ register (buffer). (Data is still retained in the Hn′ register.)
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8A.
QUICK REFERENCE (continued)
D REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
x
x
x
Least
Significant Nibble
(Shifted in Last)
Address Nibble
x
A3
A2 A1 A0
0
0
1
x
x
x
x
x
x
x
x
D15
...
D12
D11
MSB of
DAC2
1
64
Freescale Semiconductor, Inc...
D8
LSB of
DAC2
DAC2 Value
DAC2 Value = Analog Output Level of DAC2
$00 = zero output
$01 = zero + 1 LSB output
$02 = zero + 2 LSBs output
$03 = zero + 3 LSBs output
•
•
•
$FD = full scale – 2 LSBs output
$FE = full scale – 1 LSB output
$FF = full scale output
...
D7
...
D4
D3
MSB of
DAC1
...
D0
LSB of
DAC1
DAC1 Value
DAC1 Value = Analog Output Level of DAC1
$00 = zero output
$01 = zero + 1 LSB output
$02 = zero + 2 LSBs output
$03 = zero + 3 LSBs output
•
•
•
$FD = full scale – 2 LSBs output
$FE = full scale – 1 LSB output
$FF = full scale output
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8B. INITIALIZING THE DEVICE
Freescale Semiconductor, Inc...
Introduction
The registers retain data as long as power is applied to the
device. The R and N registers contain counter divide ratios
for the main loop, PLL. The Ri and Ni registers contain
counter divide ratios for the secondary loop, PLLi. Additional
control bits are located in the Ri, N, and C registers. The D
register controls the DACs. Section 8A is a handy reference
for register access and bit definitions.
The C, D, Ri, and N registers can be directly written, and
have an immediate impact on chip operation. The Hr and Hni
registers can be directly written, but have no immediate
impact on chip operation. This is because the Hr and Hni
registers are the front–ends of double buffers. The Hr register
feeds the R register. The Hni register feeds the Ni register.
Changing data in the R and/or Ni registers is done with a
write to the Hr and/or Hni register, respectively, followed by a
write to the N register. The transfer of data from the Hr to R
and Hni to Ni registers is triggered with a write to the N
register.
Typically, the Hr and Hni registers are written once, during
initialization after power up. The Hr and Hni registers only
need to be accessed if their data is changing.
and an external reference is accommodated (Out B/Xref bit
C6 = 1, with the Mode pin high). When the voltage multiplier
is enabled by programming the Ri register, the voltage is
allowed to build on the Cmult pin such that a voltage higher
than the main supply voltage is providing power to the
phase/frequency detectors. Both loops are active (PLL Stby
bits C1 = C0 = 0). Also, for this example, Output A and Output
C are programmed low (Out bits C7 = C5 = 0).
In summary, hexadecimal 58 or $58 is serially transferred
(BitGrabber access with no address bits).
Step 2: Load the Ri Register
For the secondary loop, the 19.44 MHz reference must be
divided down to 80 kHz by the Ri counter; the divide ratio is
243. Per Section 8A, the value is doubled to 486. The 16
LSBs of the Ri register determine the Ri counter divide ratio.
Therefore, 486 is converted to $01E6 and becomes the 16
LSBs (Ri15 to Ri0) in the Ri register. Test/Rst bit Ri16 must
be a 0. Bits Ri19 to Ri17 determine the refresh rate of the
voltage multiplier. The frequency at Osce is < 20 MHz.
Therefore, per Section 8A, bits Ri19 to Ri17 must be 0 0 1. If
Output A is needed as a MCU port expander, bits Ri21 =
Ri20 = 0. Per Section 8A, Y Coefficient bits Ri23 = Ri22 = 0.
In summary, $050201E6 is serially transferred
(conventional access with an address of 0 1 0 1).
An Example
Following is an initialization example for a system with a
main loop that covers 450 to 500 MHz in 5 kHz steps. An
external reference of 19.44 MHz is utilized. The secondary
loop is selected to run at 50 MHz. Both VCOs are positive
polarity meaning that when the input control voltage
increases, the output frequency increases. A divided–down
reference is not needed (fout and fout). Therefore, the Mode
pin is tied to Vpos and the Pol and Poli pins are tied to ground.
The following initialization gives serial data examples for
BitGrabber access of the C, Hr, and N registers.
Step 3: Load the Hr Register
For the main loop, the 19.44 MHz reference must be
divided down to 5 kHz by the R counter; the divide ratio is
3888. Per Section 8A, the ratio 3888 is doubled to 7776 and
then converted to $1E60. The Hr register value is
programmed as $1E60. When the Hr register contents are
transferred to the R register, the R counter divide ratio is
determined.
In summary, $1E60 is serially transferred (BitGrabber
access). This value is transferred from the Hr to the R
register when the N register is accessed in Step 5.
Initialization
Below is the six–step initialization sequence used after
power up for the example given above.
Programming the C register first is recommended if the
voltage multiplier is utilized. There are three important criteria
to note. Violation of any criterion may cause the voltage
multiplier to collapse. The first criterion is that after power up,
a sufficient time interval must be provided (after the C and Ri
registers are initialized) for the on–chip voltage multiplier to
build up the voltage on the Cmult pin. This interval is
determined by the external capacitor size tied to the Cmult pin
and the charging current which is about 100 µA. After this
interval, the chip can maintain the voltage on the Cmult pin
and the phase/frequency detectors for the main loop may be
safely activated. The second criterion is that before the
phase/frequency detectors are activated, legitimate divide
ratios (pertinent to the application) must be loaded in the
registers. The third criterion is a hardware issue. The three
criteria are discussed with more detail in Section 7E.
If the voltage multiplier is not used, Step 1 is eliminated
and the initialization sequence starts with Step 2.
Step 1: Load the C Register
The C register is programmed such that the main loop’s
phase/frequency detector outputs are floating (PD Float bit
C4 = 1), the reference circuit is active (Osc Stby bit C2 = 0),
Step 4: Load the Hni Register
For the secondary loop, the phase detector is chosen to
run at 80 kHz. Therefore, 80 kHz must be multiplied up to
50 MHz which is a factor of 625. Per Section 8A, the factor is
first multiplied by 8 which equals 5000 and then converted to
$1388. The Hni register is programmed as $1388. When the
Hni register contents are transferred to the Ni register, the Ni
counter divide ratio is determined.
In summary, $04001388 is serially transferred
(conventional access with an address of 0 1 0 0). The value
$1388 is transferred to the Ni register when the N register is
accessed in Step 5.
Step 5: Load the N Register
For this example, the IC is initialized to tune the lowest end
of the main loop. The lowest end of the main loop’s frequency
range is 450 MHz. Therefore, the 5 kHz must be multiplied up
to 450 MHz which is a factor of 90,000 or $15F90 to be
loaded into bits N17 to N0 of the N register. Bit N18 is
programmed to 0 for a PDout–Hi to PDout–Lo current ratio of
4:1. If PDout–Lo is used for the main loop, bits N21 to N19
must be 0 0 1. (PDout–Lo must be used to initialize the device
when adapt is used, see Section 8D.) Bit N22 = 0 to select a
lock detect window of approximately 32 / Osc e =
32 / 19.44 MHz or 1.6 µs. Bit N23 must be programmed to 1
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by the user. (When the Mode pin is high, programming N23 to
a 0 is for Motorola use only.)
In summary, $895F90 is serially transferred (BitGrabber
access). The N register access also causes double–buffer
transfers of Hr to R and Hni to Ni.
Freescale Semiconductor, Inc...
Step 6: Load the C Register
Now that legitimate divide ratios are programmed for the
counters, the main loop may be activated. Thus, the PD float
bit C4 is now programmed to 0. The standby bits are
unchanged: C2 = C1 = C0 = 0. Bit C5 could be used to control
Output C to either a low level or high impedance; for a low
level, C5 = 0. Whenever an external reference is utilized, bit
C6 must be 1. Bit C7 may be used to control Output A to a low
or high level because it is selected as “port expander” by bit
Ri21 and Ri20; for a low level, C7 = 0.
In summary, $40 is serially transferred (BitGrabber
access). This causes the main loop to tune to 450 MHz, the
secondary loop to tune to 50 MHz, and both the Output A and
Output C pins to be forced low.
The device is now initialized.
8D. PROGRAMMING UTILIZING HORSESHOE WITH
ADAPT
Introduction
A unique adapt feature can be used with the MC145181
when conventional tuning can not meet the lock–time
requirements of a system and the annoying spurs or noise
can not be tolerated from a fractional–N scheme. The adapt
feature is available on the main loop only.
For adapt, a timer is engaged which causes an internal
data update of the R and N registers to be delayed. The IC
supports the Horseshoe scheme for adapt by allowing a
fairly–close quickly–tuned approximate frequency to be
tuned, followed by the tuning of the exact frequency. Two sets
of R and N data are sent to the device. The first set {R1, N1}
is for tuning the approximate frequency. The second set {R2,
N2} is for tuning the exact frequency. Use of the timer delays
the transfer of {R2, N2} until a programmed interval has
elapsed. In addition, after the interval has elapsed, the main
loop control switches from PDout–Hi to PDout–Lo.
Tuning Near the Top of the Band
8C. PROGRAMMING WITHOUT ADAPT
Tuning the Top of the Band
After initializing the device via steps 1 through 6 in Section
8B, the only register that needs to be loaded to tune the main
loop is the N register.
For this example, tuning the upper end of the band
(500 MHz) requires that the 5 kHz at the phase/frequency
detector be multiplied up to 500 MHz. This is a loop
multiplying factor of 100,000. This value is converted to
$186A0 and is loaded for bits N17 to N0. Bits N23 to N18 are
not changed and are programmed as indicated in Section 8B,
step 5.
In summary, $8986A0 is transferred to tune the main loop.
No other registers are loaded.
Tuning Other Channels
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, only requires
programming the N register. See Table 22 for example
frequencies.
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Table 22. Main Loop Tuning Examples
Frequency
Desired
(MHz)
Multiplying
Factor
(Decimal)
Multiplying
Factor
(Hexadecimal)
N Register
Data
(Hexadecimal)
450.000
90,000
$15F90
$895F90
450.005
90,001
$15F91
$895F91
450.010
90,002
$15F92
$895F92
450.015
90,003
$15F93
$895F93
455.000
91,000
$16378
$896378
458.015
91,603
$165D3
$8965D3
471.040
94,208
$17000
$897000
500.000
100,000
$186A0
$8986A0
66
Continuing the example, after initializing the device via
steps 1 through 6 in Section 8B, Horseshoe with adapt can
be used to tune the main loop to obtain fast frequency jumps.
Use of the BitGrabber access is recommended to minimize
the number of serial data clocks required for sending the four
“words”.
In this example, the first phase of adapt utilizes
approximate tuning with the phase/frequency detector
running at 4x the step size. Therefore, the approximate
tuning runs the detector at about 20 kHz. The second phase,
with exact tuning, runs the detector at 5 kHz. Horseshoe with
adapt requires that two data sets be serially sent to the
device for every frequency tuned. The first set is for
approximate tuning {R1, N1}; the second set is for exact
tuning {R2, N2}.
Approximate tuning with Horseshoe is unique. This
method involves two key elements: (1) increasing the phase
detector frequency and (2) varying both the R and N divide
values such that the approximate frequency is within a
certain predetermined range. The Horseshoe algorithm
contained in the development system software also allows
placing a constraint on the loop–gain variation that the user
can tolerate.
For example, to tune 459.97 MHz, the first {R1, N1} data
set could contain divide ratios for the R and N counters of
973.5 and 23,034, respectively. With this data set, the phase
detector is running at about 19.97 kHz and the approximate
frequency is about 170 Hz from the exact frequency. The
second data set contains R and N divide values of 3,888 and
91,994, respectively. This achieves the exact (target)
frequency of 459.97 MHz.
The timer must be programmed to determine the interval
that the device is in the approximate–tune mode. For this
example, assume this is 32 fR cycles; thus, bits N21 N20
N19 = 1 0 1 in the first data set. Note that this time interval is
32 cycles of fR, with the phase detector running at about
20 kHz (approximate tune) or about 1.6 ms plus the MCU
shift time shown in Figure 64. Included in the first data set are
N23 = 1 which is required when the Mode pin is high, N22 = 0
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MC145181
for the lock detect window of 1.6 µs, and N18 = 0 for a current
ratio of 4:1 (because the phase detector is running at
approximately 4x the step size). Note that bits N23, N22, and
N18 are unchanged from the initialization values.
For the second data set, bits N23, N22, and N18 are
unchanged. Bits N21, N20, and N19 must be programmed as
0 0 1. This enables PDout–Lo for the exact tune after time out.
In summary, two data sets need to be sent to the device:
{R1, N1} and {R2, N2}. They are sent in succession as R1,
N1, R2, N2; where R1 is the R register value for the first data
set, N1 is the N register value for the first set, etc. For the
example, these values are {R1, N1} = {$079B, $A859FA} and
{R2, N2} = {$1E60, $89675A}. See Figure 64.
8E. CONTROLLING THE DACs
Introduction
The two 8–bit DACs are independent circuit blocks on the
chip. They have no interaction with other circuits on the chip.
A single 16–bit register, called the D register, holds the binary
value which controls both DACs.
Programming the DACs
A DAC programmed for 0 scale is in the low–power mode.
The 0 scale is programmed as $00 for each 8–bit DAC.
As an example, consider a system that uses just one of the
DACs (DAC 1). The other DAC output is unused and is
programmed for 0 output. If a condition for a system requires
that the DAC have a half–scale output, then DAC 1 is
programmed as $80.
In summary, $03000080 is serially transferred
(conventional access with an address of 0 0 1 1).
Tuning Other Channels
Freescale Semiconductor, Inc...
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, requires sending
two data sets to the part {R1, N1} and {R2, N2}. See Table 23.
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Table 23. Main Loop Tuning Using Horseshoe With Adapt
Approximate Tuning
Desired
Target
Frequency
(MHz)
R1
450.000
Exact Tuning
N1
Frequency
Error
(Hz)
R2
N2
$0798
$A857E4
0
$1E60
$895F90
450.005
$079B
$A85807
548
$1E60
$895F91
450.020
$0798
$A857E5
0
$1E60
$895F94
450.255
$0795
$A857CE
162
$1E60
$895FC3
459.970
$079B
$A859FA
170
$1E60
$89675A
500.000
$0798
$A861A8
0
$1E60
$8986A0
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67
68
Clk
D in
Enb
24
Initialize
N Register
After
Power Up
2
Figure 64.
1
16
24
Write
N Register
2
Cock
Timer
Enb
High
at
Least
N21 N20 N19
20 Osce
1
0
0
Cycles +
99 f in
1
0
1
Cycles
1
1
0
1
1
1
1
Enb High at
Least 20 Osce
Cycles
Write
Hr Register
2
N1
1
16
24
Write
N Register
2
N2
Timer
Fires
N21 N20 N19
0
0
1
1
Enb High at
Least 20 Osce
Cycles
Write
Hr Register
2
R2
Internal Data Transfer of
Exact Tune Data, Switch from
PDout–Hi to PDout–Lo
Exact Tune
(Not drawn
to scale)
Tune Next
Channel, Write
Hr Register
NOTE: The interval for shifting in Exact Tune {R2, N2} data adds to the actual Approximate Tuning time. However, this is usually insignificant. For example, at a data rate of 2 Mbps
(2 megabits per second), approximately 20 µ s is added to the Approximate Tuning time.
N21 N20 N19
0
0
1
1
R1
Actual Timer Interval
(Do Not Shift in Next Channel)
Total Time Out Interval For Approximate Tune
(Not drawn to scale)
Figure 64. Serial Data Format for Horseshoe with Adapt
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MC145181
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9. APPLICATION CIRCUIT
Figure 65. Application Circuit
Low–pass
Filter
Low–pass
Filter
Optional
Secondary
VCO
Vpos
24
23
22
21
Vpos PDout′ Creg Cmult
General–purpose
(Three–state)
Vpos
Freescale Semiconductor, Inc...
Main
VCO
25
26
27
Note 4
Vpos
R
SMD
Note 1
0.1 µF X7R
0805 SMD or Smaller
50 Ω
SMD
28
29
30
31
32
20
2k
19
18
17
PDout–Hi
PDout–Lo
Gnd
Output C
Output B
Vpos
Gnd
fout/Pol
Gnd
fout/Poli
fin
MC145181
Vpos
fin
fini
Vpos
Gnd
Mode
Output A
Oscb
DAC
Osce Vpos DAC1 DAC2 Enb
Din
Clk
1
6
7
2
3
4
5
General–purpose
(Open–drain)
Rx
16
15
14
0.1 µF X7R
0805 SMD or
Smaller
R
SMD
13
12
Vpos
11
10
9
50 Ω
SMD
Note 1
Note 5
General–purpose
(Totem–pole)
LD
8
DAC
Power
(Note 3)
NOTES: 1. R should be chosen to achieve the desired isolation. Use of a
capacitor in place of R is possible, but there is the possibility of
phase locking on VCO harmonics if they fall on the high–sensitivity
point of the fin or fini input. This is because use of a capacitor in
place of R forms a high–pass filter.
2. Vpos may range from 1.8 to 3.6 V.
3. DAC power may be any potential between 1.8 V and 3.6 V.
4. Configurable pins. See Pin Descriptions.
5. Tie mode to Gnd or Vpos.
ReFLEX Codec
or MCU
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10. OUTLINE DIMENSIONS
PLASTIC PACKAGE
CASE 873C–01
(LQFP–32)
ISSUE A
D
D
2
0.20 C A–B D
D
24
ALL 4 SIDES
17
b1
BASE METAL
25
16
Freescale Semiconductor, Inc...
c
c1
B
A
E1
E
ÉÉÉÉ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇÇ
ÉÉÉÉ
b
0.08
E1
2
E
2
32
9
M
PLATING
C A–B D
SECTION J–J
6
1
8
D1
2
0.10 H A–B D
ALL 4 SIDES
D1
J
0.080 C
K
J
C
4x
SEATING
PLANE
e/2
28x
e
q2
q1
R1
R2
A A2
0.25
H
A1
S
q3
q
L
L1
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS. AND
TOLERANCING PER ASME Y14.5M, 1994.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED
WHERE THE LEADS EXIT THE PLASTIC BODY AT
DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THAN 0.08 mm. DAMBAR CAN NOT BE
LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN A
PROTRUSION AND AN ADJACENT LEAD IS 0.07
mm.
6. EXACT SHAPE OF CORNERS MAY VARY.
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R1
R2
S
q
q1
q2
q3
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.18
0.27
0.17
0.23
0.10
0.20
0.09
0.16
7.00 BSC
5.00 BSC
7.00 BSC
5.00 BSC
0.50 BSC
0.45
0.75
1.00 REF
0.08
–––
0.08
0.20
0.20
–––
0_
7_
0_
–––
11_
13_
11_
13_
DETAIL K
70
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MC145181
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