TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 • • • • • • • • • • 8-Bit Serial-In Parallel-Out Driver 1-A Output Current Capability Per Channel or 8-A Total Current Overcurrent Limiting and Out-of-Saturation Voltage Protection on Driver Outputs Contains Eight Open-Collector Saturating Sink Outputs With Low On-State Voltage High-Impedance Inputs With Hysteresis Are Compatible With TTL or CMOS Levels Exceptionally Low On-State Supply Current 50 mA Very Low Standby Power 20 mW Typical Status of Output Drivers May Be Monitored at Serial Output 3-State Serial Output Permits Serial Cascading or Wire-AND Device Connections 45-V Transient Clamping With Inductive Switching on Outputs, 20-mJ Rating Per Driver Output KV PACKAGE (TOP VIEW) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Y4 Y5 Y6 Y7 RST VCC SO GND SI SCLK SIOE Y0 Y1 Y2 Y3 The tab is electrically connected to GND. description The TPIC2802 octal intelligent-power switch is a monolithic BIDFET† integrated circuit designed to sink currents up to 1 A at 45 V simultaneously at each of eight driver outputs under serial input data control. Furthermore, use of a Darlington output structure enables an 80% reduction in the on-state supply current compared with earlier designs. Status of the individual driver outputs is available in serial data format. The driver outputs have overcurrent limiting and out-of-saturation voltage protection features. Applications include driving solenoids, relays, dc motors, lamps, and other medium-current or high-voltage loads. The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit parallel latch, which independently controls each of the eight Y-output drivers. Data is entered into the device serially via the serial input (SI) and goes directly into the lowest bit (0) of the shift register. Using proper timing signals, the input data is passed to the corresponding output latch and output driver. A logic-high SI bit n turns the corresponding output driver (Yn)off. A logic-low bit at SI turns the corresponding output driver on. Serial data is transferred into SI on the high-to-low transition of the serial clock (SCLK) input in 8-bit bytes with data for the Y7 output (most significant bit) first and data for Y0 output (least significant bit) last. Both SI and SCLK are active when the serial input-output enable (SIOE) input is low and are disabled when SIOE is high. Each driver output is monitored by a voltage comparator that compares the Y-output voltage level with an internal out-of-saturation threshold voltage reference level. The logic state of the comparator output is dependent upon whether the Y output is greater or smaller than the reference voltage level. While SIOE is held high, an activated driver output is unlatched and turned off when the output voltage exceeds the out-of-saturation threshold voltage level except when the internal unlatch enable is low and disabled. The high-to-low transition of SIOE transfers the logic state of the comparator output to the shift register. † BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 functional block diagram RST Retriggerable One Shot H 11 One Shot SIOE SI SCLK 100 µs 1D C1 R 5 200 ns SR Bit 0 S 1D 7 4 S 1D 49 V R Comparator STD SR Bit 1 S 1D + – 10 V CC 1.8-V Reference Y1 Output Latch 3 S 1D Y1 49 V C1 C1 R SY1 Channels 2– 6 To D of SR3 From Q of SR6 SR Bit 7 S 1D + – 1.8-V Reference Y7 Output Latch 12 S 1D 49 V C1 C1 R SY7 SO Latch 1.8-V Reference 9 C1 R POST OFFICE BOX 655303 + – 3-State Buffer 1D 2–2 Y0 C1 C1 6 Y0 Output Latch • DALLAS, TEXAS 75265 SO Y7 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 Terminal Functions PIN I/O DESCRIPTION NAME NO. GND 8 RST 11 I Reset. An asynchronous reset is provided for the shift register and the parallel latches. This terminal is active when low and has no internal pullup. When active, it causes the power outputs to turn off. A power-on clear can be implemented using an RC network to VCC. SCLK 6 I Serial clock. This terminal clocks the shift register. The serial output (SO) changes state on the rising edge of SCLK and serial input (SI) data is accepted on the falling edge. SI 7 I Serial Input. A high on this terminal programs a particular output to be off, and a low turns it on. SIOE 5 I Serial input-output enable. Data is transferred from the shift registers to the power outputs on the rising edge of this signal. The falling edge of this signal parallel loads the output voltage sense bits from the power output stages into the shift register. The output driver SO is enabled when this terminal is low, provided RST is high. SO 9 O Serial output. This terminal is the serial 3-state output from the shift register and is in a high-impedance state when SIOE is high or RST is low. A high for a data bit on this terminal indicates that the corresponding power output (Yn) is high. This means that the output was programmed to be off the last time a byte was input to the device or that the output faulted and was latched off by the output voltage-sense indicator. A low on this output indicates that the corresponding power output (Yn) is low (on output stage or open-circuit condition). VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Ground. Common return for entire chip. The output current from this terminal is potentially as high as 8 A if all outputs are on. GND is used for both logic and power circuits. 10 4 3 2 1 15 14 13 12 5-V supply voltage O Power outputs. These outputs are provided with current limiting and voltage sense for fault indication and protection. The nominal load current for these outputs is 500 mA, and the current limiting is set to a minimum of 1 A. The active-low outputs also have voltage clamps set at about 45 V for recirculation of inductive load current. Internal 90-kΩ pulldown resistors are provided at each output. These resistors hold the output low during an open-circuit condition. schematic of inputs and outputs EQUIVALENT OF ALL LOGIC INPUTS (SI, SCLK, SIOE, RST) EQUIVALENT OF SERIAL OUTPUT (SO) EQUIVALENT OF Y OUTPUTS (Yn) VCC VCC VCC Output 49 V Input Output 90 kΩ GND All resistor and voltage values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 absolute maximum ratings over operating temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Output voltage range, SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 mA Peak output sink current at Y, IO repetitive, tw = 10 ms, duty cycle = 50%, (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Continuous output current at Y, IO (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Peak current through GND terminal: Nonrepetitive tw = 0.2 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 8 A Repetitive tw = 10 ms, duty cycle = 50% . . . . . . . . . . . . . . . . . . . . – 6 A Continuous current through GND terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 4.5 A Single-pulse avalanche energy rating, EAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mJ Avalanche current, IAS(max) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous dissipation at (or below) TA = 25°C (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.575 W Continuous dissipation at (or below) TC = 75°C (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W Operating case or virtual-junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. All voltage values are with respect to network GND. 2. Each Y output is individually current limited with a typical overcurrent limit of about 1.8 A. 3. Multiple Y outputs of this device can conduct rated current simultaneously; however, power dissipation (average) over a short time interval must fall within the continuous dissipation range and the GND terminal current range. 4. VCC = 20 V, starting TJ = 25°C, L = 310 mH, IAS = 0.28 A. 5. VCC = 10 V, starting TJ = 25°C, L = 8 mH, IAS = 1 A (see Figure 6). 6. For operation above 25°C free-air temperature, derate linearly at the rate of 28.6 mW/°C. For operation above 75°C case temperature, derate linearly at the rate of 333 mW/°C. To avoid exceeding the maximum virtual-junction temperature, these ratings must not be exceeded. recommended operating conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V High-level input voltage, VIH 0.75 VCC 5.25 V Low-level input voltage, VIL – 0.3 0.2 VCC V Output voltage, VO(off) 45 Continuous output current, IO(on) Operating case temperature, TC – 40 25 V 1 A 105 °C electrical characteristics over recommended operating virtual junction temperature range (unless otherwise noted) PARAMETER ICC 2–4 Supply current TEST CONDITIONS All outputs on, All outputs off, POST OFFICE BOX 655303 IO = 0.5 A at all outputs TJ = 25°C • DALLAS, TEXAS 75265 MIN TYP MAX 50 4 10 UNIT mA TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 electrical characteristics over recommended operating virtual junction temperature range (unless otherwise noted) (continued) driver array outputs (Y0 to Y7) PARAMETER VOK VO(on) ( ) Output clamp voltage On-state output voltage VTOS Out-of-saturation threshold voltage IO(off) IO(cl) Off-state output current Output current limit TEST CONDITIONS IO = 0.5 A, MIN TYP† 45 49 Output programmed off and current shunted to ground IOL = 0.175 A IOL = 0.5 A With one output programmed on and conducting d ti UNIT V 1 V 1 1.3 V 1.2 1.5 V 1.4 1.6 V 1.6 1.8 2.1 V 600 µA 1 1.8 A 40 90 kΩ IOL = 0.75 A IOL = 1 A, During unlatch disable With output programmed on and an overcurrent fault condition MAX VO = 24 V with output programmed off VO = 3 V with output programmed on Internal output pulldown resistor shift register (Inputs SI, SCLK, SCLK, and RST) PARAMETER VIT+ VIT – Positive-going threshold voltage Vhys II Hysteresis voltage (VIT+ – VIT–) Ci Input capacitance TEST CONDITIONS MIN MAX UNIT 0.75 VCC Negative-going threshold voltage 0.1 VCC V 0.85 Input current V 2.5 V ± 10 µA 20 pF TYP† MAX UNIT 0.2 0.4 VI = 0 to VCC VI = 0 to VCC shift register (output SO) PARAMETER VOL VOH Low-level output voltage High-level output voltage IO Output current Co Output capacitance † All typical values are at VCC = 5 V, TJ = 25°C. TEST CONDITIONS IO = 1.6 mA IO = – 0.8 mA MIN VCC –1.3 VO = 0 to VCC, VO = 0 to VCC, V V SIOE input high ±20 µA SIOE input high 20 pF timing requirements over recommended ranges of supply voltage and operating case temperature (see Figure 1) MIN MAX UNIT 0 1 MHz fclock tw(SCLKH) Clock frequency, SCLK tw(SCLKL) tw(RST) Pulse duration, SCLK low tsu1 tsu2 Setup time, SIOE↓ before SCLK↑ tsu3 th1 tr tf Rise time, SCLK, SI, SIOE 90 ns Fall time, SCLK, SI, SIOE 90 ns Pulse duration, SCLK high See Note 7 Pulse duration, RST low 410 ns 410 ns 1200 ns 1 µs Setup time, SCLK↓ before SIOE↑ 1 µs Setup time, SI high before SCLK↓ 150 ns Hold time, SI low after SCLK↓ 150 ns NOTE 7: For cascaded operation, the clock pulse durations (tw(SCLKL) and tw(SCLKH)) must be a minimum of 700 ns (giving a maximum clock frequency of 632 kHz). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 thermal characteristics PARAMETER RθJC Thermal resistance, junction-to-case temperature RθJA Thermal resistance, junction-to-ambient temperature MIN MAX UNIT 3 °C/W 35 °C/W switching characteristics over recommended ranges of supply voltage and operating case temperature PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN MAX UNIT ten tdis Enable time SIOE↓ SO CL = 20 pF, RL = 1 kΩ, See Figure 2 1000 ns Disable time SIOE↑ SO CL = 20 pF, RL = 1 kΩ, See Figure 2 1000 ns td1 td2 Delay time, valid data SCLK↑ SO CL = 200 pF, See Figure 3 Delay time, unlatch disable SIOE↑ CL = 20 pF, RL = 5 Ω, tr(SO) tf(SO) Rise time Yn SO CL = 200 pF, See Figure 3 Fall time SO CL = 200 pF, See Figure 3 RL = 28 Ω, IOL = 500 mA, IOL = 500 mA, td(on) Delay time, turn on SIOE↑ Yn CL = 20 pF, See Figure 5 td(off) Delay time, turn off SIOE↑ Yn CL = 20 pF, See Figure 5 RL = 28 Ω, tv Valid time, SO output data remains valid after SCLK high SCLK↑ SO CL = 200 pF, See Figure 3 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 See Figure 4 75 0 550 ns 450 µs 150 ns 150 ns 10 µs 10 µs ns TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 PARAMETER MEASUREMENT INFORMATION VIH RST 10% 10% VIL tw(RST) VIH SIOE 10% 10% tsu1 tw(SCLKH) 90% SCLK 90% 10% tsu3 SI tr ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Don’t Care 90% 10% VIH 90% 10% tw(SCLKL) 10% VIL ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tf th 90% 90% Valid 10% 10% VIL tsu2 VIH Don’t Care Valid Don’t Care VIL Figure 1. Input Timing Waveforms 10 ns 5V 10 ns 2.5 V 5V 10 VCC TPIC2802 9 Under SO Test 5 Input SIOE GND RL = 1 kΩ SIOE Input 90% 0V tdis ten SO Output Waveform 1 (see Note B) 2.5 V 50% 50% VOL 8 TEST CIRCUIT FOR ENABLE AND DISABLE TIMES 90% 10% 2.5 V 10% Output CL = 20 pF (see Note A) 2.5 V ten SO Output Waveform 2 (see Note B) tdis VOH 50% 50% 2.5 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control when SIOE is high. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from off to on. Figure 2. Test Circuit and Voltage Waveforms for Enable and Disable Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 PARAMETER MEASUREMENT INFORMATION 5V Input 10 ns 10 VCC 9 TPIC2802 Under SO 6 Test SCLK GND SCLK Input 10 ns 10% 8 0V td1 Output CL = 200 pF (see Note A) 5V 90% 50% tv SO Output Waveform 1 (see Note B) VOH 90% 10% VOL tr(SO) td1 TEST CIRCUIT tv SO Output Waveform 2 (see Note B) VOH 90% 10% VOL tf(SO) VOLTAGE WAVEFORMS NOTES: C. CL includes probe and jig capacitance. D. Waveform 1 is for an output with internal conditions such that the low-to-high transition of SCLK causes the SO output to switch from high to low. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from off to on. Figure 3. Test Circuit and Voltage Waveforms for Delay Times 5V 15 V 10 Input 5 VCC TPIC2802 Under Test SIOE GND 10 ns Y 8 TEST CIRCUIT Output CL = 20 pF (see Note B) 10 ns SIOE Input RL = 5 Ω (see Note A) 90% 90% 50% 50% 10% Y-Output Voltage (see Note C) 50% 10% 0V Voff = 15 V 50% td2 (see Note D) Y-Output Current (see Note C) 5V Von = 6 V IO(CL) = 1.8 A 50% 0 VOLTAGE WAVEFORMS NOTES: A. Load voltage VS and load resistance RL are selected such that on-state voltage at the Y output under test, Von is greater than the maximum out-of-saturation hold voltage, VTOS. Thus VOL = Von > VTOS(max) = 2.1 V. B. CL includes probe and jig capacitance. C. Output voltage and current waveforms are for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from off to on. D. td2 = delay until Y-output current goes off under fault condition. Figure 4. Test Circuit and Voltage Waveforms for Unlatch Disable Delay 2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 PARAMETER MEASUREMENT INFORMATION 14 V 10 ns 5V SIOE Input 10 RL = 28 Ω VCC Input 5 SIOE 10 ns TPIC2802 Under Test 10% 90% 90% 50% 50% 5V 10% 0V Output Y CL = 20 pF (see Note A) Y-Output Waveform 1 (see Note C) 8 GND td(off) 14 V 50% VOL td(on) 14 V Y-Output Waveform 2 (see Note C) TEST CIRCUIT FOR TURN-OFF td(off) AND TURN-ON td(on) DELAY TIMES (see Note B) 50% VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. td(off) = tPLH, td(on) = tPHL C. Waveform 1 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from on to off. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from off to on. Figure 5. Test Current and Voltage and Current Waveforms for Turn-Off and Turn-On Delay Times 10 V 5V IAS = 1 A IC 10 L = 8 mH IC VCC Input TPIC2802 Under 5 Test SIOE GND 0 Y Output V(BR)CEX VCE 0 8 tav (b) VOLTAGE AND CURRENT WAVEFORMS (a) TEST CIRCUIT Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–9 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE PEAK AVALANCHE CURRENT vs JUNCTION TEMPERATURE 800 1000 tav = 0.5 ms I AS – Peak Avalanche Current – mA I AS – Peak Avalanche Current – mA TJS = 25°C TJS = 75°C 100 TJS = 125°C 10 TJS = Starting Junction Temperature 700 tav = 1 ms 600 tav = 3 ms 500 tav = 7 ms 400 300 200 100 0.1 1 10 0 100 0 20 40 60 80 100 120 140 160 180 200 TJS – Starting Junction Temperature – °C tav – Time Duration of Avalanche – ms Figure 7 Figure 8 APPLICATION INFORMATION 10 5 7 Microcontroller With Bus VCC Y0 SIOE Y1 Y2 SO Y3 L 14 V ± 0.5 V 3 1 SCLK Y4 11 RST R 2 SI 9 6 4 Y5 8 15 14 13 GND Y6 12 VCC = 5 V ± 5% R = 30 Ω ± 5% L = 45 mH ±10% 8 Loads up to 0.5 A Each Y7 TPIC2802 Figure 9. Microcontroller Driving Eight Loads Using a TPIC2802 for Load Interface 2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 PRINCIPLES OF OPERATION timing data transfer Figure 10 shows the overall 8-bit data-byte transfer to and from the TPIC2802 interface bus. The logic state of the eight output drivers, Y0 through Y7, is latched into the shift register at time t0 on the high-to-low transition of SIOE. Therefore, the SO output data (DY0, DY1 . . . ) represent the conditions at the Y-driver outputs at time t0. The data at the SO output is updated on the low-to-high transition of SCLK. Input data present at the SI input is clocked into the shift register on the high-to-low transition of SCLK. As shown in Figure 10 on the SI input, input data DI7 is clocked at time t1, DI6 is clocked at time t2, etc. Eight SCLK pulses are used to serially load the eight bits of new data into the device. After all the new data is serially loaded, the low-to-high transition of SIOE parallel loads the new data to the eight driver output latches, which in turn directly control the eight Y-driver outputs. An unlimited amount of data can be shifted through the shift register (into the SI and out the SO), and this allows other devices to be cascaded in a daisy chain with the TPIC2802. Once the last data bit has been shifted into the TPIC2802, the SIOE input is pulled high. The clock (SCLK) input is low at both transitions of the SIOE input to avoid any false clicking of the shift register. The SCLK input is gated by the SIOE input, so the SCLK input is ignored whenever SIOE is high. At the rising edge of SIOE, the shift register data is latched into the parallel latch and the output stages are actuated by the new data. An internal 100-µs delay timer is also started on this rising edge. During the time delay, the outputs are protected only by the analog current-limiting circuits, since the resetting of the parallel latches by fault conditions are inhibited during this time period. This allows the device to overcome any high switching currents that can flow during turn-on. Once the delay ends, the output voltages are sensed by the comparators and any output voltages higher than nominally 1.8 V are latched off. Time t0 t1↑ t1↓ t2↑ t2↓ t3↑ t3↓ t4↑ t4↓ t5↑ t5↓ t6↑ t6↓ t7↑ t7↓ t8↑ t8↓ t9↑ H SIOE L H ÇÇÇ ÇÇÇ ÇÇÇ SCLK SI SO CP1 CP2 DI7 DY7 CP3 DI6 DY6 CP4 DI5 DY5 CP5 DI4 CP6 DI3 DY4 DY3 CP7 DI2 DY2 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ CP8 DI1 DY1 L H DI0 DY0 L H HI-Z L Y0 Prior (old) H DI0 (new) L Y1 Prior (old) H DI1 (new) L Y7 Prior (old) H DI7 (new) L Figure 10. Data-Byte Transfer Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–11 TPIC2802 OCTAL INTELLIGENT-POWER SWITCH WITH SERIAL INPUT SLIS013 – APRIL 1992 fault-conditions check Open-circuit conditions on any output can be monitored or checked by programming that output off. After a short delay (microseconds), another control byte can be clocked into the device. If the diagnostic bit for that output comes back low, it indicates that the output is low and open circuited. A current overload condition can be detected by programming an output on. After waiting an appropriate length of time, another byte is clocked into the TPIC2802. The diagnostic bit clocked back from the TPIC2802 in the subsequent data transfer indicates a low output. If a high returns, a current overload is indicated. A quick overall check can be done by clocking in a test control byte and after a sufficient time delay, clock in another control byte. The diagnostic data is exclusive ORed with the original control byte. If a fault condition exists, a high results from the subsequent exclusive OR. 2–12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated