SLDS031A – APRIL 1985 – REVISED APRIL 1993 High-Speed Serially-Shifted Data Input Totem-Pole Outputs Latches on All Driver Outputs description The SN65555, SN75555, SN65556, and SN75556 are monolithic BIDFET† integrated circuits designed to drive the column electrodes of an electroluminescent display. The SN65556 and SN75556 output sequence is reversed from the SN65555 and SN75555 for ease in printed-circuitboard layout. The devices consist of a 32-bit shift register, 32 latches, and 32 output AND gates. Serial data is entered into the shift register on the low-to-high transition of CLOCK. When high, LATCH ENABLE transfers the shift register contents to the outputs of the 32 latches. When OUTPUT ENABLE is high, all Q outputs are enabled. Data must be loaded into the latches and OUTPUT ENABLE must be high before supply voltage VCC2 is ramped up. Serial data output from the shift register can be used to cascade shift registers. This output is not affected by LATCH ENABLE or OUTPUT ENABLE. Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 SERIAL OUT CLOCK GND 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 OUTPUT ENABLE DATA IN LATCH ENABLE VCC1 VCC2 SN65555, SN75555 . . . FN PACKAGE (TOP VIEW) Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 7 6 5 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 NC SERIAL OUT NC NC NC CLOCK GND VCC2 VCC1 LATCH ENABLE DATA IN OUTPUT ENABLE The SN65555 and SN65556 are characterized for operation from – 40 C to 85 C. The SN75555 and SN75556 are characterized for operation from 0 C to 70 C. SN75555 . . . N PACKAGE (TOP VIEW) Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Each Device Drives 32 Electrodes 90-V Output Voltage Swing Capability Using Ramped Supply 15-mA Output Source and Sink Current Capability NC – No internal connection † BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process. Copyright POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1993, Texas Instruments Incorporated 4–1 SLDS031A – APRIL 1985 – REVISED APRIL 1993 SN65556, SN75556 N PACKAGE (TOP VIEW) 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 Q21 Q20 Q19 Q18 Q17 Q16 Q15 Q14 Q13 Q12 Q11 1 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 OUTPUT ENABLE DATA IN LATCH ENABLE VCC1 VCC2 6 5 4 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 7 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 NC SERIAL OUT NC NC NC CLOCK GND VCC2 VCC1 LATCH ENABLE DATA ENABLE OUTPUT ENABLE Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 SERIAL OUT CLOCK GND SN65556, SN75556 FN PACKAGE (TOP VIEW) NC – No internal connection logic symbols† SN65555, SN75555 VCC2 21 OUTPUT ENABLE 25 LATCH ENABLE 23 CLOCK 19 DATA IN 24 SN65556, SN75556 CMOS/EL DISP V CC2 21 25 OUTPUT ENABLE 23 LATCH ENABLE [PWR Q1-32] EN3 C2 SRG 32 C1/ 1D CLOCK 2D 2D 3 3 17 Q1 16 Q2 2D 2D 3 3 2D 2D 3 3 19 3 3 26 Q1 27 Q2 1 Q17 40 Q18 2D 2D 3 3 40 Q15 1 Q16 27 Q31 26 Q32 18 SERIAL OUT 2D 2D 3 3 16 Q31 17 Q32 18 SERIAL OUT † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for N packages. 4–2 SRG 32 C1/ 2D 2D DATA IN 24 CMOS/EL DISP [PWR Q1-32] EN3 C2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1D SLDS031A – APRIL 1985 – REVISED APRIL 1993 logic diagram (positive logic) V CC2 OUTPUT ENABLE LATCH ENABLE Output Buffers Shift Register DATA IN 1D CLOCK Latches R1 C2 LC1 Q1 LC2 Q2 2D C1 1D R2 C1 C2 2D 28 Stages (Q3 thru Q30) Not Shown 1D R31 C1 C2 LC31 Q31 LC32 Q32 2D 1D R32 C1 C2 2D SERIAL OUT FUNCTION TABLE CONTROL INPUTS FUNCTION OUTPUTS SHIFT REGISTER R1 THRU R32 LATCHES LC1 THRU LC32 SERIAL Q1 THRU Q32 LATCH ENABLE OUTPUT ENABLE No X X X X Load and shift† No change Determined by LATCH ENABLE‡ R32 R32 Determined by OUTPUT ENABLE Latch X X L H X X As determined above Stored data New data R32 Determined by OUTPUT ENABLE Output Enable X X X X L H As determined above Determined by LATCH ENABLE‡ R32 R32 All L LC1 thru LC21, respectively CLOCK Load H = high level, L = low level, X = irrelevant, = low-to-high-level transition. † R32 and the serial output take on the state of R31, R31 takes on the state of R30,. . .R2 takes on the state of R1, and R1 takes on the state of the data input. ‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 4–3 SLDS031A – APRIL 1985 – REVISED APRIL 1993 typical operating sequence CLOCK DATA IN Valid Irrelevant Invalid Valid Previously Stored Data New Data Valid SR Contents LATCH ENABLE Latch Contents OUTPUT ENABLE VCC2 Valid Q Outputs schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS VCC2 VCC1 VCC1 Output Input Output GND 4–4 TYPICAL OF SERIAL OUTPUT GND POST OFFICE BOX 655303 DALLAS, TEXAS 75265 GND SLDS031A – APRIL 1985 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Supply voltage, VCC2 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1 + 0.3 V Ground current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: SN65555, SN65556 . . . . . . . . . . . . . . . . . . . . . . . – 40 C to 85 C SN75555, SN75556 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65 C to 150 C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260 C NOTES: 1. Voltage values are with respect to network GND. 2. These devices have been designed to be used in applications in which the high-voltage supply, V CC2, is switched to GND before changing the state of the outputs. DISSIPATION RATING TABLE PACKAGE TA 25 C POWER RATING DERATING FACTOR ABOVE TA = 25 C TA = 70 C POWER RATING TA = 85 C POWER RATING FN 1700 mW 13.6 mW/ C 1088 mW 884 mW N 1250 mW 10.0 mW/ C 800 mW 650 mW recommended operating conditions MIN NOM MAX Supply voltage, VCC1 10.8 12 15 V Supply voltage, VCC2 0 80 V 8.1 11.1 11.25 – 0.3† 15.3 – 0.3† 3.75 High level input voltage High-level voltage, V IH (see Figure 1) VCC1 = 10.8 V VCC1 = 15 V Low level input voltage Low-level voltage, V IL (see Figure 1) VCC1 = 10.8 V VCC1 = 15 V 2.7 UNIT V V – 15 mA Low-level output current, IOL 15 mA Output clamp current, IOK 20 mA 6.25 MHz High-level output current, IOH Clock frequency, fclock 0 Pulse duration, CLOCK high or low, tw(CLK) (see Figure 2) 80 ns Pulse duration, LATCH ENABLE, tw(LE) 80 ns Setup time, time tsu Hold time, time th DATA IN before CLOCK (see Figure 2) OUTPUT ENABLE before VCC2 (see Figure 4) DATA IN after CLOCK (see Figure 2) OUTPUT ENABLE after VCC2 (see Figure 4) 20 80 ns 100 Rate of rise for V CC2, dv/dt Operating free-air free air temperature, temperature TA ns 500 80 SN65555, SN65556 – 40 85 SN75555, SN75556 0 85 V/ s C † The algebraic convention, in which the least positive (most negative) value is designated as minimum, is used in this data sheet for logic voltage levels. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 4–5 SLDS031A – APRIL 1985 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range, VCC1 = 12 V, VCC2 = 80 V PARAMETER V OH High level output voltage High-level V OL Low level output voltage Low-level IIH High-level input current IIL Low-level input current ICC1 ICC2 TEST CONDITIONS IO = – 15 mA IO = – 100 A Q outputs SERIAL OUT Q outputs MIN 8 1 V I = 12 V VI = 0 UNIT V 10.5 IOL = 15 mA IOL = 100 A SERIAL OUT MAX 77 1 V A –1 A Supply current from VCC1 2 mA Supply current from VCC2 5 mA switching characteristics, VCC1 = 12 V, TA = 25 C TEST CONDITIONS PARAMETER tPHL Propagation delay time, high-to-low-level, SERIAL OUT from CLOCK tPLH Propagation delay time, low-to-high level, SERIAL OUT from CLOCK td Delay time, VCC2 to Q outputs CL = 20 pF to GND,, See Figure 3 V CC2 = 0,, dv/dt = 80 V/ s, See Figure 4 RECOMMENDED OPERATING CONDITIONS INPUT VOLTAGE LOGIC-LEVEL LIMITS vs SUPPLY VOLTAGE VCC1 12 TA = Full Range VVII – Input Voltage – V 10 Minimum VIH 8 6 4 Maximum V IL 2 2 10 11 12 13 14 V CC1 – Supply Voltage – V Figure 1 4–6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15 MIN MAX UNIT 140 ns 140 ns 100 ns SLDS031A – APRIL 1985 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION tw(CLK) VIH CLOCK 50% 50% 50% VIL tw(CLK) tsu th VIH Valid DATA IN VIL Figure 2. Input Timing Voltage Waveforms VIH CLOCK 50% VIL t PLH VOH 50% SERIAL OUT VOL t PHL VOH SERIAL OUT 50% VOL Figure 3. Voltage Waveforms for Propagation Delay Time, CLOCK to SERIAL OUT VIH OUTPUT ENABLE 50% 50% VIL 80 V tsu th VCC2 10% 10% td Q Output 0V VOH Valid 10% VOL Figure 4. Voltage Waveforms for Delay Times, VCC2 to Q Outputs POST OFFICE BOX 655303 DALLAS, TEXAS 75265 4–7 SLDS031A – APRIL 1985 – REVISED APRIL 1993 4–8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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