SLLS615 − APRIL 2004 features D D D D D D D D D applications D SONET OC−192 D 10-Gbps Ethernet Receivers D 10-Gbps Fibre Channel Receivers 11.2-GHz Bandwidth 5.5-kΩ Differential Transimpedance 8.5-pA//Hz Typical Input Referred Noise 2-mA Maximum Input Current Received Signal Strength Indication CML Data Outputs Offset Cancellation Single 3.3-V Supply Bare-Die Option description The ONET9901TA is a high-speed transimpedance amplifier used in SDH/SONET systems with data rates up to 10.7 Gbps. It features a low input referred noise, 11.2-GHz bandwidth and a 5.5-kΩ transimpedance. The ONET9901TA device is available in die form and requires a single 3.3-V supply. The ONET9901TA is power efficient and dissipates less than 100 mW (typical). The ONET9901TA is characterized for operations from 0_C to 85_C. available options TA 0°C to 85°C PACKAGED DEVICE ONET9901TAY Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$ %&!!'$ # &(%#$ )#$' !)&%$ %!" $ '%%#$ '! $*' $'!" '+# $!&"'$ $#)#!) ,#!!#$- !)&%$ !%'. )' $ '%'#!(- %(&)' $'$. #(( #!#"'$'! POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLLS615 − APRIL 2004 block diagram The ONET9901TA is a high performance 10.7-Gbps transimpedance amplifier that can be segmented into the signal path, filter, and offset cancellation block. The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and an output buffer. The filter circuit provides a filtered VCC for the photodiode. The offset correction circuit uses an internal low-pass filter to cancel the dc on the input and it provides a signal to monitor the received signal strength. A simplified block diagram of the ONET9901TA is shown in Figure 1. RSSI VCCI 410 W Disable FILTER Bandgap Voltage Reference and Bias Current Generation Offset Cancellation 1 kW RF VCCO TEST + + OUT+ − − OUT− IN Transimpedance Amplifier Voltage Amplifier GND CML Output Buffer Figure 1. Block Diagram signal path The first stage of the signal path is a transimpedance amplifier that takes the photodiode current and converts it to a voltage signal. The second stage is a voltage amplifier that provides additional gain. The output of the second stage feeds the output buffer and the offset cancellation circuitry. The third and final signal path stage of the ONET9901TA is the output buffer. The output buffer provides CML outputs with an on-chip 50-Ω back-termination to VCCO. filter circuitry The filter pin provides a filtered VCC for the photodiode bias. The on-chip low-pass filter for the photodiode VCC is implemented using a filter resistor of 410 Ω and an internal capacitor. If additional filtering is required for the application, an external capacitor should be connected to the FILTER pin. offset cancellation and RSSI The offset cancellation circuitry performs low pass filtering of the output of the voltage amplifier. This senses the dc offset at the input of the ONET9901TA. The circuitry subtracts current from the input to effectively cancel the dc. The sensed current is mirrored and is used to generate the RSSI output through an external 10-kΩ resistor. To disable the offset correction loop, the FILTER pin should be tied to GND. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS615 − APRIL 2004 bond pad assignment RSSI VCCO 17 16 18 VCCI The ONET9901TA is available as bare-die. The location of the bondpads is shown in Figure 2. The circuit is characterized for ambient temperatures between 0°C and 85°C. PAD#1 VCCI 1 15 VCCO VCCI 2 14 VCCO FILTER 3 13 GND TEST 4 12 OUT+ IN 5 11 OUT– GND 6 GND 9 GND 8 GND 7 10 GND Figure 2. Bond Pad Assignment of the ONET9901TA terminal functions The following table shows a pad description for the ONET9901TA. TERMINAL TYPE DESCRIPTION NAME NO. VCCI 1, 2, 18 Supply Input stage 3.3-V ±10% supply voltage. FILTER 3 Analog Bias voltage for the photodiode (connects to an internal 410-Ω resistor to VCCI). To disable the offset correction loop, connect the FILTER pin to GND. TEST 4 Analog in Test pad. Connects to IN via a 1-kΩ resistor. Data input to TIA IN 5 Analog in GND 6−10,13 Supply OUT− 11 Analog out Inverted data output. On-chip 50-Ω back-terminated to VCCO. OUT+ 12 Analog out Non-inverted data output. On-chip 50-Ω back-terminated to VCCO. VCCO 14−16 Supply RSSI 17 Analog out Circuit ground Output stage 3.3-V ±10% supply voltage. Analog output voltage proportional to the input data amplitude. Indicates the strength of the received signal (RSSI). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLLS615 − APRIL 2004 absolute maximum ratings over operating free-air temperature range unless otherwise noted† VALUE UNIT VCCI, VCCO V(FILTER), V(OUT+), V(OUT−), V(RSSI) Supply voltage, See Note 1 –0.3 to 4 V Voltage at FILTER, OUT+, OUT−, and RSSI, See Note 1 –0.3 to 4 V I(IN), I(TEST) I(FILTER) Supply current into IN and TEST −5 to 5 mA Supply current into FILTER −8 to 8 mA I(OUT+), I(OUT−) ESD Continuous current at outputs −25 to 25 mA TJ(max) Tstg Maximum junction temperature ESD rating at all pins Storage temperature range 2 kV (HBM) 125 °C −65 to 85 °C TA Operating free-air temperature range 0 to 85 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the network ground terminal. recommended operating conditions MIN TYP MAX Supply voltage, VCCI, VCCO 3 3.3 3.6 UNIT V Operating free-air temperature, TA 0 85 °C dc electrical characteristics over recommended operating conditions (unless otherwise noted), typical operating condition is at VCCI = VCCO = 3.3 V and TA = 25°C PARAMETER VCC ICC Supply voltage VIN ro Input bias voltage r(FILTER) Photodiode filter resistance 4 TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 V 30 41 mA 0.84 0.96 Supply current Output resistance Single-ended to VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 410 V Ω 50 330 UNIT 500 Ω SLLS615 − APRIL 2004 ac electrical characteristics over recommended operating conditions (unless otherwise noted), typical operating condition is at VCCI = VCCO = 3.3 V and TA = 25°C PARAMETER IIN,OVL TEST CONDITIONS AC input overload current MIN TYP MAX 2 Input linear range 0.95 < linearity < 1.05 ARSSI Z(21) RSSI gain Small signal transimpedance BW(H_3dB) BW(L_3dB) Small signal bandwidth CPD = 0.2 pF Low frequency −3 dB bandwidth −3 dB, IIN = < 50 µAp−p dc BW(H_3dB_RSSI) IN,IN RSSI bandwidth UNIT mAp−p µAp−p 50 60 10-kΩ load, See Note 2 1500 2000 2500 Differential output, 10 µAp−p < IIN = < 50 µAp−p 4400 5500 6600 V/A Ω 11.2 GHz 17 kHz 5 kHz Input referred RMS noise CPD = 0.2 pF 900 nA Input referred noise density CPD = 0.2 pF 8.5 pA/√Hz DJ Deterministic jitter IIN < 1.3 mAp−p (K28.5 pattern) IIN = 2 mAp−p (K28.5 pattern) VOD(max) Maximum differential output voltage IIN = 1 mAp−p 7 11 22 psp−p 500 700 mVp−p NOTE 2: On the chip, a 6725-Ω resistor is used in parallel to the external 10-kΩ resistor, resulting in a total 4-kΩ resistor for a typical process. By choosing an appropriate external resistor, the typical RSSI gain can be adjusted. Without an external resistor, the RSSI gain is approximately 3360 V/A under typical conditions. APPLICATION INFORMATION Figure 3 shows the ONET9901TA being used as a receiver in a typical fiber optic application. The ONET9901TA converts the electrical current generated by the PIN photodiode into a differential voltage output. The FILTER input provides a dc bias voltage for the PIN that is low pass filtered by the combination of the internal 410-Ω resistor and internal capacitor. For additional power supply filtering, use an external capacitor (CFILTER). The RSSI output is used to mirror the photodiode output current and must be connected via a 10-kΩ resistor to GND or left open. Within the ONET9901TA, the OUT+ and OUT− pins are internally terminated by a 50-Ω pullup to VCCO. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLLS615 − APRIL 2004 RSSI VCC 18 17 16 10 kW 1 15 PAD#1 2 14 3 410 W 4 ONET 9901TA 13 12 5 C1 OUT+ 11 OUT− 6 10 C2 CFILTER (Optional) 7 8 9 GND Figure 3. Basic Application Circuit board layout Careful attention to board layout parasitics and external components is necessary to achieve optimal performance with a high-performance transimpedance amplifier like the ONET9901TA. Recommendations that optimize performance include: 1. Minimize total capacitance on the IN pad by using a low-capacitance photodiode and paying attention to stray capacitances. Place the photodiode close to the ONET9901TA die in order to minimize the bond wire length and thus the parasitic inductance. 2. The external filter capacitor (CFILTER) may have an impact on the transfer function of the TIA and must be chosen with care based on the module implementation. 3. Use identical termination and symmetrical transmission lines at the differential output pins OUT+ and OUT–. 4. Use short bond wire connections for the supply terminals VCCI, VCCO, and GND. Provide sufficient supply voltage filtering. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS615 − APRIL 2004 chip dimensions and pad locations PAD#1 1189 µm Y Origin 0,0 729 µm X Figure 4. Chip Dimensions and Pad Locations Figure 5. Chip Layout POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLLS615 − APRIL 2004 PAD LOWER LEFT COORDINATE UPPER RIGHT COORDINATE SYMBOL TYPE DESCRIPTION x [mm] y [mm] x [mm] y [mm] 1 57 887 162 972 VCCI Supply Input stage 3.3-V ±10% supply voltage 2 57 767 162 852 VCCI Supply Input stage 3.3-V ±10% supply voltage 3 67 637 152 722 FILTER Analog Bias voltage for photodiode 4 67 517 152 602 TEST Analog in Test pad. Connects to IN via a 1-kΩ resistor 5 67 397 152 482 IN Analog in Data input to TIA 6 57 267 162 352 GND Supply Circuit ground 7 162 57 247 162 GND Supply Circuit ground 8 327 57 412 162 GND Supply Circuit ground 9 492 57 577 162 GND Supply Circuit ground 10 567 237 672 322 GND Supply Circuit ground 11 577 367 662 452 OUT– Analog out Inverted data output 12 577 487 662 572 OUT+ Analog out Non-inverted data output 13 567 617 672 702 GND Supply Circuit ground 14 567 747 672 832 VCCO Supply Output stage 3.3-V ±10% supply voltage 15 567 877 672 962 VCCO Supply Output stage 3.3-V ±10% supply voltage 16 492 1027 577 1132 VCCO Supply Output stage 3.3-V ±10% supply voltage 17 327 1027 412 1132 RSSI Analog out 18 162 1027 247 1132 VCCI Supply RSSI output voltage signal Input stage 3.3-V ±10% supply voltage Table 1. Pad Locations and Description of the ONET9901TA 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS615 − APRIL 2004 TYPICAL CHARACTERISTICS INPUT REFERRED NOISE CURRENT vs AMBIENT TEMPERATURE 1600 1600 1500 1500 Input Referred Noise Current − nARMS Input Referred Noise Current − nARMS INPUT REFERRED NOISE CURRENT vs AVERAGE INPUT CURRENT 1400 1300 1200 1100 1000 900 800 700 600 1400 1300 1200 1100 1000 900 800 700 600 0 200 400 600 800 1000 0 1200 10 20 30 50 60 70 80 90 80 90 Figure 7 Figure 6 TRANSIMPEDANCE vs AMBIENT TEMPERATURE DIFFERENTIAL OUTPUT VOLTAGE vs INPUT CURRENT 300 78 200 77 Transimpedance − dBΩ Differential Output Voltage − mV 40 Ambient Temperature − °C Average Input Current − µA 100 0 −100 76 75 74 73 −200 −300 −1000 −750 −500 −250 72 0 250 500 750 1000 0 10 20 30 40 50 60 70 Ambient Temperature − °C Input Current − µA Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLLS615 − APRIL 2004 TYPICAL CHARACTERISTICS RSSI OUTPUT VOLTAGE vs AVERAGE INPUT CURRENT SMALL SIGNAL BANDWIDTH vs AMBIENT TEMPERATURE 2.5 2.0 12 RSSI Output Voltage − V Small Signal Bandwidth − GHz 13 11 10 1.5 1.0 0.5 0.0 9 0 10 20 30 40 50 60 70 80 0 90 200 400 Figure 11 Figure 10 DETERMINISTIC JITTER vs INPUT CURRENT 12 Deterministic Jitter − psP-P 10 8 6 4 2 0 0 250 500 750 1000 1250 1500 1750 2000 Input Current − µAP-P Figure 12 10 600 800 Average Input Current − µA Ambient Temperature − °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1000 1200 SLLS615 − APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT EYE DIAGRAM AT 10.7 GBPS AND 2 mAP-P INPUT CURRENT Differential Output Voltage − 25 mV/Div Differential Output Voltage − 100 mV/Div OUTPUT EYE DIAGRAM AT 10.7 GBPS AND 20 mAP-P INPUT CURRENT Time − 20 ps/Div Time − 20 ps/Div Figure 13 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing ONET9901TAY ACTIVE XCEPT Y Pins Package Eco Plan (2) Qty 0 360 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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