POWERINT SMP402

®
SMP402
1-Watt Buck Regulator IC
20-72 VDC Input
Non-isolated DC Output
Product Highlights
Integrated Power Switch and CMOS Controller
• Output power > 1 W from 48 VDC input
• Adjustable output voltage
• Integrated solution minimizes overall size
+
+
48 VDC
5 VDC
-
-
High-voltage, Low-capacitance MOSFET Output
• Designed for ISDN T1 telecommunications applications
• Low capacitance allows for high frequency operation
High-voltage Buck Regulator
• Internal pre-regulator self-powers the IC on start-up
• Designed for low power consumption
• Minimum external parts required
Built-In Self-protection Circuits
• Undervoltage lockout
• Thermal shutdown
• Input polarity/level sense
Description
The SMP402, intended for non-isolated ISDN
telecommunications power supply applications, combines a
high voltage power MOSFET switch with a switchmode power
system controller in a monolithic integrated circuit. Few
external components are required to implement a low cost
power supply which meets stringent ISDN specifications. High
frequency operation reduces total power supply size.
The P-channel power MOSFET switch features include high
voltage, low RDS(ON), and low capacitance. Lower capacitance
results in a reduction in gate drive power, and also facilitates
higher frequency operation.
The controller section of the SMP402 contains all the blocks
required to drive and control the power stage: start-up preregulator circuit, oscillator, bandgap reference, error amplifier,
gate driver and level shift. Protection features include
undervoltage lockout, thermal shutdown, and input polarity
and level sensing.
SMP402
PI-555A-123091
Figure 1. Typical Application.
VIN
VLS
ENABLE
D GND
A GND
SENSE+
SENSE REXT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
POLARITY
LEVEL
VS
EA IN
EA OUT
VBIAS
CEXT
PI-553B-012892
Figure 2. Pin Configuration.
ORDERING INFORMATION
PART
NUMBER
PACKAGE
OUTLINE
Tj
RANGE
SMP402SC
S16A
0 to 120°C
The SMP402 is available in a 16-pin plastic SOIC package.
January 1996
SMP402
VIN
OUT
VLS
ENABLE
VBIAS
VS
UV
LOCKOUT
HV
REG
LEVEL
SHIFT
VREF
A GND
THERMAL
SHUTDOWN
BANDGAP
REF
REXT
D GND
S
CEXT
+
EA OUT
S
Q
R
R
+
EA IN
Q
OSC
PWM COMPARATOR
-
ERROR
AMPLIFIER
4V
+
VS
VS
23 µA
5 µA
SENSE+
LEVEL
POLARITY
VS
VS
23 µA
5 µA
SENSE-
PI-552B-062293
Figure 3. Functional Block Diagram.
2
D
1/96
SMP402
Pin Functional Description
Pin 1:
VIN is the high-voltage input to the
switching regulator. This is the Source
connection of the P-Channel power
MOSFET pass transistor.
Pin 6:
The SENSE+ input monitors the polarity
and level of the input voltage through an
external resistor for ISDN emergency
standby sensing.
Pin 2:
VLS is an internal supply for the level
shift circuit that drives the P-Channel
MOSFET. A capacitor should be placed
between VLS and VIN for bypassing. V LS
is normally 10 V below VIN .
Pin 7:
The SENSE- input monitors the polarity
and level of the input voltage through an
external resistor for ISDN emergency
standby sensing.
Pin 3:
The power supply can be shut down by
pulling ENABLE low.
Pin 4:
D GND is the common return point for
the power and logic portions of the
circuit.
Pin 5:
A GND is the common return point.
REXT and CEXT are directly connected to
this point.
Pin 8:
A 20.5 kΩ resistor connected between
REXT and A GND sets the internal bias
currents including oscillator charge and
discharge currents.
Pin 9:
The oscillator frequency can be
programmed by selecting the value of
the capacitor connected between CEXT
and A GND.
Pin 11:
EA OUT is the error amplifier output
pin for connection to the external
compensation network.
Pin 12:
EA IN is the error amplifier negative
input for connection to the feedback and
compensation networks.
Pin 13:
VS is the internal supply voltage. This
pin is brought out for external bypassing.
Pin 14:
The LEVEL output indicates when the
input voltage is in its normal operating
range.
Pin 15:
The POLARITY output is used to notify
a microprocessor of an emergency
standby condition for ISDN applications.
Pin 10:
VBIAS can be connected to the output 5 V
rail of the converter to reduce power
dissipation. The internal 5 V regulator is
cut off when the output is in regulation.
Pin 16:
OUT is the Drain connection of the PChannel pass transistor.
current for the level shift stage (≈50 µA)
and the AC switching currents for the PChannel output device are drawn from
the VIN supply under this condition. If
unused, VBIAS must be hardwired to A
GND to disable the automatic switchover
during power-up.
UV Lockout
During power-up, the undervoltage
lockout circuit keeps the P-channel
output transistor in the off state until the
internal VS supply is in regulation and
the voltage sensed by the input monitor
circuit is within the normal operation
range (>12 V).
Functional Description
High Voltage Regulator
The high-voltage regulator provides the
bias current required by the controller
and driver circuitry. The pre-regulator
consists of a high voltage MOSFET, a
gate bias current source, and an error
amplifier. The error amplifier regulates
VS to approximately 5 V by controlling
the gate of the MOSFET.
In 5 V output applications, the control
circuitry may also be operated by
connecting the VBIAS pin to the output 5
V rail of the converter to reduce power
dissipation. The internal 5 V regulator is
cut off automatically when the converter
output is in regulation. Only the supply
VLS is the level-shift supply for driving
the gate of the internal P-channel
MOSFET. The voltage at V LS is
approximately 10 V below VIN. VS is the
supply voltage for the controller and
driver circuitry. External bypass
capacitors connected to VLS and VS are
required for filtering and reducing noise.
Band Gap Reference
VREF is the 1.3 V reference voltage
generated by the temperaturecompensated bandgap reference and
buffer. This voltage is used for setting
thresholds for the error amplifier and
over temperature circuit.
D
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3
SMP402
Functional Description (cont.)
Oscillator
The oscillator frequency can be adjusted
by changing the external CEXT capacitor.
This capacitor is charged and discharged
by switched constant current sources.
The voltage switch points are determined
by hysteresis built into a comparator.
The period of the waveform is
determined by values of the current
sources which set the rising and falling
slopes of the sawtooth waveform.
Maximum duty cycle is equal to the ratio
of the charge time to the period. Clock
and blanking signals are synthesized
from the comparator output for use by
the modulator.
Error Amplifier
The error amplifier consists of a high
performance operational amplifier with
the non-inverting input connected to the
internal bandgap reference voltage. The
output of the error amplifier directly
controls the duty cycle of the power
switch.
Pulse Width Modulator
The pulse width modulator implements
a voltage-mode control loop, and
generates the digital driver signal which
controls the power switch. The duty
cycle of the driver signal will change as
a function of input voltage and load.
Increasing the duty cycle causes the
power supply output voltage to go up.
Conversely, decreasing the duty cycle
causes the output voltage to go down.
The pulse width modulator compares
the control voltage (error amplifier
output) with the sawtooth voltage
generated by the oscillator to produce
the required duty cycle.
Thermal Shutdown
Temperature protection is provided by a
precision analog circuit that turns the
power switch off when the junction gets
too hot (typically 140°C). The device
will automatically reset and turn back on
again when the junction has cooled past
the hysteresis temperature level.
SENSE+ and SENSE- Inputs
SENSE+ and SENSE-are both current
mirror inputs consisting of N-channel
MOSFETs connected as diodes. The
threshold voltage of each transistor is
typically 1.7 V. An input current which
exceeds the indicated threshold current
will turn on the mirror transistor for an
active-low signal.
POLARITY and LEVEL Outputs
The LEVEL output is high when the
input current to either SENSE+ or
SENSE- exceeds the LEVEL current
threshold and the output voltage is in
regulation. During normal operation,
the POLARITY output is high when the
input current to SENSE+ is above the
POLARITY current threshold and the
output voltage is in regulation. During
emergency operation (when the DC
input voltage is inverted), the
POLARITY output is low when the input
current to SENSE- exceeds the
48 V
32 V
INPUT
30 V
12 V
10 V
0
-10 V
-32 V
-30 V
-48 V
5 V OUT
LEVEL
POLARITY
5V
0V
5V
0V
5V
0V
PI-960A-032293
Figure 4. Turn-on and Turn-off Waveforms of the SMP402.
4
D
1/96
SMP402
Functional Description (cont.)
POLARITY current threshold.
Regulation of the output voltage is
detected by a comparator which looks
for error amplifier saturation in the output
high (maximum duty cycle) state.
Power supply turn on and turn off with a
slowly changing input voltage is shown
in Figure 4 as measured using the circuit
shown in Figure 6. Also shown are the
level and polarity outputs. The input
voltage must rise above 32 V before the
SMP402 will turn on. At this input
voltage the current through R1 into the
SENSE+ input exceeds the threshold
current (typically 23 µA), the LEVEL
and POLARITY outputs go high, and
the power supply turns on. As the input
voltage goes down, LEVEL will go low
at approximately 30 V, but POLARITY
will stay high. As the input voltage
continues to drop, POLARITY goes low
at approximately 12 V and the converter
loses regulation at approximately 10 V
and turns off. The LEVEL output will
go high and the power supply turns on
when the input voltage reaches -32 V.
POLARITY stays low to indicate that
the input voltage has reversed polarity.
As the negative input voltage falls toward
zero, LEVEL goes low at approximately
-30 V and the converter loses regulation
and turns off at approximately -10 V.
Enable
The power supply can be shut down by
pulling the ENABLE pin low. It is
internally pulled up to VS with a 100 µA
(nominal) current source. However, it is
recommended that this pin be tied to VS
if it is unused.
P-Channel Output Transistor
The output MOSFET is a 90 V pass
transistor capable of supplying >200
mA. To minimize switching noise and
EMI, it is important to keep the path
from OUT through the output diode, the
input storage capacitor, and into VIN as
short as possible.
INPUT VOLTAGE CONDITION
POLARITY
LEVEL
Negative voltage, level too low
0
0
Negative voltage, correct level
0
1
Positive voltage, level too low
1
0
Positive voltage, correct level
1
1
Figure 5. LEVEL/POLARITY Truth Table. The LEVEL and POLARITY signals are only valid when the output voltage is in regulation.
D
1/96
5
SMP402
L1
470 µH
+
VOUT
D2
C1
4X
1N4002
-
D3
C5
100 nF
D4
R1
1.2 MΩ
R2
1.2 MΩ
R7
3.3 MΩ
D6
UF4002
U1
R8
3.3 MΩ
1
2
3
4
5
6
7
8
R3
20.5 kΩ
SMP402SC
INPUT
D1
16
15
14
13
12
11
10
9
R5
75 kΩ
C2
82 µF
C6
100 nF
RTN
POLARITY
LEVEL
C4-1 nF
C3
100 nF
R4
240 kΩ
C11
120 pF
R6
24.9 kΩ
JMP 1
PI-1455-042695
Figure 6. Schematic Diagram of a Non-isolated 5 V, 1 W ISDN Regulator Circuit Utilizing the SMP402.
General Circuit Operation
The Buck DC-to-DC converter shown
in Figure 6 produces a single non-isolated
5 V, 1 W power supply. The highvoltage P-channel MOSFET transistor
in the SMP402 is turned on and off at the
switching frequency. The ratio of ONtime to the switching period is defined as
the duty cycle. The duty cycle changes
with input voltage to maintain a constant
average value of the switching
waveform. The switching waveform is
filtered by inductor L1 and capacitor C2
to produce the 5 V output. During the
MOSFET ON-time, the switch current
and inductor current ramp up at a linear
rate. During the P channel MOSFET
switch off time, the voltage across L1
reverses, forward biasing D6. Inductor
and diode current then ramp down
linearly until the MOSFET turns on
again.
During normal operation,
inductor current ramps up and down
around the average value (IOUT), which is
actually the DC load current.
6
D
1/96
The 5 V output voltage is directly sensed
and accurately regulated by an internal
error amplifier. The error amplifier
generates an error signal which directly
controls the duty cycle of the integrated
high-voltage P-channel MOSFET
switch. The effective output voltage can
be fine-tuned by adjusting the resistor
divider formed by R5 and R6. Other
output voltages are possible (up to
approximately half the input voltage) by
changing the value of L1 as well as the
resistor divider.
Polarity of the DC input voltage can be
either positive or negative. D1, D2, D3,
and D4 “rectify” the DC input voltage to
provide a positive polarity input voltage
for the converter. C1 provides input
voltage filtering. The SMP402 contains
the integrated controller and high-voltage
P-channel MOSFET which, together
with D6, generates a pulse width
modulated switching AC voltage
waveform. L1 and C2 filter the AC
voltage to create the 5 V output. C6
filters high-frequency noise currents. R5
and R6 sense and divide the 5 V output
voltage for comparison with the internal
bandgap reference voltage. C4 and R4
provide control loop compensation
feedback around the internal error
amplifier. C3 bypasses the onboard VS
regulator. C11 sets the switching
frequency. R3 is fixed to set internal
currents accurately. C5 bypasses an
internally-generated, level-shifted bias
source of approximately 10 V, which is
referenced to the positive side of the
effective input voltage. This floating
supply is used for biasing the P-channel
MOSFET gate drivers. R1 and R2 sense
the level and polarity of the DC input
voltage. The current through R1 and the
SENSE+ input or R2 and the SENSEinput must exceed 23 µA before the
converter will turn on.
R7 and R8
provide hysteresis for the SENSE+ and
SENSE- inputs. Jumper JMP1 disables
the self-bias feature of the SMP402.
SMP402
General Circuit Operation (cont.)
The line and load regulation graphs were
measured on the circuit shown in Figure
6. The switching frequency of the power
supply was measured at 230 kHz.
The maximum output power curve shows
the power output capability for a 470 µH
output filter inductor (L1).
The output power versus frequency curve
was generated by characterization of the
SMP402 at various frequencies. The
curve demonstrates the trade-off between
AC and DC power losses within the
device. As AC losses rise with frequency,
DC losses and output power must be
reduced to maintain the same device
maximum power dissipation.
Typical Performance Characteristics (Figure 6 Power Supply)
102
101
ILOAD = 200 mA
103
102
40
60
80
100
200
300
400
0
40
30
80
ILOAD = 200 mA
70
40
60
80
OUTPUT POWER vs. FREQUENCY
60
50
2
TA = 25°C
VIN = 48 VDC
1
40
0
30
2
20
Input Voltage (VDC)
Output Power (W)
Output Efficiency (%)
50
Load Power (W)
0
500
EFFICIENCY vs. INPUT VOLTAGE
PI-950-022593
5 V Output Efficiency (%)
60
1
0.5
Load Current (mA)
VIN = 24 VDC
VIN = 48 VDC
VIN = 72 VDC
0
1.0
VIN = 48 VDC
0
EFFICIENCY vs. OUTPUT POWER
70
1.5
101
Input Voltage (VDC)
80
TA = 25°C
PI-944-022293
20
PI-940-022293
PI-938-022293
104
100
0
2.0
Output Power (W)
103
Output Voltage (% of Nominal)
PI-939A-031393
Output Voltage (% of Nominal)
104
100
MAXIMUM OUTPUT POWER
LOAD REGULATION
105
PI-951-022593
LINE REGULATION
105
0
20
40
60
Input Voltage (VDC)
80
0
100
200
300
400
500
Switching Frequency (kHz)
D
1/96
7
SMP402
ABSOLUTE MAXIMUM RATINGS1
VIN Voltage .................................................................. 80 V
Drain-Source Voltage (V IN to OUT) ........................... 90 V
VBIAS Voltage .............................................................. 5.5 V
SENSE Current .................................................... ±200 µA
OUT Voltage ........................................ VIN + 0.3 V to -4 V
OUT Current ..........................................................250 mA
Logic Input Voltage ........................... -0.3 V to VS + 0.3 V
Storage Temperature ..................................... –65 to 125°C
Operating Junction Temperature(2). ................... 0 to 150°C
Lead Temperature (3). ................................................ 260°C
Power Dissipation ..................................................... 1.0 W
Thermal Impedance (θJA) ...................................... 55°C/W
Thermal Impedance (θJC)(4) .................................... 15°C/W
1.
2.
3.
4.
Unless noted, all voltages referenced to A GND, TA=25˚C
Normally limited by internal circuitry.
1/16" from case for 5 seconds.
Measured at pin 4/5.
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
V IN = 48 V, V BIAS = 5 V, GNDs = 0 V
REXT = 20.5 kΩ, CEXT = 120 pF
RS+, RS- = 1.2 MΩ, T j = 0 to 120°C
Min
Typ
Max
Units
500
kHz
260
kHz
OSCILLATOR
Output
Frequency
fOSC
Initial
Accuracy
∆fOSC
CEXT = 30 to 300 pF
50
200
230
DC
0-50
0-70
VREF
1.22
PULSE WIDTH MODULATOR
Duty
Cycle
%
ERROR AMPLIFIER
Threshold
Voltage
Gain-Bandwidth
Product
DC
Gain
AVOL
Common-mode
Range
VEA IN
Output
Impedance
ZOUT
8
D
1/96
60
See Note 2
1.32
V
0.5
MHz
80
dB
0
3
1
V
kΩ
SMP402
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
VIN = 48 V, VBIAS = 5 V, GNDs = 0 V
REXT = 20.5 kΩ, CEXT = 120 pF
RS+, RS- = 1.2 MΩ, Tj = 0 to 120°C
Min
Typ
Max
Units
120
140
°C
15
°C
CIRCUIT PROTECTION
Thermal Shutdown
Temperature
VIH = 3.0 V
Thermal Shutdown
Hysteresis
VIL = 0 V
LOGIC
Input Current
High
IIH
Input Current
Low
IIL
Input Voltage
High
VIH
Input Voltage
Low
VIL
Output Voltage
High
V OH
IOH = -0.5 mA
Output Voltage
Low
VOL
IOL = 0.5 mA
10
-500
50
µA
µA
-100
3.0
V
1.0
V
3.5
V
0.4
V
1.7
2.2
V
24
27
µA
5
7
µA
SENSE INPUTS
Threshold
Voltage
V SENSE+/-
LEVEL
Threshold Current
ILEVEL
POLARITY
Threshold Current
IPOLARITY
21
OUTPUT
ON-State
Resistance
ON-State
Current
RDS(ON)
ID(ON)
IOUT = -100 mA
Tj = 25°C
12
Tj = 100°C
20
VDS = 5 V
Tj = 25°C
200
500
See Note 1
Tj = 100°C
100
350
Ω
mA
D
1/96
9
SMP402
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
V IN = 48 V, V BIAS = 5 V, GNDs = 0 V
REXT = 20.5 kΩ, CEXT = 120 pF
RS+, RS- = 1.2 MΩ, T j = 0 to 120°C
Min
Typ
-10
Max
Units
OUTPUT (cont.)
OFF-State
Current
IDSS
VIN = 72 V, OUT = 0 V, TA = 120°C
-50
Breakdown
Voltage
BVDSS
IOUT = -250 µA, TA = 25°C
90
µA
V
SUPPLY
HV Regulator
Voltage
VIN
Off-line Supply
Current
IIN
VBIAS Supply
Voltage
VBIAS
VBIAS Supply
Current
IBIAS
12
72
VBIAS = A GND
1.5
2.5
VBIAS = 5 V
1
1.5
4.75
1
V
mA
5.25
V
1.5
mA
NOTES:
1. At low output currents (< 20 mA), the part may operate in blocking oscillation mode, resulting in large output ripple.
2. Applying >3.5 V to the EA IN pin activates an internal test circuit that turns on the output switch continuously.
Destruction of the part can occur if the output of the SMP402 is connected to a high voltage power source when the
test circuit is activated.
470 µH
100 nF
C1
75 kΩ
82 µF
48 VDC
R1
1.2 MΩ
1.2 MΩ
1
2
3
4
5
6
7
8
20.5 kΩ
SMP402SC
U1
100 nF
152 Ω
UF4002
16
15
14
13
12
11
10
9
120 pF
1 nF
240 kΩ
100 nF
24.9 kΩ
PI-1456-042695
Figure 7. Switching Time Test Circuit.
10
D
1/96
SMP402
fPWM vs. EXTERNAL CAPACITANCE
BREAKDOWN vs. TEMPERATURE
PWM Frequency (kHz)
1.0
0.9
0
25
50
400
300
200
100
0
75 100 125 150
200
400
300
500
External Capacitance (pF)
COSS vs. DRAIN VOLTAGE
DRAIN CHARGE vs. DRAIN VOLTAGE
3.0
PI-1008-051093
100
2.5
Drain Charge (nC)
80
60
40
20
2.0
1.5
1.0
0.5
0
0
20
40
60
80
0
20
Drain Voltage (V)
40
60
80
Drain Voltage (V)
DRAIN CAPACITANCE ENERGY
60
PI-941-022293
0
50
Energy (nJ)
Drain Capacitance (pF)
100
0
Junction Temperature (°C)
PI-942-022293
-50 -25
PI-1011-051793
500
PI-176B-051391
Breakdown Voltage (V)
(Normalized to 25°C)
1.1
40
30
20
10
0
0
20
40
60
80
Drain Voltage (V)
D
1/96
11
SMP402
TRANSIENT THERMAL IMPEDANCE
PACKAGE POWER DERATING
6
4
2
PI-1012-051793
100
Thermal Impedance (°C/W)
Power Dissipation (W)
Tj = 120°C
PI-1013-052093
8
10
1
0.1
0
0
25
50
75
100
-4
125
10
-3
10
-2
10
10
S16A
10
100 1000
Plastic SO-16 (W)
inches
mm
16
A
B
C
E
F
J
L
M
N
1
Time (s)
Case Temperature (°C)
DIM
-1
.398-.413
.050 BSC
.014-.018
.093-.104
.004-.012
.394-.418
.009-.012
.020-.040
.291-.299
9
10.10-10.50
1.27 BSC
0.36-0.46
2.35-2.65
0.10-0.30
10.01-10.62
0.23-0.32
0.51-1.02
7.40-7.60
(3)
N
1
8
(3)
A
Notes:
1. Package dimensions conform to JEDEC
specification MS-013-AA for standard small outline
(SO) package, 16 leads, 7.50 mm (.300 inch) body
width (issue A, June 1985).
2. Controlling dimensions are in mm.
3. Dimensions are for the molded body and do not
include mold flash or protrusions. Mold flash or
protrusions shall not exceed .15 mm (.006 inch) on
any side.
4. Pin 1 side identified by chamfer on top edge of
the package body or indent on Pin 1 end.
J
E
C
B
L
0-8˚ TYP.
F
M
PI-1846-050196
12
D
1/96
SMP402
NOTES
D
1/96
13
SMP402
NOTES
14
D
1/96
SMP402
NOTES
D
1/96
15
SMP402
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.
PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc.
©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086
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USA
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408•523•9200
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Fax:
408•523•9365
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JAPAN
Power Integrations, K.K.
Keihin-Tatemono 1st Bldg.
12-20 Shin-Yokohama 2-Chome, Kohoku-ku,
Yokohama-shi, Kanagawa 222
Japan
Phone: 81•(0)•45•471•1021
Fax:
81•(0)•45•471•3717
ASIA & OCEANIA
For Your Nearest Sales/Rep Office
Please Contact Customer Service
Phone: 408•523•9265
Fax:
408•523•9365
APPLICATIONS HOTLINE
World Wide
408•523•9260
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APPLICATIONS FAX
Americas
408•523•9361
Europe/Africa
44•(0)•1753•622•209
Japan
81•(0)•45•471•3717
Asia/Oceania
408•523•9364