® INT100 Half-Bridge Driver IC Low-Side and High-side Drive with Simultaneous Conduction Lockout Product Highlights 5 V CMOS Compatible Control Inputs • Combines logic inputs for low and high-side drives • Schmidt-triggered inputs for noise immunity Built-in High-voltage Level Shifters • Can withstand up to 800 V for direct interface to the HVreferenced high-side switch • Pulsed internal high-voltage level shifters reduce power consumption Gate Drive Outputs for External MOSFETs • Provides 300 mA sink/150 mA source current • Can drive MOSFET gates at up to 15 V • External MOSFET allows flexibility in design for various motor sizes Built-in Protection Features • Simultaneous conduction lockout protection • Undervoltage lockout HV VDDH HS OUT HS RTN VDD HS IN LS IN LS OUT COM LS RTN INT100 PI-1807-031296 Figure 1. Typical Application Description The INT100 half-bridge driver IC provides gate drive for external low-side and high-side MOSFET switches. The INT100 provides a simple, cost-effective interface between low-voltage control logic and high-voltage loads. The INT100 is designed to be used with rectified 110 V or 220 V supplies. Both highside and low-side switches can be controlled independently from ground-referenced 5 V logic inputs. Built-in protection logic prevents both switches from turning on at the same time and shorting the high voltage supply. Pulsed internal level shifting saves power and provides enhanced noise immunity. The circuit is powered from a nominal 15 V supply to provide adequate gate drive for external N-channel MOSFETs. A floating high-side supply is derived from the low-voltage rail by using a simple bootstrap technique. Applications for the INT100 include motor drives, electronic ballasts, and uninterruptible power supplies. Multiple devices can also be used to implement full-bridge and multi-phase configurations. The INT100 is available in a 16-pin plastic SOIC package. VDD HS IN LS IN COM COM N/C LS RTN LS OUT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C VDDH HS RTN HS RTN HS RTN HS OUT N/C N/C PI-1067-101493 Figure 2. Pin Configuration. ORDERING INFORMATION PART NUMBER PACKAGE OUTLINE ISOLATION VOLTAGE INT100S S16A 800 V June 1996 INT100 VDDH LINEAR REGULATOR UV LOCKOUT DISCRIMINATOR S Q DELAY HS OUT R HS RTN VDD LINEAR REGULATOR UV LOCKOUT PULSE CIRCUIT HS IN DELAY LS OUT LS IN LS RTN COM PI-1083A-013194 Figure 3. Functional Block Diagram of the INT100 2 C 6/96 INT100 Pin Functional Description Pin 1: VDD supplies power to the logic, highside interface, and low-side driver. Pin 2: Active-low logic level input HS IN controls the high-side driver output. Pin 3: Active-high logic level input LS IN controls the low-side driver output. Pin 4, 5: COM connection is used as the analog reference point for the circuit. Pin 7: LS RTN is the power reference point for the low-side circuitry, and should be connected to the source of the low-side MOSFET and to the COM pin. Pin 12,13,14: HS RTN is the power reference point for the high-side circuitry, and should be connected to the source of the high-side MOSFET. Pin 8: LS OUT is the driver output which controls the low-side MOSFET. Pin 15: VDDH supplies power to the high-side control logic and output driver. This is normally connected to a high-side referenced bootstrap circuit or can be supplied from a separate floating power supply. Pin 11: HS OUT is the driver output which controls the high-side MOSFET. INT100 Functional Description 5 V Regulators Both low-side and high-side driver circuits incorporate a 5 V linear regulator circuit. The low-side regulator provides the supply voltage for the control logic and high-voltage level shift circuit. This allows HS IN and LS IN to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply. The high-side regulator provides the supply voltage for the noise rejection circuitry and high-side control logic. Undervoltage Lockout The undervoltage lockout circuit for the low-side driver disables both the LS OUT and HS OUT pins whenever the VDD power supply falls below typically 9.0 V, and maintains this condition until the V DD power supply rises above typically 9.35 V. This guarantees that both MOSFETs will remain off during power-up or fault conditions. The undervoltage lockout circuit for the high-side driver disables the HS OUT pin whenever the VDDH power supply falls below typically 9.0 V, and maintains this condition until the VDDH power supply rises above typically 9.35 V. This guarantees that the high-side MOSFET will be off during power-up or fault conditions. Level Shift The level shift control circuitry of the low-side driver is connected to integrated high-voltage N-channel MOSFET transistors which perform the levelshifting function for communication to the high-side driver. Controlled current capability allows the drain voltage to float with the high-side driver. Two individual channels produce a true differential communication channel for accurately controlling the high-side driver in the presence of fast moving high-voltage waveforms. The high voltage level shift transistors employed exhibit very low output capacitance, minimizing the displacement currents between the low-side and high-side drivers during fast moving voltage transients created during switching of the external MOSFETs. As a result, power dissipation is minimized and noise immunity optimized. signals. These signals are used by the discriminator to reject spurious noise. The combination of differential communication with the precise timing provides maximum immunity to noise. Simultaneous Conduction Lockout A latch prevents the low-side driver and high-side driver from being on at the same time, regardless of the input signals. Delay Circuit The delay circuit matches the low-side propagation delay with the combination of the pulse circuit, high voltage level shift, and high-side driver propagation delays. This ensures that the low-side driver and high-side driver will never be on at the same time during switching transitions in either direction. Driver The CMOS drive circuitry on both lowside and high-side driver ICs provide drive power to the gates of the external MOSFETs. The drivers consist of a CMOS buffer capable of driving external transistor gates at up to 15 V. The pulse circuit provides the two highvoltage level shifters with precise timing C 6/96 3 INT100 HV+ D1 C2 VDD HS IN LS IN C1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 INT100 Q2 PHASE 2 PHASE 1 R2 PHASE 3 Q1 R1 HVPI-1458-042695 Figure 4. Using the INT100 in a 3-phase Configuration. PI-1663-112095 Switching Frequncy (kHz) 400 300 200 100 VIN = 200 V VIN = 300 V VIN = 400 V 0 0 100 200 Gate Charge (nC) Figure 5. Gate Charge versus Switching Frequency. 4 C 6/96 INT100 General Circuit Operation One phase of a three-phase motor drive circuit is shown in Figure 4 to illustrate an application of the INT100. The LS IN signal directly controls MOSFET Q1. The HS IN signal controls MOSFET Q2 via the high voltage level shift transistors communicating with the highside driver. The INT100 will ignore input signals that would command both Q1 and Q2 to conduct simultaneously, protecting against shorting the HV+ bus to HV-. observed. The order of signal application should be VDD, logic signals, and then HV+. VDD should be supplied from a low impedance voltage source. The output returns (HS RTN and LS RTN) are isolated from one another by the internal high-voltage MOSFET level shifters. The level shift circuitry is designed to operate properly even when the HS RTN swings as much as 5 V below the LS RTN pin with VDDH biased at 15 V. The INT100 will also safely tolerate more negative voltages (as low as -VDDH below LS RTN). Local bypassing for the low-side driver is provided by C1. Bootstrap bias for the high-side driver is provided by D1 and C2. Slew rate and effects of parasitic oscillations in the load waveforms are controlled by resistors R1 and R2. Maximum frequency of operation is limited by power dissipation due to highvoltage switching, gate charge, and bias power. Figure 5 indicates the maximum switching frequency as a function of input voltage and gate charge. For higher ambient temperatures, the switching frequency should be derated linearly. The inputs are designed to be compatible with 5 V CMOS logic levels and should not be connected to VDD. Normal CMOS power supply sequencing should be The bootstrap capacitor must be large enough to provide bias current over the entire on-time of the high-side driver without significant voltage sag or decay. The high-side MOSFET gate charge must also be supplied at the desired switching frequency. Figure 6 shows the maximum high-side on-time versus gate charge of the external MOSFET. Applications with extremely long highside on times require special techniques discussed in AN-10. The high-side driver is latched on and off by the edges of the appropriate lowside logic signal. The high-side driver will latch off and stay off if the bootstrap capacitor discharges below the undervoltage lockout threshold. Undervoltage lockout-induced turn off can occur during conditions such as power ramp up, motor start, or low speed operation. CBOOTSTRAP vs. ON TIME PI-566B-030692 Bootstrap Capacitance (µF) 1000 100 10 1 QG = 100 nC 0.1 0.01 0.01 QG = 20 nC 0.1 1 10 100 High Side On Time (ms) Figure 6. High-side On Time versus Bootstrap Capacitor. C 6/96 5 INT100 ABSOLUTE MAXIMUM RATINGS1 VDD Voltage ................................................................ 16.5 V VDDH Voltage ........................................... HS RTN + 16.5 V HS RTN ............................................. 800 V - VDDH to -VDDH HS RTN Slew Rate ................................................... 10V/ns Logic Input Voltage ...................................... -0.3V to 5.5 V LS OUT Voltage ................ LS RTN - 0.3 V to VDD + 0.3 V HS OUT Voltage .............. HS RTN - 0.3 V to VDDH + 0.3 V Storage Temperature ....................................... –65 to 125°C Ambient Temperature ........................................ -40 to 85°C Junction Temperature ................................................. 150°C Lead Temperature(2). ................................................... 260°C Power Dissipation (TA = 25°C).................................. 2.3 W (TA = 70°C).................................. 1.5 W Thermal Impedance (θJA) ......................................... 55°C/W 1. Unless noted, all voltages referenced to COM, TA = 25°C 2. 1/16" from case for 5 seconds. Conditions Parameter Symbol (Unless Otherwise Specified) VDDH = VDD = 15 V HS RTN = LS RTN = COM = 0 V TA = -40 to 85°C Min Typ Max V IH = 4.0 V 0 10 150 V IL = 1.0 V -20 0 20 Units LOGIC Input Current, High or Low IIH, IIL Input Voltage High VIH Input Voltage Low V IL Input Voltage Hysteresis V HY 4.0 V 1.0 0.3 µA 0.7 V V LS OUT/HS OUT Output Voltage High VOH Io= -20 mA Output Voltage Low VOL Io= 40 mA Output Short Circuit Current IOS See Note 1 Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time 6 C 6/96 td(on)LS td(on)HS tr td(off)LS td(off)HS tf See Figure 7 LS OUT VDD-1.0 VDD-0.5 0.3 Vo= 0 V -150 Vo= 15 V 300 See Figure 7 1.0 V mA LS OUT 0.6 1.0 HS OUT 1.0 1.5 80 120 LS OUT 500 1000 HS OUT 420 600 50 100 See Figure 7 See Figure 7 V HS OUT VDDH-1.0 VDDH-0.5 µs ns ns ns INT100 Conditions Parameter (Unless Otherwise Specified) VDDH = VDD = 15 V HS RTN = LS RTN = COM = 0 V TA = -40 to 85°C Symbol Min Typ Max Units LEVEL SHIFT Breakdown Voltage BVDSS VDDH = HS OUT = HS RTN IHS RTN = 100 µA Leakage Current IHS RTN) VDDH = HS OUT = HS RTN = 500 V 0.2 VDDH = HS OUT = HS RTN = 500 V 20 pF Interface Capacitance V 800 30 µA SYSTEM RESPONSE Deadtime (Low Off to High On) DtP+ See Figure 7 0 450 ns Deadtime (High Off to Low On) DtP- See Figure 7 0 300 ns 8.5 9.0 175 350 UNDERVOLTAGE LOCKOUT Input UV Trip-off Voltage VDD(UV) V DDH(UV) Input UV Hysteresis 10 V mV SUPPLY Supply Current IDD, IDDH Supply Voltage VDD, VDDH See Note 2 1.5 10 3.0 mA 16 V NOTES: 1. Applying a short circuit to the LS OUT or HS OUT pin for more than 500 µs will exceed the thermal rating of the package, resulting in destruction of the part. 2. VDD, VDDH supply must have less than 30Ω output impedance. C 6/96 7 INT100 5V 50% INPUT 50% 50% 0V td(off)LS 15 V td(on)LS 1 2 3 4 5 6 7 8 INPUT INT100 tf 16 15 14 13 12 11 10 9 15 V 1 µF 100 nF LS OUT tr 90% 90% 50% 50% 10% 0V 10% Dtptd(off)HS Dtp+ td(on)HS CL 1000 pF CL 1000 pF tf 15 V tr 90% 90% 50% HS OUT 50% 10% 0V 10% PI-1459-042695 Figure 7. Switching Time/Deadtime Test Circuit. BREAKDOWN vs. TEMPERATURE 1.0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (°C) C 6/96 PI-1808-032096 2.0 1.5 1 0.5 0 0.9 8 2.5 Power Dissipation (W) PI-176B-051391 Breakdown Voltage (V) (Normalized to 25°C) 1.1 PACKAGE POWER DERATING 0 25 50 75 100 125 Junction Temperature (°C) 150 INT100 S16A DIM Plastic SO-16 (W) inches mm 16 A B C E F J L M N .398-.413 .050 BSC .014-.018 .093-.104 .004-.012 .394-.418 .009-.012 .020-.040 .291-.299 9 10.10-10.50 1.27 BSC 0.36-0.46 2.35-2.65 0.10-0.30 10.01-10.62 0.23-0.32 0.51-1.02 7.40-7.60 (3) N 1 8 (3) A Notes: 1. Package dimensions conform to JEDEC specification MS-013-AA for standard small outline (SO) package, 16 leads, 7.50 mm (.300 inch) body width (issue A, June 1985). 2. Controlling dimensions are in mm. 3. Dimensions are for the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .15 mm (.006 inch) on any side. 4. Pin 1 side identified by chamfer on top edge of the package body or indent on Pin 1 end. J E C B L 0-8˚ TYP. F M PI-1846-050196 C 6/96 9 INT100 Notes 10 C 6/96 INT100 Notes C 6/96 11 INT100 Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc. ©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086 WORLD HEADQUARTERS Power Integrations, Inc. 477 N. Mathilda Avenue Sunnyvale, CA 94086 USA Main: 408•523•9200 Customer Service: Phone: 408•523•9265 Fax: 408•523•9365 AMERICAS For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: 408•523•9265 Fax: 408•523•9365 EUROPE & AFRICA Power Integrations (Europe) Ltd. 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