® INT200 Low-side Driver IC Low-side Drive and High-side Control with Simultaneous Conduction Lockout Product Highlights 5 V CMOS Compatible Control Inputs • Combines logic inputs for low and high-side drives • Schmidt-triggered inputs for noise immunity Built-in High-voltage Level Shifters • Integrated level shifters simplify high-side interface • Can withstand up to 800 V for direct interface to the INT201 high-side driver • Pulsed high-voltage level shifters reduce power consumption HV INT201 VDD HS IN INT200 Gate Drive Output for an External MOSFET • Provides 300 mA sink/150 mA source current • Can drive MOSFET gate at up to 15 V • External MOSFET allows flexibility in design for various motor sizes Built-in Protection Features • Simultaneous conduction lockout protection • UV lockout 3-PHASE BRUSHLESS DC MOTOR LS IN PI-11762-012396 Figure 1. Typical Application Description HS IN 1 8 VDD The INT200 Low-side driver IC provides gate drive for an external low-side MOSFET switch and high-side level shifting. When used in conjunction with the INT201 high-side driver, the INT200 provides a simple, cost-effective interface between low-voltage control logic and high-voltage loads. The INT200 is designed to be used with rectified 110 V or 220 V supplies. Both high-side and low-side switches can be controlled independently from ground-referenced 5 V logic inputs on the low side driver. LS IN 2 7 N/C Built-in protection logic prevents both switches from turning on at the same time and shorting the high voltage supply. Pulsed level shifting saves power and provides enhanced noise immunity. The circuit is powered from a nominal 15 V supply to provide adequate gate drive for external N-channel MOSFETs. Applications include motor drives, electronic ballasts, and uninterruptible power supplies. The INT200 can also be used to implement full- bridge and multi-phase configurations. The INT200 is available in 8-pin plastic DIP and SOIC packages. LS OUT 3 6 HSD1 COM 4 5 HSD2 PI–284C–072291 Figure 2. Pin Configuration. ORDERING INFORMATION PART NUMBER PACKAGE OUTLINE ISOLATION VOLTAGE INT200PFI1 P08A 600 V INT200TFI1 T08A 600 V INT200PFI2 P08A 800 V INT200TFI2 T08A 800 V January 1996 INT200 Pin Functional Description Pin 1: Active-low logic-level input HS IN controls the pulse circuit which signals the INT201 high-side driver. Pin 2: Active-high logic level input LS IN controls the low side driver output. Pin 4: COM connection; analog reference point for the circuit. Pin 5: Level shift output HSD 2 signals the high-side driver to turn off. One short, precise pulse is sent on each positive transition of HS IN. Pin 3: LS OUT is the driver output which controls the low-side MOSFET. Pin 6: Level shift output HSD 1 signals the high-side driver to turn on. Two short, precise pulses are sent on each negative transition of HS IN. Pin 7: N/C for creepage distance. Pin 8: VDD supplies power to the logic, highside interface, and low-side driver. HSD1 VDD HSD2 LINEAR REGULATOR UV LOCKOUT PULSE CIRCUIT HS IN DELAY LS OUT LS IN COM PI-286F-043093 Figure 3. Functional Block Diagram of the INT200 2 F 1/96 INT200 INT200 Functional Description 5 V Regulator The 5 V linear regulator circuit provides the supply voltage for the control logic and high-voltage level shift circuit. This allows the logic section to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply. Undervoltage Lockout The undervoltage lockout circuit disables the LS OUT pin and both HSD pins whenever the VDD power supply falls below typically 9.0 V, and maintains this condition until the VDD power supply rises above typically 9.35 V. This guarantees that both MOSFETs will remain off during power-up or fault conditions. HSD1/HSD2 The HSD1 and HSD2 outputs are connected to integrated high-voltage Nchannel MOSFET transistors which perform the level-shifting function for communication to the high-side driver. Controlled current capability allows the drain voltage to float with the high-side driver. Two individual channels produce a true differential communication channel for accurately controlling the high-side driver in the presence of fast moving high-voltage waveforms. Pulse Circuit The pulse circuit provides the two highvoltage level shifters with precise timing signals. Two pulses are sent over HSD1 to signal the high-side driver to turn on. One pulse is sent over HSD2 to signal the high-side driver to turn off. The combination of differential communication with the precise timing provides maximum immunity to noise. Conduction Latch An RS latch prevents the low-side driver and high-side driver from being on at the same time, regardless of the input signals. . Delay Circuit The delay circuit matches the low-side propagation delay with the combination of the pulse circuit, high voltage level shift, and high-side driver propagation delays. This ensures that the low-side driver and high-side driver will never be on at the same time during switching transitions in either direction. Driver The CMOS drive circuit provides drive power to the gate of the MOSFET used on the low side of the half bridge circuit. The driver consists of a CMOS buffer capable of driving an external transistor gate at up to 15 V. HV+ 8 7 6 5 R2 Q2 PHASE 2 C2 INT201 D1 1 2 3 4 PHASE 1 VDD 8 6 5 INT200 C1 HS IN 7 1 2 3 PHASE 3 Q1 4 R1 3-PHASE BRUSHLESS DC MOTOR LS IN HVPI-1461-042695 Figure 4. Using the INT200 and INT201 in a 3-phase Configuration. F 1/96 3 INT200 General Circuit Operation 400 Switching Frequncy (kHz) PDIP Local bypassing for the low-side driver is provided by C1. Bootstrap bias for the high-side driver is provided by D1 and C2. Slew rate and effects of parasitic oscillations in the load waveforms are controlled by resistors R1 and R2. The inputs are designed to be compatible with 5 V CMOS logic levels and should not be connected to VDD. Normal CMOS power supply sequencing should be observed. The order of signal application VIN = 200 V VIN = 300 V VIN = 400 V 300 PI-1782-020696 The length of time that the high-side can remain on is limited by the size of the bootstrap capacitor. Applications with extremely long high-side on times require special techniques discussed in AN-10. 200 100 0 Maximum frequency of operation is limited by power dissipation due to highvoltage switching, gate charge, and bias power. Figure 5 indicates the maximum switching frequency as a function of input voltage and gate charge. For higher ambient temperatures, the switching frequency should be derated linearly. 400 SOIC VIN = 200 V VIN = 300 V VIN = 400 V 300 PI-1785-020696 should be VDD, logic signals, and then HV+. VDD should be supplied from a low impedance voltage source. Switching Frequncy (kHz) One phase of a three-phase brushless DC motor drive circuit is shown in Figure 4 to illustrate an application of the INT200/201. The LS IN signal directly controls MOSFET Q1. The HS IN signal causes the INT200 to command the INT201 to turn MOSFET Q2 on or off as required. The INT200 will ignore input signals that would command both Q1 and Q2 to conduct simultaneously, protecting against shorting the HV+ bus to HV-. 200 100 0 0 100 200 Gate Charge (nC) 0 100 200 Gate Charge (nC) Figure 5. Switching Frequency versus Gate Charge for a) PDIP and b) SOIC. HV+ 8 7 6 5 INT201 1 2 3 4 8 7 6 5 FLUORESCENT LAMP VDD INT200 HV1 2 3 4 OSCILLATOR PI-1462-042695 Figure 6. Using the INT200 and INT201 to Drive a Fluorescent Lamp. 4 F 1/96 INT200 ABSOLUTE MAXIMUM RATINGS1 HSD1/HSD2 Voltage (1 Suffix) ................................. 600 V (2 Suffix) ................................. 800 V HSD1/HSD2 Slew Rate ........................................... 10 V/ns VDD Voltage ................................................................ 16.5 V Logic Input Voltage ...................................... -0.3V to 5.5 V LS OUT Voltage ................................ -0.3 V to V DD + 0.3 V Storage Temperature ....................................... –65 to 125°C Ambient Temperature ........................................ -40 to 85°C Junction Temperature ................................................. 150°C Lead Temperature(2).................................................... 260°C Power Dissipation PF Suffix (TA = 25°C) ......................................... 1.25 W (TA = 70°C) ....................................... 800 mW TF Suffix (TA = 25°C) ......................................... 1.04 W (TA = 70°C) ....................................... 667 mW Thermal Impedance (θJA) PF Suffix ........................................................... 100°C/W TF Suffix ........................................................... 120°C/W 1. Unless noted, all voltages referenced to COM, TA = 25°C 2. 1/16" from case for 5 seconds. Conditions Parameter Symbol (Unless Otherwise Specified) VDD = 15 V, COM = 0V TA = -40 to 85°C Min Typ Max V IH = 4.0 V 0 10 150 V IL = 1.0 V -20 0 20 Units LOGIC Input Current, High or Low IIH, IIL Input Voltage High VIH Input Voltage Low VIL Input Voltage Hysteresis V HY µA 4.0 V 1.0 0.3 0.7 V V HSD OUTPUTS Breakdown Voltage 1 Suffix 600 700 BVDSS 2 Suffix 800 900 Off-State Output Current IHSD(OFF) V HSD1, VHSD2 = 500 V On-State Output Current IHSD(ON) VHSD1, VHSD2 = 10 V On-State Pulse Width tHSD(ON) Output Capacitance COSS 0.1 5 V 15 25 µA mA 156 VHSD1, VHSD2 = 25 V 10 ns pF F 1/96 5 INT200 Conditions Parameter Symbol (Unless Otherwise Specified) VDD = 15 V, COM = 0V T A = -40 to 85°C Output Voltage High VOH Io= -20 mA Output Voltage Low VOL Io= 40 mA Output Short Circuit Current IOS Turn-on Delay Time td(on) See Figure 7 0.6 1.0 µs tr See Figure 7 80 120 ns td(off) See Figure 7 0.5 1 µs tf See Figure 7 50 100 ns Deadtime (Low Off to High On) DtP+ See Figure 8 0 450 ns Deadtime (High Off to Low On) DtP- See Figure 8 0 300 ns 8.5 9.0 175 350 Min Typ Max Units LS OUT Rise Time Turn-off Delay Time Fall Time See Note 1 V VDD-1.0 VDD-0.5 0.3 V o= 0V V o= VDD 1.0 -150 300 V mA SYSTEM RESPONSE UNDERVOLTAGE LOCKOUT Input UV Trip-off Voltage VDD(UV) Input UV Hysteresis 10 V mV SUPPLY Supply Current IDD Supply Voltage VDD 6 F 1/96 See Figure 2 1.5 10 3.0 mA 16 V INT200 NOTES: 1. Applying a short circuit to the LS OUT pin for more than 500 µs will exceed the thermal rating of the package, resulting in destruction of the part. 2. VDD supply must have less than 30 Ω output impedance. 15 V 5V INPUT 1 8 2 7 INPUT INT200 1 µF 3 CL 1000 pF 0.1 µF 50% 0V td(off) td(on) 6 tr tf 15 V 4 50% 90% 5 90% LS OUT 10% 10% 0V PI-1463-042695 Figure 7. Switching Time Test Circuit. 5V 8 7 6 5 INPUT 0V INT201 1000 pF 1 2 3 4 8 7 6 5 15 V LS OUT 15 V 47 µF 35 V 50% 50% 0V Dtp- INT200 0.1 µF 15 V 1 2 3 1000 pF 4 HS OUT Dtp+ 50% 50% 0V PI-1465-042695 Figure 8. Dead Time Test Circuit. F 1/96 7 INT200 BREAKDOWN vs. TEMPERATURE PACKAGE POWER DERATING 1.0 0.9 0 25 50 75 100 125 150 Junction Temperature (°C) F 1/96 PI-1763-013196 PF Suffix 1.0 TF Suffix 0.5 0 -50 -25 8 1.5 Power Dissipation (W) PI-176B-051391 Breakdown Voltage (V) (Normalized to 25°C) 1.1 0 25 50 75 100 125 Junction Temperature (°C) 150 INT200 P08A Plastic DIP-8 Dim. inches mm A B C D E F G H .395 MAX .090-.110 .015-.021 .040 TYP .015-.030 .125 MIN .015 MIN .125-.135 10.03 MAX 2.29-2.79 0.38-0.53 1.02 TYP 0.38-0.76 3.18 MIN 0.38 MIN 3.18-3.43 J K L .300-.320 .245-.255 .009-.015 7.62-8.13 6.22-6.48 0.23-0.38 8 5 Note 5 1 4 A J (3) D Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB for standard dual inline (DIP) package .300 inch row spacing (PLASTIC) 8 leads (issue B, 7/85). 2. Controlling dimensions: inches. 3. Dimensions are for the molded body and do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .010 inch (.25 mm) on any side. 4. These dimensions measured with the leads constrained to be perpendicular to package bottom. 5. Pin 1 orientation identified by end notch or dot adjacent to Pin 1. (4) K (3) H F G E 0 – 15 ° L C B PI-1842-050196 T08A Plastic SO-8 DIM inches mm A B C D E F G H J K 0.189-0.197 0.050 TYP 0.014-0.019 0.012 TYP 0.053-0.069 0.004-0.010 0.228-0.244 0.007-0.010 0.021-0.045 0.150-0.157 4.80-5.00 1.27 TYP 0.35-0.49 0.31 TYP 1.35-1.75 0.10-0.25 5.80-6.20 0.19-0.25 0.51-1.14 3.80-4.00 8 5 K 1 Notes: 1. Package dimensions conform to JEDEC specification MS-012-AA for standard small outline (SO) package, 8 leads, 3.75 mm (.150 inch) body width (issue A, June 1985). 2. Controlling dimensions are in mm. 3. Dimensions are for the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .15 mm (.006 inch) on any side. 4. Pin 1 side identified edge by chamfer on top of the package body or indent on Pin 1 end. 4 (3) A G E D B C (3) H F J 0-8˚ TYP. PI-1845-050196 F 1/96 9 INT200 Notes 10 F 1/96 INT200 Notes F 1/96 11 INT200 Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc. ©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086 WORLD HEADQUARTERS Power Integrations, Inc. 477 N. Mathilda Avenue Sunnyvale, CA 94086 USA Main: 408•523•9200 Customer Service: Phone: 408•523•9265 Fax: 408•523•9365 AMERICAS For Your Nearest Sales/Rep Office Please Contact Customer Service Phone: 408•523•9265 Fax: 408•523•9365 EUROPE & AFRICA Power Integrations (Europe) Ltd. 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