SCDS060F − MARCH 1998 − REVISED OCTOBER 2003
D 4-Ω Switch Connection Between Two Ports
D Rail-to-Rail Switching on Data I/O Ports
D Ioff Supports Partial-Power-Down Mode
1A
2B1
2B2
3A
4B1
4B2
5A
6B1
6B2
7A
8B1
8B2
GND
VCC
9A
10B1
10B2
11A
12B1
12B2
13A
14B1
14B2
15A
16B1
16B2
17A
18B1
18B2
GND
T0
T1
Operation
Break-Before-Make Feature
description/ordering information
The SN74CBTLV16235 is an 18-bit 1-of-2 FET
multiplexer/demultiplexer used in applications in
which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
path. This device can be used for memory
interleaving, where two different banks of memory
need to be addressed simultaneously.
The device is organized as a dual 9-bit 1-of-2
multiplexer/demultiplexer with separate control
inputs. It can be used as two 9-bit
multiplexers/demultiplexers or as one 18-bit
multiplexer/demultiplexer. Two select (S0 and S1)
inputs control the data flow. When the test (T0 and
T1) inputs are asserted, port A is connected to
both ports B1 and B2. The control inputs can be
driven with a low-voltage TTL or an SSTL_3
driver.
The SN74CBTLV16235 is specified by the
break-before-make design to have no through
current when switching directions.
This
device
is
fully
specified
for
partial-power-down applications using Ioff. The Ioff
feature ensures that damaging current will not
backflow through the device when it is powered
down. The device has isolation during power off.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
1B1
1B2
2A
3B1
3B2
4A
5B1
5B2
6A
7B1
7B2
8A
GND
VCC
9B1
9B2
10A
11B1
11B2
12A
13B1
13B2
14A
15B1
15B2
16A
17B1
17B2
18A
GND
S0
S1
PRODUCT PREVIEW
D
DGG PACKAGE
(TOP VIEW)
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − DGG Tape and reel
SN74CBTLV16235GR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&'#! (#!()$!* +$#,-('* ! '.) "#$%&'/) #$
,)*0! +.&*) #" ,)/)1#+%)!'2 .&$&(')$*'( ,&'& &!, #'.)$
*+)("(&'#!* &$) ,)*0! 0#&1*2 )3&* !*'$-%)!'* $)*)$/)* '.) $0.' '#
(.&!0) #$ ,*(#!'!-) '.)*) +$#,-('* 4'.#-' !#'()2
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1
SCDS060F − MARCH 1998 − REVISED OCTOBER 2003
FUNCTION TABLE
(each 9-bit multiplexer/demultiplexer)
INPUTS
FUNCTION
T
S
L
L
L
H
A port = B2 port
H
X
A port = B1 port = B2 port
A port = B1 port
logic diagram (positive logic)
1
1A
64
SW
1B1
SW
15
PRODUCT PREVIEW
9A
63
1B2
50
SW
9B1
SW
49
9B2
34
S0
31
T0
48
10A
16
SW
10B1
SW
36
18A
18B1
33
S1
32
T1
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10B2
28
SW
SW
2
17
• DALLAS, TEXAS 75265
29
18B2
SCDS060F − MARCH 1998 − REVISED OCTOBER 2003
simplified schematic, each FET switch
A
B
(OE)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
2.3
3.6
UNIT
V
1.7
V
2
0.7
0.8
V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
PRODUCT PREVIEW
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
SCDS060F − MARCH 1998 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
II
VCC = 3 V,
VCC = 3.6 V,
II = −18 mA
VI = VCC or GND
Ioff
ICC
VCC = 0,
VCC = 3.6 V,
VI or VO = 0 to 3.6 V
IO = 0,
VI = VCC or GND
One input at 3 V,
Other inputs at VCC or GND
∆ICC‡
Control input
Ci
Control input
VCC = 3.6 V,
VI = 3 V or 0
TYP†
MAX
UNIT
−1.2
V
±5
µA
10
µA
10
µA
300
µA
pF
A port
Cio(OFF)
B port
VO = 3 V or 0
pF
VCC = 2.3 V,
TYP at VCC = 2.5 V
ron§
PRODUCT PREVIEW
VCC = 3 V
VI = 0
II = 64 mA
II = 24 mA
VI = 1.7 V,
II = 15 mA
VI = 0
II = 64 mA
II = 24 mA
Ω
VI = 2.4 V,
II = 15 mA
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
ns
ten
tdis
S
A or B
ns
S
A or B
ns
ten
tdis
T
A or B
ns
T
A or B
PARAMETER
MIN
MAX
MIN
UNIT
MAX
ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
4
POST OFFICE BOX 655303
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SCDS060F − MARCH 1998 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
RL
From Output
Under Test
S1
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
2.5 V ±0.2 V
3.3 V ±0.3 V
30 pF
50 pF
500 Ω
500 Ω
0.15 V
0.3 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
PRODUCT PREVIEW
VCC/2
Input
th
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74CBTLV16235GR
PREVIEW
TSSOP
DGG
Pins Package Eco Plan (2)
Qty
64
2000
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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