Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Description PT6880 is an OLED Driver/Controller IC utilizing CMOS Technology specially designed to display alphanumeric and Japanese kana characters as well as symbols and graphics. It can interface with either 4-bit or 8-bit Microprocessor and display up to one 8-character line or two 8-character lines. Display RAM, Character Generator, OLED Driver as well as a wide range of instruction functions such as Display Clear, Cursor Home, Display ON/OFF, Cursor ON/OFF, Display Character Blink, Cursor Shift, Display Shift are all incorporated into a single chip having the highest performance and reliability. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages. Features CMOS Technology Low Power Consumption 4-Bit or 8-Bit MPU Interface High Speed MPU Interface: 2MHz (VDD =5V) 80 x 8-Bit Display RAM (80 characters max.) Auto Reset Function 5 x 8 and 5 x 10 Dot Matrix Built-in Oscillator with External Resistors Programmable Duty Cycle: - 1/8 Duty: (1 Display Line, 5 x 8 Dots with Cursor) - 1/11 Duty: (1 Display Line, 5 x 10 Dots with Cursor) - 1/16 Duty: (2 Display Lines, 5 x 8 Dots with Cursor) 9920-Bit Character Generator ROM (CGROM) - 208 Character Fonts (5 x 8 dot matrix) - 32 Character Fonts (5 x 10 dot matrix) 64 x 8-Bit Character Generator RAM (CGRAM) - 8 Character Fonts (5 x 8 dot matrix) - 4 Character Fonts ( 5 x 10 dot matrix) 16 Common x 40 Segment OLED Drivers Available in C.O.B. or QFP Package PT6880 pre 1.1 Page 1 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Applications Cellular Phone Data Bank/Organizer Electronic Dictionary / Translator Information Appliance P.D.A. P.O.S. Car Audio Electronic Equipment with OLED Display PT6880 pre 1.1 Page 2 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Block Diagram DISB OSC1 RESET CIRCUIT OSC2 CL OSCILLATION CIRCUIT LAT TIMING GENERATOR COM1 16-BIT SHIFT REGISTER RS R/WB MPU INTERFACE 8 COMMON SIGNAL DRIVER COM2 COM15 COM16 INSTRUCTION REGISTER E DB0 DB2 DB3 SG1 INSTRUCTION DECODER DB1 INPUT/ OUTPUT BUFFER DB4 7 DB6 8 DB7 40-BIT SHIFT REGISTER 40-BIT LATCH CIRCUIT SEGMENT SIGNAL DRIVER DISPLAY DATA RAM (DDRAM) 80x8 BITS 7 DB5 SG2 ADDRESS COUNTER SG39 DATA REGISTER SG40 8 8 BUSY FLAG 8 CHARACTER GENERATOR RAM (CGRAM) 64 BYTES 5 CHARACTER GENERATOR ROM (CGROM) 9920 BITS 5 PARALLEL / SERIAL CONVERTER AND ATTRIBUTE CIRCUIT D 40 CURSOR AND BLINK CONTROLLER REFOUT V16 OLED DRIVE VOLTAGE SEGG DVR BVR VDD GND PT6880 pre 1.1 Page 3 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 NC NC NC NC COM13 COM12 COM11 COM10 84 83 82 81 86 85 10 11 12 13 14 15 16 17 18 SG8 30 72 71 70 69 68 67 66 65 64 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS DB7 63 DB6 DB5 DB4 59 58 57 56 55 54 53 52 51 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SEGG REFOUT V16 31 32 33 34 35 36 37 38 39 40 VSS 41 VSS 42 OSC1 43 OSC2 44 BVR 45 DVR 46 NC COM9 NC NC NC NC NC NC COM8 62 61 60 19 20 21 22 23 24 25 26 27 28 29 80 79 78 77 76 75 74 73 DB3 DB2 DB1 DB0 E R/WB NC RS NC D 47 48 49 50 SG9 NC 1 2 3 4 5 6 7 8 9 LAT CL VDD DISB SG29 NC SG28 NC SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 87 SG39 SG40 V16 COM16 COM15 COM14 100 99 98 97 96 95 94 93 92 91 90 89 88 NC SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 Pin Configuration Pin/Pad Description PT6880 pre 1.1 Page 4 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC Pin Name I/O PT6880 Description Pad/Pin No. SG40 ~ SG30 SG29, SG 28 SG27 ~ SG9 SG8 ~ SG1 O Segment Driver Output Pins 89 ~ 99 1,3 5 ~ 23 30 ~ 37 SEGG - OLED Drive Power Supply (0V) 38 REFOUT O Reference Current Output Pin 39 V16 - OLED Drive Power Supply (16V) 40, 88 VSS - Ground Pin (0V) 41, 42, 65 OSC1 I Oscillator Input Pin 43 OSC2 O Oscillator Output Pin 44 BVR I Brightness Control Input Pin 45 DVR I Precharge Time Control Input Pin 46 LAT O Latch Clock Output Pin 47 CL O Shift Clock Output Pin 48 VDD - Power Supply (2.7V to 5.5V) 49 DISB O Reset Signal Output Pin 50 D O Character Pattern Data Output Pin 51 I Register Select Input Pin When this pin is set to "0", it is used as an Instruction Register. When this pin is set to "1", it is used for as the Data Register. 53 R/WB I Read/Write Control Input Pin This pin is used to select either the Write or the Read Operation. If this pin is set to "0", then the Write Function is enabled. If this pin is set to "1", then the Read function is enabled. 55 E I Data Read/Write Start Control Pin 56 I/O Low Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. These 57 ~ 60 RS DB0 ~ DB3 PT6880 pre 1.1 Page 5 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 pins are not used during a 4-bit operation. DB4 ~ DB7 I/O High Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. D7 can be used as a Busy Flag. COM1 ~ COM8 COM9 ~ COM16 O Common Driver Output Pins (see Note 1) NC - No Connection 61 ~ 64 66 ~ 73 80 ~ 87 2, 4, 24 ~ 29, 52, 54, 74 ~ 79, 100 Note: 1. COM1 to COM16 are used as the Common Output Driver Pins. However, when the pins are not in used, the respective common signals are transformed into non-selection waveforms. For example, under a 1/8 Duty Factors, the Common Driver Output Pins -- COM9 to COM16 are not used. Common Driver Output Pins -- COM12 to COM16 are not used during a 1/11 duty factor. Therefore, the common signals represented by aforementioned Unused Common Driver Output Pins are transformed into non-selection waveforms. PT6880 pre 1.1 Page 6 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Functional Description Registers PT6880 provides two types of 8-bit registers, namely: Instruction Register (IR) and Data Register (DR). The register is selected using the RS Pin. When the RS pin is set to "0", the Instruction Register Type is selected. When RS pin is set to "1", the Data Register Type is selected. Please refer to the table below. RS 0 0 1 1 R/WB 0 1 0 1 Operation Instruction Register Write as an Internal Operation. Read Busy Flag (DB7) and Address Counter (DB0 to DB6) Data Register Write as an Internal Operation (DR to DDRAM or CGRAM) Data Register Read as an Internal Operation (DDRAM or CGRAM to DR) INSTRUCTION REGISTER (IR) The Instruction Register is used to store the instruction code (i.e. Display Clear, Cursor Home and others), Display Data RAM (DDRAM) Address, and the Character Generator RAM (CGRAM) Address. Instruction register can only be written from the MPU. DATA REGISTER (DR) The Data Register is used as a temporary storage for data that are going to be written into the DDRAM or CGRAM as well as those data that are going to be read from the DDRAM or CGRAM. BUSY FLAG (BF) The Busy Flag is used to determine whether PT6880 is idle or internally operating. When PT6880 is performing some internal operations, the Busy Flag is set to "1". Under this condition, the no other instruction will not be accepted. When RS Pin is set to "0" and R/WB Pin is set to "1", the Busy Flag will be outputted to the DB7 pin. When PT6880 is idle or has completed its previous internal operation, the Busy Flag is set to "0". The next instruction can now be processed or executed. PT6880 pre 1.1 Page 7 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 ADDRESS COUNTER (AC) The address counter is used to assign the Display Data RAM (DDRAM) Address and the Character Generator RAM (CGRAM) Address. When an Address information is written into the Instruction Register (IR), this Address information is sent from the Instruction Register to the Address Counter. At the same time, the nature of the Address (either CGRAM or DDRAM) is determined by the instruction. After writing into or reading from the DDRAM or CGRAM, the Address Counter is automatically increased or decreased by 1 (for Write or Read Function). It must be noted that when the RS pin is set to "0" and R/WB is set to "1", the contents of the Address Counter are outputted to the pins -- DB0 to DB6. DISPLAY DATA RAM (DDRAM) The Display Data RAM (DDRAM) is used to store the Display Data which is represented as 8-bit character code. The Display Data RAM supports an extended capacity of 80 x 8-bits or 80 characters. The area in the DDRAM which are not used for display can be used as General Data RAM. For more details, please refer to the sections below. The Display Data RAM Address (ADD) is set in the Address Counter as a hexadecimal. High Order Bits Address Counter (hexadecimal ) Low Order Bits AC6 AC5 AC4 AC3 AC2 AC1 AC0 An example of a DDRAM Address = 4E is given below. DDRAM Address: 4E AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0 PT6880 pre 1.1 Page 8 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 1-LINE DISPLAY (N=0) When the number of characters displayed is less than 80, the first character is displayed at the head position. The relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position (digit) DDRAM Address (hexadecimal) 1 2 3 4 …………. 78 79 80 00 01 02 03 …………. 4D 4E 4F For example, when only 8 characters are displayed in one Display Line, the relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position DDRAM Address 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 Shift Left 01 02 03 04 05 06 07 08 Shift Right 4F 00 01 02 03 04 05 06 2-LINE DISPLAY (N=1) Case 1: The Number of Characters displayed is less than 40 x 2 lines When the number of characters displayed is less than 40 x 2 lines, then the first character of the first and second lines are displayed starting from the head. It is important to note that the first line end address and the second line start address are not consecutive. Please refer the figure below. Display Position DDRAM Address (hexadecimal) PT6880 pre 1.1 1 2 3 4 ………. 37 38 39 40 00 01 02 03 ………. 24 25 26 27 40 41 42 43 ………. 64 65 66 67 Page 9 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 To illustrate, for 2-line x 8 characters display, the relationship between the DDRAM address and position of the OLED panel is shown below. Display Position 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 Shift Left 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 Shift Right 27 67 00 40 01 41 02 42 03 43 04 44 05 45 06 46 DDRAM Address Case 2: 16-Character x 2 Lines Display PT6880 can be extended to display 16 characters x 2 lines by using the 40-output extension driver. When there is a Display Shift operation, the DDRAM Address is also shifted. Please refer to the example below. Display Position 1 00 40 2 01 41 3 4 5 6 02 03 04 05 42 43 44 45 PT6880 Display 7 06 46 8 07 47 9 08 48 10 11 12 13 14 15 09 0A 0B 0C 0D 0E 49 4A 4B 4C 4D 4E Extension Driver Display 16 0F 4F Shift Left 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0A 0B 4A 4B 0C 0D 4C 4D 0E 4E 0F 4F 10 50 Shift Right 27 67 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 0A 0B 4A 4B 0C 0D 4C 4D 0E 4E DDRAM Address PT6880 pre 1.1 Page 10 09 49 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Character Generator ROM (CGROM) The Character Generator ROM (CGROM) is used to generate either 5 x 8 dots or 5 x 10 dots character patterns from 8-bit character codes. It can generate up to two hundred eight (208) 5 x 8 dot character patterns and thirty two (32) 5 x 10 dot character patterns. For user-defined character patterns, please contact PTC. CORRESPONDENCE BETWEEN THE CHARACTER CODES AND THE CHARACTER PATTERNS UPPER BITS 0000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 LOWER BITS 0000 CG RAM 1 0001 CG RAM 2 0010 CG RAM 3 0011 CG RAM 4 0100 0101 CG RAM 5 CG RAM 6 0110 CG RAM 7 0111 CG RAM 8 1 1000 1 1 1 1 1 1 1010 1011 CG RAM 3 CG RAM 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1001 1 1 1 1 1 CG RAM 2 1 1 1 1 1 1 1 CG RAM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PT6880 pre 1.1 1 1 1 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 CG RAM 7 CG RAM 8 1 1 1 1110 1 1 1 1 1 1 CG RAM 5 CG RAM 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1101 1 1 1 1100 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Page 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 CHARACTER Generator RAM (CGRAM) The Character Generator RAM (CGRAM) is used to generate either 5 x 8 dot or 5 x 10 dot character patterns. It can generate eight 5 x 8 dot character patterns and four 5 x 10 dot character patterns. The character patterns generated by the CGRAM can be rewritten. User-defined character patterns for the CGRAM is supported. Areas in the CGRAM that are not used for display may be used as the General Data RAM. RELATIONSHIP BETWEEN CGRAM ADDRESS, DDRAM CHARACTER CODE AND CGRAM CHARACTER PATTERNS (FOR 5 X 8 DOT CHARACTER PATTERN) Character Codes (DDRAM Data) 7 6 5 4 3 2 1 0 High Low 0 0 0 0 0 0 Notes: 0 0 0 0 0 0 1. 2. 3. 4. 5. PT6880 pre 1.1 * * * 0 0 1 0 0 1 0 1 1 CGRAM Address 5 4 3 2 1 High 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character Patterns (CGRAM Data) 7 6 5 4 3 2 1 High Low * * * 1 1 1 1 * * * 1 0 0 0 * * * 1 0 0 0 * * * 1 1 1 1 * * * 1 0 1 0 * * * 1 0 0 1 * * * 1 0 0 0 * * * 0 0 0 0 * * * 1 0 0 0 * * * 0 1 0 1 * * * 1 1 1 1 * * * 0 0 1 0 * * * 1 1 1 1 * * * 0 0 1 0 * * * 0 0 1 0 * * * 0 0 0 0 * * * * * * 0 1 0 1 * * * * 0 * * * * 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 Character Pattern 1 Cursor Position Character Pattern 2 Cursor Position * * * * * = Not Relevant The character pattern row positions correspond to the CGRAM data bits -- 0 to 4, where bit 4 is in the left position. Character Code Bits 0 to 2 correspond to the CGRAM Address Bits 3 to 5 (3 bits : 8 types) If the CGRAM Data is set to "1", then the selection is displayed. If the CGRAM is set to "0", there no selection is made. The CGRAM Address Bits 0 to 2 are used to define the character pattern line position. The 8th line is the cursor position and its display is formed by the logical OR with the cursor. The 8th line CGRAM data bits 0 to 4 must be set to "0". If any of the 8th line CGRAM data Page 12 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC 6. PT6880 bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit 3 is not relevant and will not have any effect on the character display. Because of this, the first Character Pattern shown above ( R ) can be displayed when the Character Code is 00H or 08H. RELATIONSHIP BETWEEN CGRAM ADDRESS, DDRAM CHARACTER CODE AND CGRAM CHARACTER PATTERNS (FOR 5 X10 DOT CHARACTER PATTERN) Character Codes (DDRAM Data) 7 6 5 4 3 2 1 0 High Low 0 0 0 0 Notes: 0 0 0 0 1. 2. 3. 4. 5. PT6880 pre 1.1 * * 0 1 0 1 * * 5 4 High 0 1 0 1 CGRAM Address 3 2 1 0 Low Character Patterns (CGRAM Data) 7 6 5 4 3 2 1 0 High Low 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 1 1 1 1 1 1 1 1 0 * * * * * * * 0 0 0 1 0 0 1 0 0 0 0 * * * * * * * 0 0 1 0 0 0 1 0 0 0 0 * * * * * * * 0 0 1 0 0 0 1 0 0 0 0 * * * * * * * 0 0 0 1 1 1 0 0 0 0 0 * * * * * * * 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Character Pattern Cursor Position * = Not Relevant The character pattern row positions correspond to the CGRAM data bits -- 0 to 4, where bit 4 is in the left position. Character Code Bits 1 and 2 correspond to the CGRAM Address Bits -- 4 and 5 respectively (2 bits : 4 types) If the CGRAM Data is set to "1", then the selection is displayed. If the CGRAM is set to "0", there no selection is made. The CGRAM Address Bits 0 to 3 are used to define the character pattern line position. The 11th line is the cursor position and its display is formed by the logical OR with the cursor. Page 13 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC 6. PT6880 The 11th line CGRAM data bits 0 to 4 must be set to "0". If any of the 11th line CGRAM data bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit -- 0 and 3 are not relevant and will not have any effect on the character display. Because of this, the Character Pattern shown above ( P ) can be displayed when the Character Code is 00H, 01H, 08H or 09H. Timing Generation Circuit The timing signals for the internal circuit operations (i.e. DDRAM, CGRAM, and CGROM) are generated by the Timing Generation Circuit. The timing signals for the MPU internal operation and the RAM Read for Display are generated separately in order to prevent one from interfering with the other. This means that, for example, when the data is being written into the DDRAM, there will be no unwanted interference such as flickering in areas other than the display area. OLED Driver Circuit PT6880 provides 16 Common Drivers and 40 Segment Driver Outputs. When a character font and the number of lines to be displayed have been selected, the corresponding Common Drivers output the drive waveform automatically. A non-selection waveform will be outputted by the rest of the Common Drivers. Serial data transmission always begins with the display data character pattern corresponding to the last Display Data RAM (DDRAM) Address. The serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register. Thus, PT6880 drives from the head display. Cursor / Blink Control Circuit The cursor or character blinking is generated by the Cursor / Blink Control Circuit.The cursor or the blinking will appear with the digit located at the Display Data RAM (DDRAM) Address Set in the Address Counter (AC). Address Counter AC6 0 AC5 0 AC4 0 AC3 1 AC2 0 AC1 0 AC0 0 CASE 1: FOR 1-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM PT6880 pre 1.1 Page 14 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Address 08H. Display Position DDRAM Address (hexadecimal) 1 2 3 4 5 6 7 8 9 10 11 00 01 02 03 04 05 06 07 08 09 0A | Cursor Position Note: The cursor or blinking appears when the Address Counter (AC) selects the Character Generator RAM (CGRAM). When the AC selects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position. CASE 2: FOR 2-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM Address 08H. Display Position DDRAM Address (hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A Cursor Position Note: The cursor or blinking appears when the Address Counter (AC) selects the Character Generator RAM (CGRAM). When the AC selects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position. Reset Function INTERNAL RESET CIRCUIT INITIALIZATION When power is turned ON, PT6880 is initialized automatically by an internal reset circuit. The following instructions are executed during the initialization. 1. Display Clear 2. Function Set: DL = "1" : 8-Bit Interface Data N = "0" : 1-Line Display F = "0": 5 x 8 Dot Character Font 3. Display ON/OFF Control: D = "0" : Display OFF PT6880 pre 1.1 Page 15 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC 4. Entry Mode Set: PT6880 C = "0" : Cursor OFF B = "0" : Blinking OFF I/D = "1" : Increment by 1 S = "0" : No Shift The Busy Flag (BF) is in a busy state until the initialization is completed (BF="1"). The busy state will be in effect 10 ms after the VDD rises to 4.5 Volts. Please note that in order for the initialization by internal reset circuit to be successful, the electrical characteristic conditions listed in the Electrical Characteristics Section must be complied with. Otherwise, such initialization must be performed by instruction from the MPU. Instructions PT6880's Instruction Register (IR) and Data Register (DR) are the only registers that can be controlled by the MPU. Prior to the commencement of it internal operation, PT6880 temporarily stores the control information to its Instruction Register (IR) and Data Register (DR) in order to easily facilitate interface with various types of MPU. The internal operation of the PT6880 are determined by the signals (RS, R/WB, DB0 to DB7) that are sent from the MPU. These signals are categorized into 4 instructions types, namely: 1. 2. 3. 4. Function Setting Instructions (i.e. Display, Format, Data Length etc.) Internal RAM Address Setting Instructions Data Transfer with Internal RAM Instructions Miscellaneous Function Instructions The generally used instructions are those that execute data transfers with the internal RAM. However, when the internal RAM addresses are auto incremented/decremented by 1 after each Data Write, the program load of the MPU is lightened. The Display Shift Instruction can be executed at the same time as the Display Data Write, thereby minimizing system development time with maximum programming efficiency. When an instruction is being executed for an internal operation, only the Busy Flag/Address Read Instruction can be performed. The other instructions are not valid. It should be noted that during the execution of an instruction, the Busy Flag is set to "1". The Busy Flag is set to "0" when the instructions are can be accepted and executed. Therefore, the Busy Flag should be checked to make certain that BF = "0" before sending another instruction from the MPU. If not, the time between the first instruction and the next instruction is longer than the time it takes to execute the instruction itself. Instruction PT6880 pre 1.1 Description Code Page 16 Mar. 2002 Max. Execution Time when Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 fsp or fosc = 250kHz R S R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Return Home 0 0 0 0 0 0 0 0 1 x Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Display ON/OFF Control 0 0 0 0 0 0 1 D C B Cursor/ Display Shift 0 0 0 0 0 1 S/C R/L x x Function Set 0 0 0 0 1 DL N F x x Set CGRAM Address 0 0 0 1 ACG ACG ACG ACG ACG ACG Set DDRAM Address 0 0 1 ADD ADD ADD ADD ADD ADD ADD Read Busy Flag & Address 0 1 BF AC AC AC AC AC AC AC 1 0 Write Data Writes data into the CGRAM or DDRAM 37us tADD=4us* 1 1 Read Data Read data from the CGRAM or DDRAM 37us tADD=4us* Write data into the CGRAM or DDRAM Read Data from the CGRAM PT6880 pre 1.1 Page 17 Clears entire display. Sets DDRAM Address 0 into the Address Counter Sets DDRAM Address 0 into the Address Counter. Returns shifted display to original position. DDRAM contents remain unchanged. Sets cursor move direction and specifies display shift. (These operations are performed during data write and read.) Sets entire Display (D) ON/OFF. Sets Cursor (C) ON/OFF. Sets Blinking(B) of Cursor Position Character. Moves cursor & shifts display without changing DDRAM contents. Sets interface data length (DL). Sets number of display lines (N). Sets Character Font (F). Sets CGRAM Address. CGRAM data is sent and received after this setting. Sets DDRAM Address. The DDRAM data Is sent and received after this setting. Reads Busy Flag (BF) indicating that internal operation is being performed. Reads Address Counter contents. Mar. 2002 1.52ms 37us 37us 37us 37us 37us 37us 0us Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 or DDRAM Notes: 1. 2. x = Not Relevant * = After the CGRAM/DDRAM Read or Write Instruction has been executed, the RAM Address Counter is incremented or decremented by 1. After the Busy Flag is turned OFF, the RAM Address is updated. 3. I/D = Increment / Decrement Bit I/D = "1" : Increment I/D = "0" : Decrement S = Shift Entire Display Control Bit BF = Busy Flag BF = "1" : Internal Operating in Progress BF ="0" : No Internal Operation is being executed, next instruction can be accepted. R/L = Shift Right / Left R/L = "1" : Shift to the Right R/L = "0" : Shift to the Left S/C = Display Shift / Cursor Move S/C = "1" : Display Shift S/C = "0" : Cursor Move DDRAM = Display Data RAM CGRAM = Character Generator RAM ACG =CGRAM Address ADD = Address Counter Address (corresponds to cursor address) AC = Address Counter (used for DDRAM and CGRAM Addresses) F = Character Pattern Mode F = "1" : 5 x 10 dots F = "0" : 5 x 8 dots N = Number of Lines Displayed N = "1" : 2 -Line Display N = "0" : 1-Line Display * = The time it takes to execute an instruction changes when the frequency changes. To illustrate an example: When fcp of fosc = 250 kHz, then 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. the execution time = 37us x 270/250 = 40us 16. tADD is the time period starting when the Busy Flag is turned OFF up to the time the Address Counter is updated. Please refer to the diagram below. PT6880 pre 1.1 Page 18 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC BUSY SIGNAL (DB7) PT6880 BUSY STATE ADDRESS COUNTER (DB0 TO DB6) A A+1 tADD where 1. tADD depends on the operation frequency and may be calculated using the following equation tADD = 1.5 / (fcp) seconds or tADD = 1.5 /(fosc) seconds INSTRUCTION DESCRIPTION Clear Display Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 This instruction is used to clear the Display Write Space 20H in all DDRAM Addresses. That is, the character pattern for the Character Code 20H must be a BLANK pattern. It then sets the DDRAM Address 0 into the Address Counter and reverts the display to its original state (if the display has been shifted). The display will be cleared and the cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display. Under the Entry Mode, this instruction also sets the I/D to 1 (Increment Mode). The S Bit of the Entry Mode does not change. Return Home Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 * Note: * = Not Relevant This instruction is used to set the DDRAM Address 0 into the Address Counter and revert the display to its original status (if the display has been shifted). The DDRAM contents do not change. The cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display. PT6880 pre 1.1 Page 19 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Entry Mode Set Instruction The Entry Mode Set Instruction has two controlling bits: I/D and S. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S I/D is the Increment / Decrement Bit. When I/D is set to "1". the DDRAM Address is incremented by "1" when a character code is written into or read from the DDRAM. An increment of 1 will move the cursor or blinking one step to the right. When the I/D is set to "0", the DDRAM is decremented by 1 when a character code is written into or read from the DDRAM. An decrement of 1 will move the cursor or blinking one step to the left. S : Shift Entire Display Control Bit This bit is used to shift the entire display. When S is set to "1", the entire display is shifted to the right (when I/D ="0") or left (when I/D ="1"). The display does not shift when reading from the DDRAM, writing into or reading from the CGRAM. When S is set to "0", the display is not shifted. Display ON / OFF Control Instruction The Display On / OFF Instruction is used to turn the display ON or OFF. The controlling bits are D, C and B. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 D C B D : Display ON /OFF Bit When D is set to "1", the display is turned ON. When D is set to "0", the display is turned OFF and the display data is stored in the DDRAM. The display data can be instantly displayed by setting D to "1". C : Cursor Display Control Bit When C is set to "1", the cursor is displayed. In a 5 x 8 dot character font, the cursor is displayed via the 5 dots in the 8th line. In a 5 x 10 dot character font , it is displayed via 5 dots in the 11th line. When C is set to "0", the cursor display is disabled. PT6880 pre 1.1 Page 20 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 During a Display Data Write, the function of the I/D and others will not be altered even if the cursor is not present. Please refer to the figure below. 5 x 8 Dot Character Font 5 x 10 Dot Character Font Cursor Cursor B : Blinking Control Bit When B is set to '1", the character specified by the cursor blinks. The blinking feature is displayed by switching between the blank dots and the displayed character at a speed of 409.6ms intervals when the fcp or fosc is 250kHz. Please refer to the figure below. Figure 1 Figure 2 Note: Figure 1 and 2 are alternately displayed The cursor and the blinking can be set to display at the same time. The blinking frequency depends on the fosc or the reciprocal of fcp. To illustrate, when fcp =270kHz, then, the blinking frequency = 409.6 x 250/270 = 379.2ms Cursor / Display Shift Instruction PT6880 pre 1.1 Page 21 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 This instruction is used to shift the cursor or display position to the left or right without writing or reading the Display Data. This function is used to correct or search the display. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 * * S/C R/L S/C 0 0 1 1 R/L 0 1 0 1 Shift Function Shifts the cursor position to the left. (AC is decremented by 1). Shifts cursor position to the right. (AC incremented by 1). Shifts entire display to the left. The cursor follows the display shift. Shifts the entire display to the right. The cursor follows the display shift. In a 2-line Display, the cursor moves to the second line when it passes the 40th digit of the first line. The first and second line displays will shift at the same time. When the displayed data is shifted repeatedly, each line moves only horizontally. The second line display does not shift into the first line position. The Address Counter (AC) contents will not change if the only action performed is a Display Shift. Function Set Instruction The Function Set Instruction has three controlling 3 bits, namely: DL, N and F. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 * * DL N F PT6880 pre 1.1 Page 22 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 DL : Interface Data Length Control Bit This is used to set the interface data length. When DL is set to "1", the data is sent or received in 8-bit length via the DB0 to DB7 (for an 8-Bit Data Transfer). When DL is set to "0", the data is sent or received in 4-bit length via DB4 to DB7 ( for a 4-Bit Data Transfer). When the 4-bit data length is selected, the data must be sent or received twice. N : Number of Display Line This is used to set the number of display lines. When N="1", the 2-line display is selected. When N is set to "0", the 1-line display is selected. F : Character Font Set This is used to set the character font set. When F is set to "0", the 5 x 8 dot character font is selected. When F is set to "1", the 5 x 10 dot character font is selected. It must be noted that the character font setting must be performed at the head of the program before executing any instructions other than the Busy Flag and Address Instruction. Otherwise, the Function Set Instruction cannot be executed unless the interface data length is changed. Set CGRAM Address Instruction This instruction is used to set the CGRAM Address binary AAAAAA into the Address Counter. Data is then written to or read from the MPU for CGRAM. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 0 ACG ACG ACG ACG ACG Note: ACG is the CGRAM Address DB0 ACG Set DDRAM Address Instruction This instruction is used to set the DDRAM Address binary AAAAAAA into the Address Counter. The data is written to or read from the MPU for the DDRAM. If 1-line display is selected (N="0"), then AAAAAAA can be 00H to 4FH. When the 2-line display is selected, then AAAAAAA can be 00H to 27H for the first line and 40H to 67H for the second line. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 ADD ADD ADD ADD ADD ADD ADD Higher Order Bits Lower Order Bits Note: ADD = DDRAM Address PT6880 pre 1.1 Page 23 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Read Busy Flag and Address Instruction This instruction is used to read the Busy Flag (BF) to indicate if PT6880 is internally operating on a previously received instruction. If BF is set to "1", then the internal operation is in progress and the next instruction will not be accepted. If the BF is set to "0", then the previously received instruction has been executed and the next instruction can be accepted and processed. It is important to check the BF status before proceeding to the next write operation. The value of the Address Counter in binary AAAAAAA is simultaneously read out. This Address Counter is used by both the CGRAM and the DDRAM and its value is determined by the previous instruction. The contents of the address are the same as for the instructions -- Set CGRAM Address and Set DDRAM Address. RS R/WB DB7 0 1 BF Notes: DB6 DB5 DB4 DB3 DB2 DB1 DB0 AC AC AC AC AC AC AC Higher Order Bits Lower Order Bits 1. BF= Busy Flag 2. AC = Address Counter Write Data to CGRAM / DDRAM Instruction This instruction writes 8-bit binary data -- DDDDDDDD to the CGRAM or the DDRAM. The previous CGRAM or DDRAM Address setting determines whether a data is to be written into the CGRAM or the DDRAM. After the write process is completed, the address is automatically incremented or decremented by 1 in accordance with the Entry Mode instruction. It must be noted that the Entry Mode instruction also determines the Display Shift. RS R/WB DB7 DB6 DB5 DB4 DB3 1 0 D D D D D Higher Order Bits DB2 DB1 DB0 D D D Lower Order Bits Read Data from the CGRAM or DDRAM Instruction This instructions reads the 8-bit binary data -- DDDDDDDD from the CGRAM or the DDRAM. The Set CGRAM Address or Set DDRAM Address Set Instruction must be executed before this instruction can be performed, otherwise, the first Read Data will not be valid. RS R/WB DB7 DB6 DB5 DB4 DB3 1 1 D D D D D Higher Order Bits DB2 DB1 DB0 D D D Lower Order Bits When the Read Instruction is executed in series, the next address data is normally read from the Second Read. There is no need for the Address Set Instruction to be performed before this Read PT6880 pre 1.1 Page 24 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 instruction when using the Cursor Shift Instruction to shift the cursor (Reading the DDRAM). The Cursor Shift Instruction has the same operation as that of the Set the DDRAM Address Instruction. After a Read instruction has been executed, the Entry Mode is automatically incremented or decremented by 1 . It must be noted that regardless of the Entry Mode, the Display Shift is not executed. After the Write instructions to either the CGRAM or DDRAM has been performed, the Address Counter is automatically increased or decreased by 1. The RAM data selected by the Address Counter cannot be read out at this time even if the Read Instructions are executed. Therefore, in order to correctly read the data, the following procedure has suggested: 1. 2. Execute the Address Set or Cursor Shift (only with DDRAM) Instruction Just before reading the desired data, execute the Read Instruction from the second time the Read Instruction has been sent. MPU Interface PT6880 can be configured to interface with either the 4-bit or 8-bit MPU via the DB0 to DB7 pins. 8-BIT MPU INTERFACE When PT6880 interfaces with an 8-bit MPU, DB0 to DB7 are used. The 8-bit data transfer starts from the four high order bits --DB4 to DB7 followed by the four low order bits -- DB0 to DB3. An example of a Busy Flag Check Timing in an 8-Bit MPU Interface is given in the diagram below. PT6880 pre 1.1 Page 25 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 4-BIT MPU INTERFACE PT6880 can be configured to interface with a 4-bit MPU and is selected via a program. If the I/O port of the 4-Bit MPU from which PT6880 is connected to, is capable of transferring 8 bits, then an 8-bit data transfer operation is executed. Otherwise, two 4-bit data transfer operations are needed to satisfy one complete data transfer. Under the 4-bit data transfer, DB4 to DB7 are used as bus lines. DB0 to DB3 are disabled. The data transfer between PT6880 and MPU is completed after two 4-bit data have been transferred. The Busy Flag must be checked (one instruction) after completion of the data transfer (that is, 4-bit data has been transferred twice.). The Busy Flag must be checked after two 4-bits data transfer has been completed. Please refer to the diagram below for a 4-bit data transfer timing sequence. Where: 1. 2. 3. IR7 = Instruction Bit 7 IR3 = Instruction Bit 3 AC3 = Address Counter 3 From the above timing diagram, it is important to note that the Busy Flag Check and the data transfer are both executed twice. PT6880 pre 1.1 Page 26 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 OLED Interface PT6880 supports two display types, namely: 5 x 8 dots and 5 x 10 dots character fonts. Each of these type includes a cursor display. Up to 2 lines may be displayed in a 5x 8 dot character font type and 1 line for a 5 x 10 dots character font type. The number of lines that can be displayed as well as the type of font can be selected by using the software program. Please refer to the table below Number of Display Line Character Font Type 1 1 2 5 x 8 dots + cursor 5 x 10 dots + cursor 5 x 8 dots + cursor Number of Common Signals 8 11 16 Duty Factor 1/8 1/11 1/16 As shown in the table above, three types of common signals are available. An example of each configuration is shown in the examples below. It should be noted that every 5 segment signal lines can display one digit, therefore, PT6880 can display up to 8 digits in a 1-line display and 16 digits in a 2-line display. Example 1: An OLED and PT6880 interface with a 5 x 10 dot, 8-character x 1-line display at 1/11 duty cycle is given below. PT6880 pre 1.1 Page 27 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Example 2: OLED and PT6880 connection with 5 x 8 dots, 8-character x 1-line display, at 1/8 duty cycle. Example 3: OLED and PT6880 Connection when 5 x 8 dots, 8-character x 2-line display at 1/16 duty cycle. COM1 OLED Display Panel COM8 COM9 COM16 PT6880 SG1 SG2 SG39 SG40 PT6880 pre 1.1 Page 28 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Absolute Maximum Rating (Unless otherwise stated, Ta=25 oC) Parameter Power Supply Voltage 1 Power Supply Voltage 2 Input Voltage Operating Temperature Storage Temperature Symbol VDD-GND V16 -SEGG Vt Topr Tstg Rating -0.3 to +5.5 -0.3 to +18.0 -0.3 to VDD+0.3 -30 to +85 -55 to +125 Unit V V V o C o C DC Electrical Characteristics (Unless otherwise stated, Ta=25oC, V16=16V) Parameter High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Output Voltage 1 PT6880 pre 1.1 Symbol VIH1 VIL1 VIH2 VIL2 VOH1 Condition All input pins and I/O pins except OSC1 VDD=3V All input pins and I/O pins except OSC1 VDD=5V All input pins and I/O pins except OSC1 VDD=3V All input pins and I/O pins except OSC1 VDD=5V OSC1 VDD=3V OSC1 VDD=5V OSC1 VDD=3V OSC1 VDD=5V Applies to I/O Pins, DB0 to DB7, VDD=3V, IOH=-0.1mA Applies to I/O Pins, DB0 to DB7, VDD=4.5-5.5V, IOH=-0.205mA Page 29 Min. Typ. Max. VDD 0.7VDD - 2.2 - -0.3 - 0.55 V -0.3 - 0.60 V 0.7VDD - VDD V VDD -1.0 - VDD V - - 0.2 VDD V - - 1.0 V 0.75VDD - - V 2.4 - - V VDD VDD Unit V V VDD Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC Low Level Output Voltage 1 VOL1 High Level Output Voltage 2 VOH2 Low Level Output Voltage 2 VOL2 Input Leakage Current (see Note 1) Pull-up MOS Current Operating Current (see Notes 2) OLED Voltage High Level Segment Output Current High Level Segment Output Current Tolerance High Level Segment Output Current Tolerance Low level Common Sink Current PT6880 pre 1.1 ILI -Ip Icc VOLED Applies to I/O Pins, DB0 to DB7 VDD=3V, IOL=0.1mA Applies to I/O Pins, DB0 to DB7 VDD=4.5-5.5V, IOL=1.2mA All Output Pins except DB0 to DB7. VDD=3V, IOH=0.04mA All Output Pins except DB0 to DB7. VDD=4.5-5.5V, IOH=0.04mA All Output Pins except DB0 to DB7. VDD=3V, IOL=0.04mA All Output Pins except DB0 to DB7. VDD=4.5-5.5V, IOL=0.04mA PT6880 - - 0.2VDD V - - 0.1VDD V 0.8VDD - - V 0.9VDD - - V - - 0.2VDD V - - 0.1VDD V VDD=3V, VIN= 0 to VDD -1 - 1 uA VDD=5V, VIN= 0 to VDD -1 - 1 uA DB0 to DB7, RS, R/WB VIN=3.0V DB0 to DB7, RS, R/WB VIN=5.0V Rf Oscillation, External Clock VDD=3V, fosc=270kHz Rf Oscillation, External Clock VDD=5V, fosc=270kHz V16 - SEGG VDD=3V V16 - SEGG VDD=5V 10 50 50 125 120 250 uA uA - - 1 mA - - 1 mA 9.0 - 16.0 V 9.0 - 16.0 V ISEGOH VSEGOH=14V -30 - -300 uA ITOL1* ISEGOH=-300uA - - ±5 % ITOL2* ISEGOH=-300uA - - +1 % ICOMOL VCOMOL=0.4V 15 - - mA Page 30 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC Notes: 1. 2. PT6880 Current flowing through pull-up MOSs, excluding output drive MOS. Input/Output current is not included. When the input is at an intermediate level with the CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. AC Electrical Characteristics (Unless otherwise specified, Ta = 25oC, V16=16V) Parameter External Clock Frequency External Clock Rise Time Symbol fcp trcp External Clock Fall Time tfcp Clock Oscillation Frequency fosc Notes: below. 1. PT6880 pre 1.1 Condition Min. Typ. Max. Unit Applies only to external clock operation. (see Note 1), VDD=3V 125 250 350 kHz Applies only to external clock operation. (see Note 1), VDD=5V 125 250 350 kHz Applies only to external clock operation. (see Note 1), VDD=3V - - 0.2 us - - 0.2 us - - 0.2 us - - 0.2 us 190 270 350 kHz 190 270 350 kHz Applies only to external clock operation. (see Note 1), VDD=5V Applies only to external clock operation. (see Note 1), VDD=3V Applies only to external clock operation. (see Note 1), VDD=5V Rf=75 kΩ, (see Note 2) VDD=3V Rf=91 kΩ, (see Note 2) VDD=5V These parameters apply only to external clock operation. Please refer to the diagram Page 31 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC 2. PT6880 This parameter applies only to the internal oscillation operation using an oscillation resistor Rf. Please refer to the diagram below. When VDD=5V, Rf= 91 kΩ + 2% The values of the Oscillation Frequency depend on the capacitance of the pins -- OSC1 and OSC2 -therefore, the wiring length of these puns must be minimized. Bus Timing Characteristics (Unless otherwise specified, Ta = -20 to +75oC, VDD=5V, V16=16V) Write Operation Timing Characteristics Parameter Symbol Enable Cycle Time tcycE Enable Pulse Width (High Level) PWEH Enable Rise/ Fall Time tEf, tEr Address Set-up Time (RS, R/WB to E) tAS Address Hold Time tAH Data Set-up Time tDSW Data Hold Time tH PT6880 pre 1.1 Condition Typ. - Max. - Unit VDD=3V Min. 1000 VDD=5V 500 - - ns VDD=3V 450 - - ns VDD=5V 230 - - ns VDD=3V - - 25 ns VDD=5V - - 20 ns VDD=3V 60 - - ns VDD=5V 40 - - ns VDD=3V 20 - - ns VDD=5V 10 - - ns VDD=3V 195 - - ns VDD=5V 80 - - ns VDD=3V 10 - - ns VDD=5V 10 - - ns Page 32 ns Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Write Operation Timing Diagram RS VIH1 V IH1 VIL1 V IL1 tAH tAS R/WB VIL1 VIL1 PWEH tAH tEf E VIH1 VIH1 VIL1 VIL1 V IL1 tEr tDSW tH VIH1 DB0 ~ DB7 VIL1 VALID DATA VIH1 VIL1 tcycE PT6880 pre 1.1 Page 33 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Read Operation Timing Characteristics Parameter Symbol Enable Cycle Time tcycE Enable Pulse Width (High Level) PWEH Enable Rise/ Fall Time tEf, tEr Address Set-up Time (RS, R/WB to E) tAS Address Hold Time tAH Data Delay Time tDDR Data Hold Time tDHR Condition Typ. - Max. - Unit VDD=3V Min. 1000 VDD=5V 500 - - ns VDD=3V 450 - - ns VDD=5V 230 - - ns VDD=3V - - 25 ns VDD=5V VDD=3V - - 20 ns 60 - - ns VDD=5V 40 - - ns VDD=3V 20 - - ns VDD=5V 10 - - ns VDD=3V - - 360 ns VDD=5V - - 160 ns VDD=3V 5 - - ns VDD=5V 5 - - ns ns Read Operation Timing Diagram RS V IH1 VIH1 V IL1 VIL1 tAH tAS R/WB VIL1 VIL1 PWEH tAH tEf E VIH1 V IH1 VIL1 VIL1 V IL1 tEr tDHR tDDR VOH1 DB0 ~ DB7 VOL1 * VOH1 VALID DATA VOL1 tcycE Note: * = VOL1 is assumed to be 0.8V at 2MHz Operation. PT6880 pre 1.1 Page 34 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Interface Timing Characteristics with External Driver Parameter Symbol High Level Clock Pulse Width tCWH Low Level Clock Pulse Width tCWL Clock Set-up Time tCSU Data Set-up Time tSU Data Hold Time tDH Clock Rise / Fall Time tct Condition VDD=3V Typ. - Max. - Unit ns VDD=5V Min. 800 800 VDD=3V 800 - - ns VDD=5V 800 - - ns VDD=3V 500 - - ns VDD=5V 500 - - ns VDD=3V 300 - - ns VDD=5V 300 - - ns VDD=3V 300 - - ns VDD=5V 300 - - ns VDD=3V - - 200 ns VDD=5V - - 100 ns ns Interface Timing with External Driver Diagram tct LAT VOH2 VOH2 tCWH VOL2 tCWH CL tCWL VOH2 VOL2 tct tCSU tSU VOH2 D PT6880 pre 1.1 tDH VOL2 Page 35 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Power Supply Condition for Internal Reset Circuit Parameter Symbol Power Supply Rise Time trCC Power Supply OFF Time tOFF Condition VDD=3V Min. 0.1 Typ. - Max. 10 Unit ms VDD=5V 0.1 - 10 ms VDD=3V 1 - - ms VDD=5V 1 - - ms Internal Power Supply Reset Timing Diagram Notes: 1. 2. 3. PT6880 pre 1.1 tOFF compensates for the power oscillation period caused by the momentary power supply oscillations. Specified at 4.5V for a 5-Volt operation and at 2.7 for a 3-Volt operation. If 4.5V is not reached during the 5-Volt operation, the internal reset circuit will not operate normally. Under this condition, PT6880 must be initialized using the instructions. Page 36 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Application Circuit D LAT CL DISB REFOUT E R/WB RS MCU DB0 DB1 DB6 DB7 OSC1 PT6880 pre 1.1 PT6880 DI LAT CL DISB BVR O78 O79 O80 O1 O2 O3 O4 O39 O40 O1 O2 COM15 COM16 COM1 COM2 OLED PANEL REFOUT PT6800 BVR DVR DVR SEGG SEGG SHL OSC2 Page 37 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Package Information 100 Pins, QFP Package (Body Size: 20mm x 14mm , Pitch:0.65mm) D D1 A A2 -A- A1 -B- L1 E1 E -D- e c b 1 -C- SEATING PLANE 2 R1 R2 -H- GAUGE PLANE 0.25mm S L 3 PT6880 pre 1.1 Page 38 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC Symbol c L L1 A A1 A2 b D D1 E E1 e S R1 R2 θ θ1 θ2 θ3 Min. 0.11 0.73 Nom. 0.88 1.60 BSC 0.25 2.50 0.22 0.2 0.13 0.13 0o 0o 5o 5o 2.70 23.20 BASIC 20.00 BASIC 17.20 BASIC 14.00 BASIC 0.65 BASIC - PT6880 Max 0.23 1.03 3.40 0.50 2.90 0.40 0.30 7o 16o 16o Notes: 1. All dimensioning and tolerancing dimension conform to ASME Y14.5M-19942. 2. Dimensions “D1” and “E1” do not include mold protrusion, allowable protrusion is 0.25 mm per side. 3. Regardless of the relative size of the upper and lower body sections, dimensions “D1” and “E1” are determined at the largest feature of the body exclusive of mold flash and gate burrs but including any mismatch between the upper and lower sections of the molded body. 4. Controlling Dimensions: Millimeters 5. Dimension “b” do not include dambar protrusion. The dambar protrusion(s) shall not cause the lead width to exceed “B” maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 6. Refer to JEDEC MS-022 Variation GC-1 JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. PT6880 pre 1.1 Page 39 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Pad Information COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 V16 SG40 SG39 SG38 SG37 SG36 SG35 SG34 SG33 SG32 SG31 SG30 SG29 Pad Configuration SG28 SG27 SG26 COM8 SG25 COM7 SG24 COM6 SG23 COM5 SG22 COM4 SG21 COM3 SG20 COM2 SG19 COM1 SG18 SG17 VSS SG16 DB7 DB6 SG15 DB5 SG14 DB4 SG13 DB3 DB2 SG12 DB1 SG11 DB0 SG10 E R/WB SG9 RS DISB VDD CL LAT DVR6 BVR OSC2 OSC1 VSS VSS V16 REFOUT SEGG SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 D chip size: 2778*3128 pad size: 90*90 ptich size: 120 P-Substrate:VSS unit: µm PT6880 pre 1.1 Page 40 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC PT6880 Pad Location * * * PAD # NAME Location * * * **************************************** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SG(29) NC SG(28) NC SG(27) SG(26) SG(25) SG(24) SG(23) SG(22) SG(21) SG(20) SG(19) SG(18) SG(17) SG(16) SG(15) SG(14) SG(13) SG(12) SG(11) SG(10) SG(9) NC NC NC NC NC NC SG(8) SG(7) SG(6) SG(5) SG(4) SG(3) SG(2) SG(1) SEGG REFOUT V16 VSS VSS OSC1 OSC2 BVR DVR LAT PT6880 pre 1.1 [ 105.900, 3049.400 ] [ 50.000, 2821.300 ] [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 50.000, 2701.300 2581.300 2461.300 2341.300 2221.300 2101.300 1981.300 1861.300 1741.300 1625.600 1475.600 1325.600 1175.600 1025.600 875.600 725.600 575.600 425.600 275.600 ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 50.000, 171.300, 292.000, 412.000, 532.000, 652.000, 772.000, 892.000, 1012.014, 1153.128, 1282.214, 1402.200, 1522.200, 1642.200, 1762.200, 1882.200, 2002.200, 2122.200, 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] Page 41 Mar. 2002 Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Preliminary OLED Driver/Controller IC 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CL VDD DISB D NC RS NC R/WB E DB(0) DB(1) DB(2) DB(3) DB(4) DB(5) DB(6) DB(7) VSS COM(1) COM(2) COM(3) COM(4) COM(5) COM(6) COM(7) COM(8) NC NC NC NC NC NC COM(9) COM(10) COM(11) COM(12) COM(13) COM(14) COM(15) COM(16) V16 SG(40) SG(39) SG(38) SG(37) SG(36) SG(35) SG(34) SG(33) SG(32) SG(31) SG(30) NC PT6880 pre 1.1 [ [ [ [ 2242.200, 2362.200, 2482.200, 2699.200, 50.000 ] 50.000 ] 50.000 ] 90.500 ] [ 2699.200, 210.500 ] [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 2699.200, 330.500 450.500 570.500 690.500 810.500 930.500 1050.500 1170.500 1290.500 1410.500 1537.900 1921.000 2041.000 2161.000 2281.000 2401.000 2521.000 2641.000 2761.000 ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 2690.800, 2570.800, 2380.800, 2240.800, 2100.800, 1960.800, 1820.800, 1680.800, 1560.800, 1440.800, 1320.800, 1185.900, 1065.900, 945.900, 825.900, 705.900, 585.900, 465.900, 345.900, 225.900, 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 3049.400 ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] Page 42 PT6880 Mar. 2002