RF9957 7 CDMA/FM RECEIVE AGC AND DEMODULATOR Typical Applications • CDMA/FM Cellular Systems • Spread-Spectrum Cordless Phones • CDMA PCS Systems • High Speed Data Modems • Wireless Local Loop Systems • General Purpose Digital Receivers Product Description 0.157 0.150 1 0.012 0.008 0.344 0.337 0.025 8°MAX 0°MIN Optimum Technology Matching® Applied ü GaAs HBT GaAs MESFET Si Bi-CMOS SiGe HBT Si CMOS 7 0.0688 0.0532 0.2440 0.2284 0.050 0.016 Si BJT 0.0098 0.0040 QUADRATURE DEMODULATORS The RF9957 is an integrated complete IF AGC amplifier and Quadrature Demodulator designed for the receive section of dual-mode CDMA/FM cellular and PCS applications. It is designed to amplify received IF signals, while providing 100dB of gain control range, and demodulate to baseband I and Q signals. Noise Figure, IP3, and other specifications are designed to be compatible with the IS98 and J-STD-018 Interim Standard for CDMA cellular communications. The IC is manufactured on an advanced 15GHz FT Silicon Bipolar process, and is packaged in a standard miniature 24-lead plastic SSOP package. 0.0098 0.0075 Package Style: SSOP-24 Features • Supports Dual Mode Operation (CDMA GC FL+ and FM) 23 19 • Digitally Controlled Power Down Mode • 2.7V to 3.3V Operation Gain Control CDMA IN+ 4 16 Q OUT+ CDMA IN- 5 IN SEL 14 15 Q OUTInput Select Quad. ÷2 FM IN+ 8 13 LO+ • Quadrature LO Divider • IF AGC Amp with 100dB Gain Control 12 LO21 I OUT+ FM IN- 9 22 I OUT- Band Gap Reference 24 18 BG OUT PD FL- Ordering Information 10 Functional Block Diagram Rev C11 010622 RF9957 RF9957 PCBA CDMA/FM Receive AGC and Demodulator Fully Assembled Evaluation Board RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 7-27 RF9957 Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) Input RF Power Ambient Operating Temperature Storage Temperature Parameter Rating Unit -0.5 to +5 -0.5 to VCC +0.7 +3 -40 to +85 -40 to +150 VDC VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Overall (Cascaded) Maximum Gain Minimum Gain Gain Variation vs. VCC and T Input IP3 +45 -3 -39 QUADRATURE DEMODULATORS 7 Noise Figure IF Input Frequency Range IF Input Impedance I/Q Frequency Range I/Q Amplitude Balance I/Q Phase Balance Max I/Q Output Voltage I/Q DC Output I/Q DC Offset LO Input Frequency Range LO Input Level LO Input Impedance +50 -55 2040 1020 -50 -36 -4 5 70 50 to 250 2400 1200 0 to 50 0.1 1 920 460 dB dB dB dBm dBm dBm dB dB MHz Ω Ω MHz dB deg mVPP VDC mVDC MHz mVPP Ω Ω 3.3 18 16 10 VDC mA mA µA -50 +3 2760 1380 0.5 5 500 680 340 2.0 5 100 to 500 60 to 600 800 400 20 Condition T=25 °C, VCC =3.0V, ZLOAD =5kΩ, LO=170MHz @400mVPP, IF Freq=85MHz, ZS =500Ω (CDMA), ZS =850Ω (FM) VGC =2.5V, FM or CDMA Input, Balanced VGC =0.5V, FM or CDMA Input, Balanced VCC =2.7V to 3.3V and T=-30°C to +85°C VGC =2.5V, Maximum Gain Gain = 35 dB, PIN=-61dBm VGC =0.5V, Minimum Gain VGC =2.5V, Maximum Gain VGC =0.5V, Minimum Gain FM or CDMA, Balanced FM or CDMA, Single Ended Balanced, maximum output level Common Mode I OUT+ to I OUT-; Q OUT+ to Q OUTBalanced Balanced Single Ended Power Supply Supply Voltage Current Consumption 7-28 2.7 3.0 14.5 12.5 CDMA Mode FM Mode Sleep Mode (PD≤ 0.5V) Rev C11 010622 RF9957 Function VCC1 2 VCC2 3 VCC3 4 CDMA IN+ Description Interface Schematic Supply voltage for the LO flip-flop divider and limiting amp. This pin may be connected in parallel with pins 2 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the bandgap, gain control bias circuitry, and AGC stages 2, 3, and 4. This pin may be connected in parallel with pins 1 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the FM and CDMA AGC input stages. This pin may be connected in parallel with pins 1 and 2. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. CDMA Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other CDMA input is AC coupled to ground. The balanced input impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ. BIAS 1200 Ω BIAS 1200 Ω CDMA IN+ 5 6 CDMA INGND 7 8 GND FM IN+ 9 10 FM INBG OUT 11 DEC 12 LO- 13 LO+ Rev C11 010622 Same as pin 4, except complementary input. CDMA IN- See pin 4. Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. Same as pin 6. FM Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other FM input is AC coupled to ground. The balanced input impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ. Same as pin 8, except complementary input. Bandgap Voltage Reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. LO Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other LO input is AC coupled to ground. The frequency of the signal applied to these pins is internally divided by a factor of 2, hence the carrier frequency for the modulator becomes one half of the applied frequency. The singleended input impedance is 400Ω (balanced is 800Ω). The LO input may be driven single-ended but balanced provides optimum gain and phase balance. Same as pin 12, except complementary input. BIAS 1200 Ω BIAS 1200 Ω FM IN+ FM IN- See pin 8. BIAS 400 Ω LO- 7 QUADRATURE DEMODULATORS Pin 1 BIAS 400 Ω LO+ See pin 12. 7-29 RF9957 Pin 14 Function IN SEL Description Interface Schematic Selects between CDMA and FM mode. This is a digitally controlled input. A logic “high” (≥VCC-0.7VDC) selects CDMA mode. A logic “low” (<0.5VDC) selects FM mode. In FM mode, ONLY the I mixer is active. There is no Q output in FM mode. The impedance on this pin is 30kΩ. BIAS 60 kΩ 60 kΩ IN SEL 15 16 17 18 Q OUT- Q OUT+ GND FL- QUADRATURE DEMODULATORS 7 19 20 21 22 23 FL+ GND I OUT+ I OUTGC Balanced Baseband Output of Q Mixer. This pin is internally DC biased and should be DC blocked externally. This output is active in CDMA mode, but is NOT active in FM mode. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. Each pin should be loaded with 2.5kΩ. The balanced load should be 5kΩ. The single-ended output impedance is 1kΩ, while the balanced output impedance is 2kΩ. Same as pin 15, except complementary output. VCC VCC 1 kΩ 1 kΩ Q OUT+ Q OUT- See pin 15. Same as pin 6. Balanced AGC Output/Demod Input. This balanced node is pinned out to allow shunt filtering of the AGC output signal as it enters the demodulator. The basic configuration of the filter should consist of a shunt inductor and shunt capacitor, both connected to the power supply, as the internal circuitry requires this power supply connection through the inductor to operate. Same as pin 18, except complementary. FL- FL+ VCC2 VCC2 1.2 kΩ VCC1 VCC1 1.2 kΩ See pin 18. Same as pin 6. Balanced Baseband Output of I Mixer. This pin is internally DC biased and should be DC blocked externally. This output is active in both CDMA and FM modes. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. Each pin should be loaded with 2.5kΩ. The balanced load should be 5kΩ. The single-ended output impedance is 1kΩ, while the balanced output impedance is 2kΩ. Same as pin 21, except complementary output. VCC 1 kΩ VCC 1 kΩ I OUT+ I OUT- See pin 22. Analog Gain Control for AGC Amplifiers. The valid control range is from 0.5 to 2.5VDC. These voltages are valid for ONLY a 37kΩ source impedance. The gain range for the AGC is 95dB. BIAS 21 kΩ GC 40 kΩ 7-30 Rev C11 010622 RF9957 Pin 24 Function PD Description Interface Schematic Power Down Control. When logic “high” (≥VCC-0.3V), all circuits are operating; when logic “low” (≤0.5V), all circuits are turned off. The input impedance of this pin is 10kΩ. 10 kΩ PD Pin Out 24 PD VCC2 2 23 GC VCC3 3 22 I OUT- CDMA IN+ 4 21 I OUT+ CDMA IN- 5 20 GND GND 6 19 FL+ GND 7 18 FL- FM IN+ 8 17 GND FM IN- 9 16 Q OUT+ BG OUT 10 15 Q OUT- DEC 11 LO- 12 Rev C11 010622 7 QUADRATURE DEMODULATORS VCC1 1 14 IN SEL 13 LO+ 7-31 RF9957 Application Schematic VCC 100 pF Power Down 1 VCC1 PD 24 37 kΩ 2 VCC2 GC 23 10 nF 3 VCC3 I OUT- 22 Gain Control 10 nF 100 nF CDMA SAW Filter I OUT100 nF CDMA IN+ 4 CDMA IN+ I OUT+ I OUT+ 21 680 Ω CDMA IN- 390 nH GND 20 5 CDMA IN- 6 GND FL+ 19 7 GND FL- 18 7 pF VCC 7 pF 10 nF 10 nF FM IN+ 390 nH 8 FM IN+ GND 17 9 FM IN- Q OUT+ 16 10 nF 7 100 nF 10 nF 10 BG OUT QUADRATURE DEMODULATORS Q OUT+ 100 nF Q OUT- Q OUT- 15 10 nF 11 DEC Input Select IN SEL 14 1 nF 1 nF 12 LO- 100 pF LO+ 13 LO IN 7-32 Rev C11 010622 RF9957 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1-3 P3 P2 P1 P1-1 1 PD 2 GND 3 VCC P2-1 P2-3 1 GC 2 GND 3 IN SEL P3-1 P3-3 1 +5 VDC 2 GND 3 -5 VDC R13 36 kΩ R15 1 kΩ P1-1 P2-1 C26 100 nF C25 100 nF P1-3 C2 10 µF J1 CDMA C1 10 nF C5 13 pF 50 Ω µstrip C3 10 nF T1 1 C6 13 pF C4 10 nF L2 390 nH R1 680 Ω 1 VCC1 PD 24 2 VCC2 GC 23 3 VCC3 I OUT- 22 4 CDMA IN+ I OUT+ 21 5 CDMA IN- GND 20 6 GND R9 820 Ω C31 100 nF R8 4.3 kΩ R12 1.6 kΩ C21 100 nF CLC426/ 7 CL + V 6 + 2 - V4 U2 3 L4 390 nH P1-3 C20 6.8 pF L1 390 nH C30 100 nF FL+ 19 R10 8.2 kΩ R11 51 Ω C22 10 µF P3-1 50 Ω µstrip J5 I OUT P3-3 C23 100 nF C24 10 µF C17 100 nF C18 10 µF C27 4.6 nF L5 390 nH 50 Ω µstrip C8 9.1 pF C7 20 pF L3 330 nH R14 3 kΩ 7 GND 8 FM IN+ GND 17 9 FM IN- Q OUT+ 16 FL- 18 C19 6.8 pF R4 820 Ω C9 10 nF C28 100 nF C10 10 nF 10 BG OUT Q OUT- 15 C11 10 nF 11 DEC J3 LO 50 Ω µstrip C12 1 nF T2 1 12 LO- LO+ 13 CLC426/ 7 CL + V 6 + 2 - V4 U1 3 R3 4.3 kΩ R6 8.2 kΩ R7 51 Ω P3-1 50 Ω µstrip C16 10 µF P2-3 9957400 Rev B 7 J4 Q OUT P3-3 C15 100 nF R2 270 Ω C13 1 nF Rev C11 010622 C29 100 nF IN SEL 14 R5 1.6 kΩ C14 100 nF 7-33 QUADRATURE DEMODULATORS J2 FM RF9957 Evaluation Board Layout Board Size 3.025” x 3.025” Board Size 0.031”, Board Material FR-4 QUADRATURE DEMODULATORS 7 7-34 Rev C11 010622 RF9957 QUADRATURE DEMODULATORS 7 Rev C11 010622 7-35 RF9957 CDMA Cascade Conversion Gain versus Gain Control Voltage (VCC=3.0 V, 85 MHz) 50 50 40 40 30 20 10 0 -10 -20 -30 +25°C -40 FM Cascade Conversion Gain versus Gain Control Voltage (VCC=3.0V, 85MHz) 60 Cascade Conversion Gain (dB) Cascade Conversion Gain (dB) 60 30 20 10 0 -10 -20 -30 +25°C -40 -30°C -30°C -50 -50 +85°C -60 +85°C -60 0.5 1 1.5 2 2.5 0.5 1 1.5 GC (V) CDMA IIP3 versus Gain -10 -10 -20 -20 IIP3 (dBm) IIP3 (dBm) (VCC=3.0V, 85MHz) 0 -30 -30 -40 -40 -50 -50 -60 -60 -60 -40 -20 0 20 40 60 -60 -40 -20 Gain (dB) 40 60 40 60 (VCC=3.0V, 85MHz) 80 70 60 60 Noise Figure (dB) 70 50 40 30 50 40 30 20 20 10 10 0 0 -60 -40 -20 0 Gain (dB) 7-36 20 FM Noise Figure versus Gain (VCC=3.0V, 85MHz) 80 0 Gain (dB) CDMA Noise Figure versus Gain Noise Figure (dB) QUADRATURE DEMODULATORS 7 2.5 FM IIP3 versus Gain (VCC=3.0V, 85MHz) 0 2 GC (V) 20 40 60 -60 -40 -20 0 20 Gain (dB) Rev C11 010622