RFMD RF2637

RF2637
0
RECEIVE AGC AMPLIFIER
Typical Applications
• 3V Basestation Systems
• Commercial and Consumer Systems
• General Purpose Linear IF Amplifier
• Portable Battery-Powered Equipment
Product Description
The RF2637 is a complete AGC amplifier designed for
the receive section of 3V cellular and PCS applications
basestations. It is designed to amplify IF signals while
providing more than 90dB of gain control range. Noise
Figure, IP3, and other specifications are designed for basestations. The IC is manufactured on an advanced high
frequency SiGe process, and is packaged in a standard
miniature 8-lead plastic MSOP package.
0.006
+ 0.003
0.192
+ 0.008
0.012
-A-
0.0256
0.118
+ 0.004 sq.
0.034
6° MAX
0° MIN
0.021
+ 0.004
Optimum Technology Matching® Applied
Si BJT
GaAs HBT
9SiGe HBT
Si Bi-CMOS
InGaP/HBT
GaN HEMT
0.006
+ 0.002
NOTES:
1. Shaded lead is pin 1.
2. All dimensions are exclusive of
flash, protrusions or burrs.
3. Lead coplanarity: 0.002 with
respect to datum "A".
Package Style: MSOP-8
GaAs MESFET
Si CMOS
Features
SiGe Bi-CMOS
• Supports Basestation Applications
• -55dB to +51dB Gain Control Range @
85MHz
• Single 3V Power Supply
IN+ 1
8 VCC1
IN- 2
7 VCC2
GND 3
6 OUT+
GC 4
GAIN
CONTROL
• 12MHz to 385MHz Operation
Ordering Information
5 OUT-
Functional Block Diagram
Rev A3 040511
• -2dBm Input IP3
RF2637
RF2637 PCBA
Receive AGC Amplifier
Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
10-41
RF2637
Absolute Maximum Ratings
Parameter
Supply Voltage
Control Voltage
Input RF Power
Operating Ambient Temperature
Storage Temperature
Parameter
Value
Unit
-0.5 to +7.0
-0.5 to +5.0
+10
-40 to +85
-40 to +150
VDC
VDC
dBm
°C
°C
Specification
Min.
Typ.
Max.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Unit
T=25°C, 85MHz, VCC =3.0V, ZS =500Ω,
ZL =500Ω, 500Ω External Input Terminating
Resistor, 500Ω External Output Terminating
Resistor (Effective ZS =333Ω, Effective
ZL =250Ω) (See Application Example)
Overall
Frequency Range
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Gain Slope
Gain Control Voltage Range
Gain Control Input Impedance
Noise Figure
Input IP3
Stability (Max VSWR)
Condition
+40
-65
+35
-68
-46
12 to 385
+51
-55
+45
-58
57
0 to 2.5
30
5
-40
-2
+65
-40
+55
-48
7.2
MHz
dB
dB
dB
dB
dB/V
VDC
kΩ
dB
dBm
dBm
10:1
VGC =2.5V, 85MHz
VGC =0.1V, 85MHz
VGC =2.5V, 385MHz
VGC =0.1V, 385MHz
Note 1
Source impedance of 4.7kΩ
At maximum gain and 85MHz
At +40dB gain, referenced to 500Ω
At minimum gain, referenced to 500Ω
Spurious<-70dBm
IF Input
Input Impedance
1
kΩ
CDMA, differential
V
mA
mA
Minimum gain, VCC =3.0V
Maximum gain, VCC =3.0V
Power Supply
Voltage
Current Consumption
6
7
2.7 to 3.4
10
11.5
15
15
Thermal
Thermal Resistance
150
Maximum Junction Temperature
90
Note 1: Measured between a gain control voltage of 1.0V to 1.5V.
10-42
°C/W
°C
Theta J-Ref 85°C
Ref 85°C
Rev A3 040511
RF2637
Pin
1
Function
IN+
2
3
INGND
4
GC
Description
CDMA balanced input pin. This pin is internally DC-biased and should
be DC-blocked if connected to a device with a DC level other than VCC
present. A DC to connection to VCC is acceptable. For single-ended
input operation, one pin is used as an input and the other CDMA input
is AC-coupled to ground. The balanced input impedance is 1kΩ, while
the single-ended input impedance is 500Ω.
Same as pin 2, except complementary input.
Interface Schematic
BIAS
700 Ω
700 Ω
CDMA+
CDMA-
See pin 1.
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
Analog gain adjustment for all amplifiers. Valid control ranges are from
0V to 2.5V. Maximum gain is selected with 2.5V. Minimum gain is
selected with 0V. These voltages are only valid for a 4.7kΩ DC source
impedance.
VCC
12.7 kΩ
23.5 kΩ
15 kΩ
5
OUT-
6
7
OUT+
VCC2
8
VCC1
Rev A3 040511
Balanced output pin. This is an open-collector output, designed to
operate into a 250Ω balanced load. The load sets the operating impedOUT+
ance, but an external choke or matching inductor to VCC must also be
supplied in order to correctly bias this output. This bias inductor is typically incorporated in the matching network between the output and next
stage. Because this pin is biased to VCC, a DC-blocking capacitor must
be used if the next stage’s input has a DC path to ground.
Same as pin 5, except complementary output.
See pin 5.
Supply voltage pin. External bypassing is required. The trace length
between the pin and the bypass capacitors should be minimized. The
ground side of the bypass capacitors should connect immediately to
ground plane.
Same as pin 7.
OUT-
See pin 7.
10-43
RF2637
Application Schematic
Measurement
Reference Plane
ZS=500 Ω
Z S, EFF=333 Ω
CDMA IF Filter
CDMA+
R1:
1 kΩ
CDMAZ IN, EFF=500 Ω
1
8
2
7
3
6
Z IN=1 kΩ
10 nF
C1
VCC
ZLOAD=500Ω
L1
C2
OUT+
R2: 500Ω
GAIN
4
4.7 kΩ
GAIN
CONTROL
C2
OUT-
5
ZLOAD,EFF=250 Ω
R1 sets the CDMA balanced input impedance. The effective input impedance is then 500 Ω.
C1
L1
VCC
Measurement
Reference Plane
10 nF
ZOUT=500 Ω
R2 sets the balanced output impedance to 500 Ω. L1 and C2 serve dual purposes. L1 serves
as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1
and C2 may be chosen to form an impedance matching network of the load impedance is not
500 Ω. Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit
at the IF when the load impedance is 500 Ω.
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
CDMA
J1
SMA
50 Ω µstrip
C3
15 pF
L1
390 nH
C4
15 pF
C1
10 nF
L2
390 nH
C2
10 nF
C10
10 nF
T1
R1
1 kΩ
1
2
3
4
P1
P1-1
P1-3
10-44
1
VCC
2
GND
3
GC
7
L4
390nH
C8
15 pF
OUT
T2
GC
R2
4.7 kΩ
VCC
8
C5
1 nF
6
GAIN
CONTROL
R3
510 Ω
50 Ω µstrip
J2
SMA
5
L3
390nH
C9
15 pF
VCC
2627400A
C6
10 nF
C7
10 nF
Rev A3 040511
RF2637
Evaluation Board Layout
Board Size 2.750" x 2.000"
Board Thickness 0.031”, Board Material FR-4
Rev A3 040511
10-45
RF2637
10-46
Rev A3 040511
RF2637
Gain versus VGC Across Temperature,
VCC = 3.0V
0.0
40.0
-10.0
20.0
-20.0
Input IP3 (dBm)
Gain (dB)
Input IP3 versus VGC Across Temperature,
VCC = 3.0V, FO = 85MHz
60.0
0.0
-20.0
-30.0
-40.0
-40.0
-50.0
-40°C
25°C
85°C
-40°C
25°C
85°C
-60.0
-60.0
0.0
0.5
1.0
1.5
2.0
2.5
VGC (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VGC (V)
Noise Figure versus Frequency Across Temperature,
VCC = 3.0V, VGC = 2.5V
9.0
8.0
Noise Figure (dB)
7.0
6.0
5.0
4.0
3.0
2.0
-40°C
25°C
85°C
1.0
0.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
Frequency (MHz)
Rev A3 040511
10-47
RF2637
10-48
Rev A3 040511