RF9936 8 PCS LOW NOISE AMPLIFIER/MIXER Typical Applications • CDMA/TDMA/DCS1900 PCS Systems • General Purpose Downconverter • PHS 1500/WLAN 2400 Systems • Micro-Cell PCS Base Stations • Receivers Employing Diversity Antennas • Portable Battery Powered Equipment D R ES F9 98 IG 6 N S Optimum Technology Matching® Applied ! Si BJT Si Bi-CMOS GaAs HBT LNA SEL 1 .010 .004 .033 1 .012 .008 .344 .337 .025 .244 .228 .069 .053 .050 .016 .010 .008 Package Style: SSOP-24 Si CMOS Features • Complete Receiver Front-End 24 GC VCC1 2 GAIN ADJUST 23 GND9 • Analog RF Gain Control 22 VCC4 • Single 3.6V Power Supply GND1 4 21 GND8 • Digitally Selectable LNA Inputs N S O ee T VCC2 3 LNA2 IN 5 GND2 6 GND3 7 LNA1 IN 8 20 LNA OUT SEL. LOGIC 18 MIX RF IN VCC3 10 15 IF+ 14 GND5 Ordering Information RF9936 RF9936 PCBA PCS Low Noise Amplifier/Mixer Fully Assembled Evaluation Board 13 LO BUFF OUT Functional Block Diagram Rev A8 000822 • 1500MHz to 2500MHz Operation 17 GND6 16 IF- LO IN 12 • Digitally Selectable Buffered LO Output 19 GND7 GND4 9 LO BUFF EN 11 8 8°MAX 0°MIN GaAs MESFET U F pg O ra R de d P SiGe HBT .157 .150 uc t N E ro W d The RF9936 is a monolithic integrated receiver front-end for PCS applications. The IC contains all of the required components to implement the RF functions of the receiver front-end except for the passive filtering and LO generation. It contains two LNAs (low-noise amplifiers), a double-balanced Gilbert cell mixer, a balanced IF output, an LO isolation buffer amplifier, and an LO output buffer amplifier for providing the buffered LO signal as an output. On-chip digital logic is used to enable the appropriate LNA. The LNAs share a common output that permits insertion of a bandpass filter between the LNA output and the Mixer section. Analog gain adjustment is provided which allows 10dB variation in gain. The IC is designed to operate from a single 3.6V power supply. FRONT-ENDS Product Description RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-121 RF9936 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Ambient Operating Temperature Storage Temperature Parameter Rating Unit -0.5 to 7.0 +6 -40 to +85 -40 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Condition RF Frequency Range LO Frequency Range IF Frequency Range 1500 to 2500 1200 to 2500 DC to 500 D R ES F9 98 IG 6 N S T = 25°C, VCC =3.6V, RF=1959MHz, LO=1749MHz @ -2dBm Overall MHz MHz MHz 1kΩ balanced load, 2.5dB Image Filter Loss. Cascaded Performance Input IP3 -14 -9 2.5 5.1 Gain Reverse Isolation Output VSWR dB VG ≥2.5V dBm dBm dB dB 1.4 <2.5:1 dB +2 dBm 13.5 23 <1.5:1 dB dB U F pg O ra R de d P Noise Figure Input VSWR 15.5 dB uc t First Section (LNA) N S O ee T FRONT-ENDS Cascade Noise Figure 27.5 N E ro W d 8 Cascade Conversion Gain, Maximum Cascade Conversion Gain, Minimum Cascade Input IP3 By varying the gain of the second stage, a trade-off of gain and noise figure against IP3 can be made. VG ≤0.5V Input VSWR Input IP3 Conversion Gain, Maximum Conversion Gain, Minimum Output Impedance 8-122 6.5 13.5 1.5:1 -3 +2 16 6 1 Input is internally matched for optimum noise figure from a 50Ω source. IP3 may be increased 10dB by connecting pin 22 to VCC through the matching inductor. The LNA’s current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made. See pin description for pin 20. With 1kΩ balanced load. Second Section (Mixer) Noise Figure Maximum Gain Minimum Gain Single sideband, at Maximum Gain Setting Single sideband, at Minimum Gain Setting The LNA section may be left unused. Power is not connected to pin 1. The performance is then as specified for the Second Section (Mixer). dB dB dBm dBm dB dB kΩ By varying the gain of the second stage, a trade-off of gain and noise figure against IP3 can be made. Please see data plots. Single Sideband, at maximum gain Single Sideband, at minimum gain At maximum gain At minimum gain VG ≤0.2V VG ≥2.5V Balanced Rev A8 000822 RF9936 Parameter Specification Min. Typ. Max. Unit Condition LO Input LO Input Range LO Output Level LO to RF (Mix In) Rejection LO to IF1, IF2 Rejection LO Input VSWR -5 to +3 -5 -25 30 20 <2:1 dBm dBm dBm dB dB 3.6±5% 5 46 43 V mA mA mA Buffer On, -2dBm input Buffer Off, -2dBm input Single ended Power Supply LNA only LNA + Mixer, LO Buffer On LNA + Mixer, LO Buffer Off D R ES F9 98 IG 6 N S 50 47 8 N S O ee T U F pg O ra R de d P uc t FRONT-ENDS N E ro W d Voltage Current Consumption Rev A8 000822 8-123 RF9936 VCC2 4 GND1 5 LNA2 IN 6 7 GND2 GND3 8 LNA1 IN 9 10 GND4 VCC3 11 LO BUFF EN 12 LO IN 13 LO BUFF OUT 14 GND5 15 IF+ 16 17 IFGND6 18 MIX RF IN 19 GND7 8-124 10 kΩ 150 Ω VCC1 VCC4 BIAS Ground connection for LNA1. Keep traces physically short and connect immediately to ground plane for best performance. RF Input pin for LNA1. This pin is internally DC blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50Ω source impedance. Same as pin 7. Supply voltage for both LO buffer amplifiers. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Enable pin for the LO output buffer amplifier. This is a digitally controlled input. A logic "high" (≥3.1V.) turns the buffer amplifier on, and the current consumption increases by 3mA (with -2dBm LO input). A logic "low" (≤0.5V.) turns the buffer amplifier off. Mixer LO Input pin. This pin is internally DC blocked and matched to 50Ω. Optional Buffered LO Output. This pin is internally DC blocked and matched to 50Ω. The buffer amplifier is switched on or off by the voltage level at pin 11. Ground connection for both LO buffer amplifiers. Keep traces physically short and connect immediately to ground plane for best performance. Open-collector IF Output pin. This is a balanced output. The output impedance is set by an internal 1000Ω resistor to pin 16. Thus the differential IF output impedance is 1000Ω. The resistor sets the operating impedance, but an external choke or matching inductor to VCC must be supplied in order to bias this output. This inductor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. Same as pin 15, except complementary output. LO BUFF EN U F pg O ra R de d P 3 Supply Voltage for the Mixer and RF Buffer Amplifier. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Supply Voltage for the LNAs and associated select logic. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Ground connection for LNA2. Keep traces physically short and connect immediately to ground plane for best performance. RF Input pin for LNA2. This pin is internally DC blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50Ω source impedance. Same as pin 4. LNA SEL D R ES F9 98 IG 6 N S VCC1 Interface Schematic Selects which LNA (LNA1 or LNA2) is active. This is a digitally controlled input. A logic "high" (≥3.1V.) selects LNA2. A logic "low" (≤0.5V.) selects LNA1. uc t 2 Description N E ro W d Function LNA SEL N S O ee T FRONT-ENDS 8 Pin 1 7.5 kΩ IF- IF+ 1 kΩ See pin 15. Ground connection for the Mixer. Keep traces physically short and connect immediately to ground plane for best performance. Mixer RF Input Pin. This pin is internally DC blocked and matched to 50Ω. Same as pin 17. Rev A8 000822 RF9936 21 22 GND8 VCC4 23 24 GND9 GC Description Interface Schematic LNA Output pin. This is an open-collector output. This pin is typically connected to pin 22 through a bias/matching inductor. This inductor, in conjunction with a series blocking/matching capacitor, forms a matching network to the 50Ω image filter and provides bias (see Application Example). The LNA’s IP3 may be increased 10dB by connecting pin 20 to VCC through the inductor. The LNA’s current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made by connecting resistance values between VCC and the matching inductor. The two reference points for consideration are with 150Ω used, which is what connection to pin 22 achieves, the Input IP3 is +2dBm and the LNA ICC is 5mA. Using no resistance, the Input IP3 is +12 dBm and the LNA ICC is 15 mA. Desired operating points in between these values may be interpolated, roughly. Same as pin 17. LNA OUT D R ES F9 98 IG 6 N S Function LNA OUT Output supply voltage for the LNA Output (pin 20). This pin should NOT be connected to a voltage supply. This pin should be connected to pin 20 through a bias/matching inductor (see Application Example). External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Same as pin 17. Analog gain adjustment for RF buffer amplifier. Minimum gain is selected with 2.5V to 3.0V. Maximum gain is selected with 0V to 0.5 V. When operating the RF9936 at fixed maximum gain, this pin may be grounded. See pin 2. 150 Ω GC 8 350 Ω N S O ee T U F pg O ra R de d P uc t FRONT-ENDS N E ro W d Pin 20 Rev A8 000822 8-125 RF9936 Application Schematic LNA SEL 1 GC (Min Gain: ≥3.1V, Max Gain: ≤0.5V) 24 VCC 2 GAIN ADJUST 23 68 pF 3 22 4 21 5 20 68 pF RF2 IN 2.7 nH SEL. LOGIC 7 RF1 IN 8 D R ES F9 98 IG 6 N S 1.8 pF 6 18 VCC 68 pF 17 LO IN 8 C1 L1 C2 ZFILTER = 1 kΩ Filter 16 IF- C2 10 LO BUFF EN (On: ≥3.1v, Off: ≤0.5V) VCC 1 nF 68 pF 9 RF Image Filter, 50 Ω 19 15 68 pF 11 12 14 13 C1 L1 VCC 1 nF ZOUT = 1 kΩ IF+ Measurement Reference Plane LO BUFF OUT N S O ee T U F pg O ra R de d P uc t FRONT-ENDS N E ro W d L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 100 Ω. Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit at the IF when the IF filter's input impedance is 100 Ω. 8-126 Rev A8 000822 RF9936 Evaluation Board Schematic IF 210MHz (Download Bill of Materials from www.rfmd.com.) R1 1 kΩ 1 C15 1 nF 24 2 P1-1 C17 1 nF LNA2 IN J2 C16 22 pF 22 4 21 50 Ω µstrip 5 LNA1 IN J1 50 Ω µstrip SEL. LOGIC P1-1 C18 22 pF 8 9 R2 1 kΩ P1-3 C23 1 nF C20 22 pF 10 11 50 Ω µstrip J3 12 19 2 C1 22 pF see notes P1-3 1 3 C5 22 pF see notes 6 FL1 (SAW Filter) 4 5 50 Ω µstrip J6 L6 39 nH C21 1 pF C6 100 pF C3 22 pF see notes 16 15 L7 39 nH 14 13 C22 1 pF C7 100 pF L2 470 nH L3 470 nH C13 22 pF C9 1 nF L5 180 nH C12 1 nF C8 5.1 pF T1 5.5:1 C11 1.5 pF 1 VCC 2 GND 3 BUFFER ENABLE P2 P2-1 MIXER IN 18 17 P1-1 P2-3 1 LNA SELECT 2 GND 3 GC IF OUT 50 Ω µstrip J4 L4 47 nH C24 4.7 µF 50 Ω µstrip 8 LO OUT J5 N S O ee T U F pg O ra R de d P uc t FRONT-ENDS N E ro W d Note: 1) For cascaded LNA/MIXER applications, install C1 and C5 and remove C2 and C3 (default configuration). 2) For LNA only and/or MIXER only characterization, install C2 and remove C1 and C5. 3) L5 select value 180 nH to 220 nH. 4) Do not install C2, C3 in normal cascade operation. 50 Ω µstrip LNA OUT J7 L1 2.7 nH C4 3.9 pF Drawing 9936401 Rev A P1 C2 22 pF see notes C10 22 pF 20 7 C19 1 nF 23 3 6 LO IN GAIN ADJUST P2-3 C14 1 nF D R ES F9 98 IG 6 N S P2-1 Rev A8 000822 8-127 RF9936 Evaluation Board Layout D R ES F9 98 IG 6 N S (Assembly, Top layer, Mid-signal layer, Internal Ground layer) N S O ee T U F pg O ra R de d P uc t FRONT-ENDS N E ro W d 8 8-128 Rev A8 000822 U F pg O ra R de d P N S O ee T Rev A8 000822 D R ES F9 98 IG 6 N S FRONT-ENDS uc t N E ro W d RF9936 Evaluation Board Layout cont’d 8 8-129 U F pg O ra R de d P N S O ee T uc t 8 D R ES F9 98 IG 6 N S N E ro W d FRONT-ENDS RF9936 8-130 Rev A8 000822