RF9986 8 PCS LOW NOISE AMPLIFIER/MIXER Typical Applications • CDMA/TDMA/DCS1900 PCS Systems • Micro-Cell PCS Base Stations • PHS 1500/WLAN 2400 Systems • Portable Battery-Powered Equipment • General Purpose Down Converter Product Description 0.157 0.150 1 0.012 0.008 0.344 0.337 0.025 Si Bi-CMOS ü GaAs MESFET SiGe HBT Si CMOS 8 8°MAX 0°MIN Optimum Technology Matching® Applied GaAs HBT 0.0688 0.0532 0.2440 0.2284 0.050 0.016 Si BJT 0.0098 0.0040 0.0098 0.0075 Package Style: SSOP-24 Features 24 NC • Complete Receiver Front-End VCC1 2 23 GND9 • Extremely High Dynamic Range VCC2 3 22 VCC4 • Single 3.6V Power Supply GND1 4 21 GND8 NC 1 LNA IN 5 20 LNA OUT GND2 6 19 GND7 GND3 7 18 MIX RF IN NC 8 16 IF- VCC3 10 15 IF+ LO IN 12 14 GND5 • 1500MHz to 2500MHz Operation Ordering Information RF9986 RF9986 PCBA PCS Low Noise Amplifier/Mixer Fully Assembled Evaluation Board 13 LO BUFF OUT Functional Block Diagram Rev B1 010717 • External LNA IP3 Adjustment 17 GND6 GND4 9 LO BUFF EN 11 FRONT-ENDS The RF9986 is a monolithic integrated receiver front-end for PCS, PHS, and WLAN applications. The IC contains all of the required components to implement the RF functions of the receiver front-end except for the passive filtering and LO generation. It contains an LNA (low-noise amplifiers), a double-balanced Gilbert cell mixer, a balanced IF output, an LO isolation buffer amplifier, and an LO output buffer amplifier for providing the buffered LO signal as an output. The IC is designed to operate from a single 3.6V power supply. RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-131 RF9986 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Ambient Operating Temperature Storage Temperature Parameter Rating Unit -0.5 to 7.0 +6 -40 to +85 -40 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T = 25°C, VCC =3.6V, RF=1959MHz, LO=1749MHz @ -2dBm Overall RF Frequency Range LO Frequency Range IF Frequency Range DC to 500 MHz MHz MHz 1500 1200 2500 2500 25 -10.0 2.5 dB dBm dB Noise Figure Input VSWR 1.4 <2:1 dB Input IP3 +5.5 dBm 12 23 <1.5:1 dB dB 5.5 1.5:1 -0.5 15.5 1 dB Cascaded Performance Cascade Conversion Gain Cascade Input IP3 Cascade Noise Figure 1kΩ balanced load, 2.5dB Image Filter Loss. 22 -15.0 First Section (LNA) FRONT-ENDS 8 Condition Gain Reverse Isolation Output VSWR Second Section (Mixer) Noise Figure Input VSWR Input IP3 Conversion Gain Output Impedance dBm dB kΩ Single Sideband The LNA section may be left unused. Power is not connected to pin 1. The performance is then as specified for the Second Section (Mixer). Input is internally matched for optimum noise figure from a 50Ω source. IP3 may be increased 10dB by connecting pin 22 to VCC through the matching inductor. The LNA’s current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made. See pin description for pin 20. With 1kΩ balanced load. Single Sideband Balanced LO Input LO Input Range LO Output Level -5 to +3 -4 -25 30 20 <2:1 LO to RF (Mix In) Rejection LO to IF1, IF2 Rejection LO Input VSWR +1 -20 dBm dBm dBm dB dB Buffer On, -2dBm input Buffer Off, -2dBm input Single ended Power Supply Voltage Current Consumption 8-132 2.7 3.6±5% 5 52 48 5.0 V mA mA mA LNA only LNA + Mixer, LO Buffer On LNA + Mixer, LO Buffer Off Rev B1 010717 RF9986 Function NC VCC1 3 VCC2 4 GND1 5 LNA IN 6 7 GND2 GND3 8 9 10 NC GND4 VCC3 11 LO BUFF EN 12 LO IN 13 LO BUFF OUT 14 GND5 15 IF+ 16 17 IFGND6 18 MIX RF IN 19 GND7 Rev B1 010717 Description Interface Schematic No connection. This pin may be grounded (recommended) or left open. Supply voltage for the mixer and RF buffer amplifier. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Supply voltage for the LNA. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Ground connection for the LNA. For best performance, keep traces physically short and connect immediately to ground plane. RF Input pin for the LNA. This pin is internally DC-blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50Ω source impedance. Same as pin 4. 150 Ω VCC1 VCC4 BIAS Ground connection for the RF buffer amplifier. For best performance, keep traces physically short and connect immediately to ground plane. No connection. This pin may be grounded (recommended) or left open. Same as pin 7. Supply voltage for both LO buffer amplifiers. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Enable pin for the LO output buffer amplifier. This is a digitally controlled input. A logic "high" (≥3.1V) turns the buffer amplifier on, and the current consumption increases by 3mA (with -2dBm LO input). A logic "low" (≤0.5V) turns the buffer amplifier off. Mixer LO input pin. This pin is internally DC-blocked and matched to 50Ω. Optional buffered LO output. This pin is internally DC-blocked and matched to 50Ω. The buffer amplifier is switched on or off by the voltage level at pin 11. Ground connection for both LO buffer amplifiers. For best performance, keep traces physically short and connect immediately to ground plane. Open-collector IF output pin. This is a balanced output. The output impedance is set by an internal 1000Ω resistor to pin 16. Thus the differential IF output impedance is 1000Ω. The resistor sets the operating impedance, but an external choke or matching inductor to VCC must be supplied in order to bias this output. This inductor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. Same as pin 15, except complementary output. LO BUFF EN 8 7.5 kΩ FRONT-ENDS Pin 1 2 IF- IF+ 1 kΩ See pin 15. Ground connection for the mixer. For best performance, keep traces physically short and connect immediately to ground plane. Mixer RF Input Pin. This pin is internally DC-blocked and matched to 50Ω. Same as pin 17. 8-133 RF9986 Pin 20 Function LNA OUT 21 22 GND8 VCC4 23 24 GND9 NC Description Interface Schematic LNA output pin. This is an open-collector output. This pin is typically connected to pin 22 through a bias/matching inductor. This inductor, in conjunction with a series blocking/matching capacitor, forms a matching network to the 50Ω image filter and provides bias (see Application Schematic). The LNA’s IP3 may be increased 10dB by connecting pin 20 to VCC through the inductor. The LNA’s current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made by connecting resistance values between VCC and the matching inductor. The two reference points for consideration are with 150Ω used, which is what connection to pin 22 achieves, the Input IP3 is +5.5dBm and the LNA ICC is 5mA. Using no resistance, the Input IP3 is +15.5 dBm and the LNA ICC is 15 mA. Desired operating points in between these values may be interpolated, roughly. Same as pin 17. Output supply voltage for the LNA output (pin 20). This pin is typically connected to pin 20 through a bias/matching inductor (see application schematic). External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Same as pin 17. LNA OUT See pin 2. No connection. This pin may be grounded (recommended) or left open. Application Schematic FRONT-ENDS 8 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 VCC 22 pF 22 pF RF IN 2.7 nH 1.8 pF 9 VCC VCC 1 nF 22 pF RF Image Filter, 50 Ω C1 L1 C2 ZFILTER = 1 kΩ Filter IF- 16 22 pF C2 10 IF+ 15 LO BUFF EN (On: ≥3.1 V; Off: ≤0.5 V) 11 14 LO IN 12 13 22 pF 1 nF C1 L1 VCC Measurement Reference Plane ZOUT = 1 kΩ LO BUFF OUT L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 1000 Ω. Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circut at the IF when the IF filter's input impedance is 1000 Ω. 8-134 Rev B1 010717 RF9986 Evaluation Board Schematic (IF=210MHz) (Download Bill of Materials from www.rfmd.com.) C17 1 nF J1 LNA IN C16 22 pF 50 Ω µstrip 24 2 23 3 22 4 21 5 20 6 19 7 18 C18 22 pF P1-1 P1-3 R2 1 kΩ J2 LO IN C23 1 nF P1-3 P1-1 16 10 15 11 14 12 13 Drawing 9986400, Rev - 50 Ω µstrip C4 1 pF C2 22 pF 50 Ω µstrip J6 LNA OUT C1 22 pF FL1 C5 22 pF C29 100 pF 50 Ω µstrip T1 5.5:1 L5 220 nH C11 1.5 pF C30 100 pF L3 470 nH L2 470 nH C22 1 nF C21 22 pF 50 Ω µstrip C3 22 pF C8 5 pF J5 MIXER IN J4 IF OUT L4 47 nH 50 Ω µstrip J3 LO OUT P1-1 50 Ω µstrip P1 P1-1 C20 22 pF 9 R3 See Note 2 L1 2.7 nH 17 8 C19 1 nF C10 22 pF C24 4.7 µF Notes: 1 VCC 2 GND 3 BUFFER ENABLE Rev B1 010717 1. C11 is selected to fine tune L4 for IF output match at 210 MHz. 2. R3 is not normally populated. For applications requiring additional LNA IP3, see the datasheet for recommended resistance values. 3. C2 and C3 are not normally populated. If C2 and C3 are populated, the LNA and mixer can be tested independently; in this case, C1 and C5 should be removed. 8-135 8 FRONT-ENDS P1-1 1 RF9986 Evaluation Board Layout 3” x 3” Assembly FRONT-ENDS 8 Top layer 8-136 Rev B1 010717 RF9986 Bottom Layer 8 FRONT-ENDS Internal Ground Rev B1 010717 8-137 RF9986 FRONT-ENDS 8 8-138 Rev B1 010717