TI TMS416809

TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
D
D
D
D
D
D
D
D
D
Organization . . . 2 097 152 × 8
Single 5 V Power Supply (±10% Tolerance)
Performance Ranges:
’41x809-60
’41x809-70
’41x809-80
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
80 ns
20 ns
40 ns
DZ PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
A11†
A10
A0
A1
A2
A3
VCC
EDO
CYCLE
tHPC
MIN
25 ns
30 ns
35 ns
Extended Data Out (EDO) Operation
CAS-Before-RAS ( CBR) Refresh
High-Impedance State Unlatched Output
High-Reliability Plastic 28-Lead (DZ Suffix)
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
Operating Free-Air Temperature Range
0°C to 70°C
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments (TI)
TMS416809
TMS417809
POWER
SUPPLY
5V
5V
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
† A11 is NC (no internal connection) for TMS417809.
PIN NOMENCLATURE
AVAILABLE OPTIONS
DEVICE
1
REFRESH
CYCLES
4 096 in 64 ms
2 048 in 32 ms
description
The TMS41x809 series is a set of high-speed,
16 777 216-bit dynamic random-access memories (DRAMs) organized as 2 097 152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
A0 – A11
DQ0 – DQ7
CAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5 V Supply‡
Ground
Write Enable
‡ See Available Options Table.
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns. All addresses and
data-in lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
The TMS41x809 is offered in a 28-lead plastic
surface-mount SOJ package (DZ suffix). This
package is characterized for operation from 0°C
to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
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1
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
operation
extended data out
Extended data out (EDO) allows data output rates up to 40 MHz for 60-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold, and for
address multiplex is eliminated. The maximum number of columns that can be accessed is determined by
tRASP , the maximum RAS low time.
Extended data out does not place the data in / data out pins (DQs) into the high-impedance state with the rising
edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes
the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO
operation benefit.
address: A0 – A11 ( TMS416809) and A0 – A10 (TMS417809)
Twenty-one address bits are required to decode 1 of 2 097 152 storage-cell locations. For the TMS416809,
12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS).
Nine column-address bits are set up on A0 through A8. For the TMS417809, 11 row-address bits are set up on
inputs A0 through A10 and latched onto the chip by RAS. Ten column-address bits are set up on A0 through
A9. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable
because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffers and latching the address bits into the column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 7).
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 8).
data in / data out (DQ0 – DQ7)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE descriptions.
RAS-only refresh
TMS416809
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
2
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TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
TMS417809
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after
RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
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3
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
logic symbol (TMS416809)†
RAM 2M x 8
A0 10
A1 11
20D9/21D0
A2 12
A3 13
A4
16
A5 17
A6 18
A7 19
A8 20
A
0
2 097 151
20D17/21D8
A9 21
A10 9
20D19
A11 8
20D20
20D18
C20[ROW]
RAS
7
CAS 23
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W
OE
6
22
DQ0 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
4
POST OFFICE BOX 1443
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TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
logic symbol (TMS417809)†
RAM 2M x 8
A0 10
A1 11
20D10/21D0
A2 12
A3 13
A4
16
A5 17
A6 18
A
0
2 097 151
A7 19
A8 20
A9 21
A10 9
20D19/21D9
20D20
C20[ROW]
RAS
7
CAS 23
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W
OE
6
22
DQ0 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
functional block diagram (TMS416809)
RAS
CAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
Column Address
Buffers
256K Array
R
o
w
A8
Row Address
Buffers
8
8
I/O
Buffers
D
e
c
o
d
e
12
DataIn
Reg.
256K Array
64
DataOut
Reg.
256K Array
A9 –
A11
8
8
DQ0 – DQ7
12
functional block diagram (TMS417809)
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
Column Address
Buffers
256K Array
256K Array
A9
Row Address
Buffers
A10
256K Array
R
o
w
11
256K Array
8
32
POST OFFICE BOX 1443
I/O
Buffers
DataOut
Reg.
8
8
DQ0 – DQ7
256K Array
11
6
DataIn
Reg.
256K Array
D
e
c
o
d
e
32
8
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
V
Low-level input voltage (see Note 2)
–1
0.8
V
Supply voltage
0
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
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7
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416809
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
ICC1‡§
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
ICC2
Standby current
IOH = – 5 mA
’416809 - 60
MIN
’416809 - 70
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
’416809 - 80
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
± 10
± 10
± 10
µA
80
70
60
mA
VIH = 2.4 V ( TTL),
After 1 memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
1
1
1
mA
ICC3‡§
Average refresh current
(RAS-only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
80
70
60
mA
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
90
80
70
mA
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
8
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TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417809
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current (leakage)
IO
ICC1‡§
ICC2
’417809 - 60
MIN
’417809 - 70
MAX
2.4
MIN
’417809 - 80
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
110
100
90
mA
VIH = 2.4 V ( TTL),
After 1 memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
1
1
1
mA
110
100
90
mA
90
80
70
mA
Standby current
ICC3‡§
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
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9
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
7
pF
Co
Output capacitance
† A11 is NC (no internal connection) for TMS417809.
NOTE 3: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
PARAMETER
’41x809-60
’41x809-70
’41x809-80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS
15
18
20
ns
tCPA
tRAC
Access time from CAS precharge
35
40
45
ns
Access time from RAS
60
70
80
ns
tOEA
tCLZ
Access time from OE
20
ns
Delay time, CAS to output in low impedance
0
tREZ
tCEZ
Output buffer turn off delay from RAS (see Note 5)
3
15
3
18
3
20
ns
Output buffer turn off delay from CAS (see Note 5)
3
15
3
18
3
20
ns
tOEZ
tWEZ
Output buffer turn off delay from OE (see Note 5)
3
15
3
18
3
20
ns
Output buffer turn off delay from W (see Note 5)
3
15
3
18
3
20
ns
15
18
0
0
ns
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
5. Maximum tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven.
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x809-60
’41x809-70
’41x809-80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tHPC
tPRWC
Cycle time, EDO page mode, read-write
25
30
35
ns
Cycle time, EDO read-write
80
90
100
ns
tCSH
tCHO
Delay time, RAS active to CAS precharge
50
55
60
ns
Hold time, OE from CAS
10
10
10
ns
tDOH
tCAS
Hold time, output from CAS
3
Pulse duration, CAS active
10
tWPE
tOCH
Pulse duration, W active (output disable only)
tCP
tOEP
3
10 000
3
10 000
15
ns
10 000
ns
5
5
5
ns
10
10
10
ns
Pulse duration, CAS precharge
5
5
5
ns
Precharge time, OE
5
5
5
ns
Setup time, OE before CAS
NOTE 4: With ac parameters, it is assumed that tT = 5 ns.
10
12
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TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x809-60
MIN
’41x809-70
MAX
MIN
MAX
’41x809-80
MIN
MAX
UNIT
tRC
tRWC
Cycle time, random read or write
110
130
150
ns
Cycle time, read-write
150
175
200
ns
tRASP
tRAS
Pulse duration, RAS active, fast page mode (see Note 6)
60 100 000
70
100 000
Pulse duration, RAS active, non-page mode (see Note 6)
60
70
10 000
tRP
tWP
Pulse duration, RAS precharge
40
50
60
ns
Pulse duration, write command
10
10
10
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 7)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CAS precharge
10
12
15
ns
Setup time, write command before RAS precharge
10
12
15
ns
tWCS
tCSR
Setup time, write command before CAS active (early-write only)
0
0
0
ns
5
5
5
ns
tCAH
tDH
Hold time, column address
10
12
15
ns
Hold time, data in (see Note 7)
10
12
15
ns
tRAH
tRCH
Hold time, row address
10
10
10
ns
0
0
0
ns
tRRH
tWCH
Hold time, read command referenced to RAS (see Note 8)
0
0
0
ns
Hold time, write command during CAS active ( early-write only )
10
12
15
ns
tROH
Hold time, RAS referenced to OE
10
10
10
ns
tCHR
Hold time, CAS referenced to RAS ( CBR refresh
only )
15
15
20
ns
tOEH
tAWD
Hold time, OE command
15
18
20
ns
Delay time, column address to write command ( read-write only )
55
63
70
ns
tCRP
tCWD
Delay time, CAS precharge to RAS
0
0
0
ns
Delay time, CAS to write command ( read-write only )
40
46
50
ns
tOED
tRAD
Delay time, OE to data in
15
18
20
ns
Delay time, RAS to column address
15
tRAL
tCAL
Delay time, column address to RAS precharge
30
35
40
ns
Delay time, column address to CAS precharge
20
25
30
ns
tRCD
tRPC
Delay time, RAS to CAS ( see Note 9)
20
tRSH
tRWD
tREF
Setup time, CAS referenced to RAS ( CBR refresh only )
Hold time, read command referenced to CAS (see Note 8)
Delay time, RAS precharge to CAS
10 000
30
45
15
20
0
0
Delay time, CAS active to RAS precharge
10
Delay time, RAS to write command (read-write only)
85
Refresh time interval
35
52
80 100 000
ns
80
ns
15
20
10 000
40
60
ns
12
15
ns
98
110
ns
64
64
64
’417809
32
32
32
POST OFFICE BOX 1443
2
30
• HOUSTON, TEXAS 77251–1443
ns
0
’416809
tT
Transition time
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
6. In a read-write cycle, tRWD and tRWL must be observed.
7. Referenced to the later of CAS or W in write operations
8. Either tRRH or tRCH must be satisfied for a read cycle.
9. The maximum value is specified only to ensure access time.
ns
2
30
2
30
ms
ns
11
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
1.31 V
5V
218 Ω
828 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
12
295 Ω
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tRAD
tCP
tASC
tRAH
Address
Row
tCAL
tRAL
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ0 – DQ7
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tRAL
tRAH
Address
tCAH
Row
Don’t Care
Column
tCWL
tRAD
tRWL
tWCH
W
tWCS
Don’t Care
Don’t Care
tWP
tDH
tDS
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
tRAH
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
tRWL
W
Don’t Care
Don’t Care
tWP
tDS
tDH
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 4. Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Column
Don’t Care
tCWL
tRCS
tRWL
tRWD
tWP
tAWD
tCWD
Don’t Care
W
tCAC
tDS
tAA
tDH
tCLZ
DQ0 – DQ7
Hi-Z
Data
Out
See Note A
tRAC
Data
In
tOEZ
tOEA
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tRP
tT
tRCD
tRSH
tCSH
tCRP
tHPC
tCAS
CAS
tCP
tRAH
tASC
tCAL
tASR
tRAL
tCAH
Address
Row
Column #1
Column #2
Column #3
tRAD
tRCH
tOEA
OE
tRCS
tCAC
tRRH
tDOH
W
tCAC
tAA
tAA
tCEZ
tCPA
tRAC
tREZ
tCLZ
DQ0 – DQ7
DATA #1
DATA #2
DATA #3
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is tCPA- or tAA-dependent.
Figure 6. Extended-Data-Out Read Cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tHPC
tCP
tCAS
CAS
tRSH
tASR
tRAH
tCAL
tASC
tRAL
tCAH
Row
Address
Column #1
Column #2
Column #3
tRAD
tOCH
tCHO
tOEP
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
tCAC
W
tDOH
tCLZ
tOEZ
tCAC
tREZ
tOEZ
tRAC
DQ0 – DQ7
tCEZ
tCPA
tAA
tAA
DATA #1
DATA #1
DATA #2
Figure 7. Extended-Data-Out Read-Cycle With OE Control
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DATA #3
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tRP
tCSH
tHPC
tCRP
tRSH
tCP
tCAS
CAS
tASR
tRAH
tASC
Address
Row
tCAH
tCAL
Column #1
tRAL
Column #3
Column #2
tRAD
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCPA
tCLZ
tAA
tCPA
tCEZ
tAA
tREZ
tRAC
DQ0 – DQ7
DATA #1
DATA #2
DATA #3
Figure 8. Extended-Data-Out Read-Cycle With W Control
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRCD
tHPC
tCAS
tASC
CAS
tRAH
tCP
tCAH
tRAL
tASR
Address
tCRP
tRSH
Row
tCAL
Column
tCWL
tCWL
tRAD
tWP
W
Don’t Care
Column
Don’t Care
tRWL
Don’t Care
Don’t Care
tDH
tDS
DQ0 – DQ7
Data In
Data In
Don’t Care
Don’t Care
OE
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 9. EDO-Early-Write-Cycle Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tHPC
tRCD
tCAS
tASC
CAS
tRAH
tCP
tCAH
tRAL
tASR
Address
tCRP
tRSH
tCAL
Row
Column
Don’t Care
Column
tCWL
tCWL
tRAD
tWP
W
Don’t Care
tRWL
Don’t Care
Don’t Care
tDH
tOEH
tDS
Data In
DQ0 – DQ7
tOEH
Data In
tOED
Don’t Care
OE
Don’t Care
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 10. EDO-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
CAS
tCRP
tCP
tCAS
tASR
tASC
tCAL
tCAH
tRAL
tRAD
Row
Address
Column 1
Column 2
Don’t Care
tRAH
tCWL
tCWD
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
See Note A
tDS
tCAC
Valid
In 1
DQ0 – DQ7
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOEH
tOED
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 11. EDO Read-Write-Cycle Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
CAS
Don’t Care
tRPC
tRAH
tASR
Address
Don’t Care
Row
Don’t Care
Row
Don’t Care
W
DQ0 – DQ7
Hi Z
Don’t Care
OE
Figure 12. RAS-Only Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tRPC
CAS
tCSR
tCHR
tT
W
Don’t Care
Address
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ7
Figure 13. Automatic-CBR-Refresh-Cycle Timing
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tRRH
tRCS
Don’t Care
W
tCAC
tREZ
tAA
tCEZ
tRAC
Valid Data Out
DQ0 – DQ7
tCLZ
OE
tOEZ
tOEA
Figure 14. Hidden-Refresh Cycle (Read)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Memory Cycle
Refresh Cycle
tRAS
Refresh Cycle
tRP
tRAS
tRP
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tRRH
tWCS
tWP
W
Don’t Care
tDS
tWCH
tDH
DQ0 – DQ7
Valid Data
Don’t Care
Don’t Care
OE
Figure 15. Hidden-Refresh Cycle (Write) Timing
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J28)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.730 (18,54)
0.720 (18,29)
28
15
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
14
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.020 (0,51)
0.007 (0,18) M
0.016 (0,41)
0.004 (0,10)
0.380 (9,65)
0.360 (9,14)
0.008 (0,20) NOM
0.050 (1,27)
4040094-3 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416809 illustrated)
TI
-SS
Speed ( - 60, - 70, - 80)
TMS416809
W
C
Y
DZ
M LLLL P
Package Code
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
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