TI TMS426400P

TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
D
D
D
D
D
D
D
D
D
D
D
Electrical characteristics for TMS416400/P and
TMS417400/P is Production Data. Electrical
characteristics
for
TMS426400/P
and
TMS427400/P is Product Preview only.
Organization . . . 4 194304 × 4
Single 5 V Power Supply for TMS41x400 / P
(±10% Tolerance)
Single 3.3 V Power Supply for
TMS42x400/ P (± 0.3 V Tolerance)
Performance Ranges:
’4xx400/P-60
’4xx400/P-70
’4xx400/P-80
DJ PACKAGE
( TOP VIEW )
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR) Refresh
Long Refresh Period and Self-Refresh
Option ( TMS4xx400P)
3-State Unlatched Output
Low Power Dissipation
High-Reliability Plastic 24 / 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package and 24 / 26-Lead
Surface-Mount Thin Small-Outline Package
( TSOP)
Operating Free-Air Temperature Range:
0°C to 70°C
EPIC (Enhanced Performance Implanted
CMOS) Technology
VCC
DQ1
DQ2
W
RAS
A11†
1
2
3
4
5
26
25
24
23
22
6
21
A10
A0
A1
A2
A3
VCC
8
19
9
10
11
12
13
18
17
16
15
14
DGA PACKAGE
( TOP VIEW )
VSS
DQ4
DQ3
CAS
OE
A9
VCC
DQ1
DQ2
W
RAS
A11†
1
2
3
4
5
26
25
24
23
22
6
21
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VCC
8
19
9
10
11
12
13
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A11†
CAS
DQ1 – DQ4
OE
NC
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
Output Enable
No Internal Connection
Row-Address Strobe
5-V or 3.3-V Supply‡
Ground
Write Enable
† A11 is NC for TMS4x7400 / P.
‡ See Available Options Table
description
AVAILABLE OPTIONS
The TMS4xx400 is a set of high-speed,
16 777 216-bit dynamic random-access memories
organized as 4 194 304 words of 4 bits each. The
TMS4xx400P series are high-speed, low-power,
self-refresh, 16 777 216-bit dynamic randomaccess memories organized as 4 194 304 words of
4 bits each. The TMS4xx400 and TMS4xx400P
employ state-of-the-art EPIC (Enhanced
Performance Implanted CMOS) technology for
high performance, reliability, and low power.
DEVICE
POWER
SUPPLY
SELF
REFRESH
BATTERY
BACKUP
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426400
TMS426400P
TMS427400
TMS427400P
5V
5V
5V
5V
3.3 V
3.3 V
3.3 V
3.3 V
—
Yes
—
Yes
—
Yes
—
Yes
REFRESH
CYCLES
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
description (continued)
The TMS4xx400 and TMS4xx400P are each offered in a 24 / 26-lead plastic surface-mount TSOP (DGA suffix)
package and a 24 / 26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized
for operation from 0°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by tRASP, the maximum RAS low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column
address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max
(access time from CAS low) if tAA max (access time from column address) and tRAC have been satisfied. In the
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of tCPA or tCAC.
address: A0 – A11 ( TMS4x6400/ P) and A0 – A10 (TMS4x7400 / P)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. For the TMS4x6400 and
TMS4x6400P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11
row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address
bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS.
RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip select, activating the output buffers and latching the address bits into the column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ1 – DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of CAS) as long as tRAC and tAA are satisfied.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
RAS-only refresh
TMS4x6400, TMS4x6400P
A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This
can be achieved by strobing each of the 4096 rows (A0 – A11). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
TMS4x7400, TMS4x7400P
A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This
can be achieved by strobing each of the 2048 rows (A0 – A10). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored, and the refresh address is generated internally.
battery-backup refresh
TMS4x6400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V ) or 350 µA (3.3 V ) refresh current
is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25 µs while
holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
( VIL < 0.2 V, VIH > VCC – 0.2 V ).
TMS4x7400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V ) or 350 µA (3.3 V ) refresh current
is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5 µs while
holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
( VIL < 0.2 V, VIH > VCC – 0.2 V ).
self refresh ( TMS4xx400P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refresh a
full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures
the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. During
a write cycle, the data states of all four DQs must be the same to ensure proper function of the test mode. Test
time is reduced by a factor of four for this series.
Exit Cycle
Entry Cycle
Test Mode Cycle
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Normal
Mode
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11‡
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
RAM 4096 K × 4
20D10/21D0
15
16
17
18
19
21
8
6
5
25
4
22
2
3
24
25
A
0
4 194 303
20D19/21D9
20D20
20D21
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
A,22D
26
23C22
24,25 EN
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
‡ A11 is NC for TMS4x7400 and TMS4x7400P.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
functional block diagram
TMS4x6400/ P
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
ColumnAddress
Buffers†
R
o
w
A11
RowAddress
Buffers
4
256K Array
4
D
e
c
o
d
e
12
DataIn
Reg.
256K Array
I/O
Buffers
64
4
4
DataOut
Reg.
256K Array
DQ1 – DQ4
12
† Column addresses A10 and A11 are not used.
TMS4x7400/ P
RAS
CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
256K Array
256K Array
A10
32
RowAddress
Buffers
11
4
256K Array
R
o
w
D
e
c
o
d
256K Array e 256K Array
4
32
11
6
POST OFFICE BOX 1443
DataIn
Reg.
256K Array
• HOUSTON, TEXAS 77251–1443
I/O
Buffers
4
4
DataOut
Reg.
DQ1 – DQ4
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC:
TMS41x400, TMS41x400P . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x400, TMS42x400P . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1):
TMS41x400, TMS41x400P . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x400, TMS42x400P . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS41x400
TMS42x400
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
3
3.3
3.6
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
2
Low-level input voltage (see Note 2)
–1
0.8
– 0.3
Supply voltage
0
0
UNIT
V
V
VCC + 0.3
0.8
V
V
TA
Operating free-air temperature
0
70
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416400/ P
PARAMETER
’416400 - 60
’416400P - 60
TEST CONDITIONS†
MIN
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1‡§
MAX
2.4
MIN
MAX
2.4
’416400 - 80
’416400P - 80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
80
70
60
mA
2
2
2
mA
1
1
1
mA
500
500
500
µA
VIH = 2.4 V ( TTL),
After 1 memory cycle,
RAS and CAS high
ICC2
’416400 - 70
’416400P - 70
Standby current
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle
cycle,
RAS and CAS high
’416400
’416400P
ICC3‡§
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
80
70
60
mA
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
70
60
50
mA
ICC6#
Self-refresh current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
500
500
500
µA
ICC10#
Battery back-up
operating current
(equivalent refresh
time is 128 ms); CBR
only
tRC = 31.25 µs,
tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
500
500
500
µA
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
# For TMS416400P only
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417400/ P
PARAMETER
’417400 - 60
’417400P - 60
TEST CONDITIONS†
MIN
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1‡§
MAX
2.4
MIN
MAX
2.4
’417400 - 80
’417400P - 80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Read- or
write-cycle current
VCC = 5.5 V,
Minimum cycle
110
100
90
mA
2
2
2
mA
1
1
1
mA
500
500
500
µA
110
100
90
mA
70
60
50
mA
VIH = 2.4 V ( TTL),
After 1 memory cycle,
RAS and CAS high
ICC2
’417400 - 70
’417400P - 70
Standby current
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle
cycle,
RAS and CAS high
’417400
’417400P
ICC3‡§
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4‡¶
Average page
current
VCC = 5.5 V,
RAS low,
ICC6#
Self-refresh current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
500
500
500
µA
ICC10#
Battery back-up
operating current
(equivalent refresh
time is 128 ms);
CBR only
tRC = 62.5 µs,
tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
500
500
500
µA
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
# For TMS417400P only
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
TMS426400/ P
PARAMETER
’426400 - 60
’426400P - 60
TEST CONDITIONS†
MIN
’426400 -70
’426400P -70
MAX
MIN
MAX
UNIT
MAX
PRODUCT PREVIEW
High-level
g
output voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
VOL
Low-level
output voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
0.4
0.4
0.4
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
IO
Output current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1‡§
Read- or writecycle current
VCC = 3.6 V,
Minimum cycle
70
60
50
mA
1
1
1
mA
’426400
500
500
500
µA
’426400P
200
200
200
µA
Standby
current
LVCMOS
VIH = 2 V (LVTTL),
After 1 memory cycle,
RAS and CAS high
VIH = VCC – 0.2 V
((LVCMOS),
),
After 1 memory cycle,
RAS and CAS high
2.4
MIN
VOH
ICC2
2.4
’426400 - 80
’426400P - 80
VCC – 0.2
2.4
VCC – 0.2
V
VCC – 0.2
V
ICC3‡§
Average
refresh current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
70
60
50
mA
ICC4‡¶
Average page
current
VCC = 3.6 V,
RAS low,
60
50
40
mA
ICC6#
Self-refresh
current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
250
250
250
µA
ICC10#
Battery
back-up
operating
current
(equivalent
refresh time is
128 ms),
CBR only
tRC = 31.25 µs, tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
350
350
350
µA
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
# For TMS426400P only
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
TMS427400/ P
’427400 - 60
’427400P - 60
TEST CONDITIONS†
MIN
’427400 -70
’427400P -70
MAX
MIN
MAX
UNIT
MAX
High-level
g
output voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
VOL
Low-level
output voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
0.4
0.4
0.4
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
IO
Output current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1‡§
Read- or writecycle current
VCC = 3.6 V,
Minimum cycle
100
90
80
mA
1
1
1
mA
’427400
500
500
500
µA
’427400P
200
200
200
µA
100
90
80
mA
60
50
40
mA
Standby
current
LVCMOS
VIH = 2 V (LVTTL),
After 1 memory cycle,
RAS and CAS high
VIH = VCC – 0.2 V
((LVCMOS),
),
After 1 memory cycle,
RAS and CAS high
2.4
MIN
VOH
ICC2
2.4
’427400 - 80
’427400P - 80
VCC – 0.2
2.4
VCC – 0.2
V
VCC – 0.2
V
ICC3‡§
Average
refresh current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
ICC4‡¶
Average page
current
VCC = 3.6 V,
RAS low,
ICC6#
Self-refresh
current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
250
250
250
µA
ICC10#
Battery
back-up
operating
current
(equivalent
refresh time is
128 ms),
CBR only
tRC = 62.5 µs,
tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
350
350
350
µA
tPC = MIN,
CAS cycling
PRODUCT PREVIEW
PARAMETER
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
# For TMS427400P only
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
7
pF
Co
Output capacitance
NOTE 3: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’4xx400 - 60
’4xx400P - 60
MIN
MAX
’4xx400 - 70
’4xx400P - 70
MIN
MAX
’4xx400 - 80
’4xx400P - 80
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 4)
30
35
40
ns
Access time from CAS low (see Note 4)
15
18
20
ns
tCPA
tRAC
Access time from column precharge (see Note 4)
35
40
45
ns
Access time from RAS low (see Note 4)
60
70
80
ns
tOEA
tCLZ
Access time from OE low (see Note 4)
15
18
20
ns
Delay time, CAS low to output in low-impedance state
0
0
0
ns
tOH
tOHO
Output data hold time (from CAS)
3
3
3
ns
Output data hold time (from OE)
3
3
3
ns
tOFF
tOEZ
Output disable time after CAS high (see Note 5)
0
15
0
18
0
20
ns
Output disable time after OE high (see Note 5)
0
15
0
18
0
20
ns
NOTES: 4. Access times for TMS42x400 measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. tOFF and tOEZ are specified when the output is no longer driven.
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
tRC
tWC
Cycle time, read (see Note 6)
tRWC
tPC
’4xx400 - 60
’4xx400P - 60
’4xx400 - 70
’4xx400P - 70
’4xx400 - 80
’4xx400P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
110
130
150
ns
Cycle time, write (see Note 6)
110
130
150
ns
Cycle time, read-write (see Note 6)
155
181
205
ns
Cycle time, page-mode read or write (see Notes 6 and 7)
40
45
50
ns
tPRWC
tRASP
Cycle time, page-mode read-write (see Note 6)
85
96
105
ns
Pulse duration, RAS low, page mode (see Note 8)
60 100 000
70 100 000
80 100 000
ns
tRAS
tCAS
Pulse duration, RAS low, nonpage mode (see Note 8)
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS low (see Note 9)
15
10 000
18
10 000
20
10 000
ns
tCP
tRP
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
tWP
tASC
Pulse duration, W low
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
tASR
tDS
Setup time, row address before RAS low
0
0
0
ns
Setup time, data (see Note 10)
0
0
0
ns
tRCS
tCWL
Setup time, W high before CAS low
0
0
0
ns
Setup time, W low before CAS high
15
18
20
ns
tRWL
tWCS
Setup time, W low before RAS high
15
18
20
ns
0
0
0
ns
tWRP
tWTS
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Setup time, W low before RAS low (test mode only)
10
10
10
ns
tCAH
tDH
Hold time, column address after CAS low
10
15
15
ns
Hold time, data (see Note 10)
10
15
15
ns
tRAH
tRCH
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 11)
0
0
0
ns
tRRH
tWCH
Hold time, W high after RAS high (see Note 11)
0
0
0
ns
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
tRHCP
tOEH
Hold time, RAS high from CAS precharge
35
40
45
ns
Hold time, OE command
15
18
20
ns
tROH
tCHS
Hold time, RAS referenced to OE
tWRH
tWTH
Setup time, W low before CAS low (early-write operation only)
10
10
10
ns
– 50
– 50
– 50
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
Hold time, W low after RAS low (test mode only)
10
10
10
ns
Hold time, CAS low after RAS high (self refresh)
NOTES: 6.
7.
8.
9.
10.
11.
All cycle times assume tT = 5 ns.
To assure tPC min, tASC should be ≥ to tCP .
In a read-write cycle, tRWD and tRWL must be observed.
In a read-write cycle, tCWD and tCWL must be observed.
Referenced to the later of CAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4xx400 - 60
’4xx400P - 60
MIN
MAX
’4xx400 - 70
’4xx400P - 70
MIN
MAX
’4xx400 - 80
’4xx400P - 80
MIN
UNIT
MAX
tAWD
tCHR
Delay time, column address to W low (read-write operation only)
55
63
70
ns
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
tCRP
tCSH
Delay time, CAS high to RAS low
5
5
5
ns
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
tCWD
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
Delay time, CAS low to W low (read-write operation only)
40
46
50
ns
tOED
tRAD
Delay time, OE to data
15
18
20
ns
Delay time, RAS low to column address (see Note 12)
15
tRAL
tCAL
Delay time, column address to RAS high
30
Delay time, column address to CAS high
30
tRCD
tRPC
Delay time, RAS low to CAS low (see Note 12)
20
Delay time, RAS high to CAS low
0
0
tRSH
tRWD
Delay time, CAS low to RAS high
15
Delay time, RAS low to W low (read-write operation only)
85
tCPW
tRASS
Delay time, W low after CAS precharge (read-write operation only)
tRPS
tTAA
tTCPA
tTRAC
35
35
20
40
40
35
45
15
ns
40
52
20
ns
ns
60
ns
ns
18
20
ns
98
110
ns
60
68
75
ns
Pulse duration, self-refresh entry from RAS low
100
100
100
µs
Pulse duration, RAS precharge after self refresh
110
130
150
ns
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
Access time from RAS (test mode)
65
75
85
ns
’4x6400P
Refresh time interval
’4x7400
’4x7400P
tT
Transition time
NOTE 12: The maximum value is specified only to assure access time.
14
15
0
’4x6400
tREF
30
POST OFFICE BOX 1443
64
64
64
128
128
128
32
32
32
128
3
• HOUSTON, TEXAS 77251–1443
30
128
3
30
ms
128
3
30
ns
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
VTH
VCC
RL
R1
Output Under Test
Output Under Test
(a) LOAD CIRCUIT
DEVICE
R2
CL = 100 pF
CL = 100 pF
(b) ALTERNATE LOAD CIRCUIT
R1 (Ω )
R2 (Ω )
’41x400 / P
VCC ( V )
5
RL (Ω )
295
VTH ( V )
1.31
828
’42x400 / P
3.3
1178
868
1.4
500
218
Figure 2. Load Circuits for Timing Parameters
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tCP
tRAD
tASC
tRAH
tCAL
tRAL
Address
Row
Column
Don’t Care
tRCS
W
tRRH
tRCH
tCAH
Don’t Care
Don’t Care
tCAC
tOFF
tOH
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tOHO
tOEA
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
tCAL
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
tASR
tASC
CAS
tCP
tRAL
tRAH
Address
tCAH
Row
tCWL
tRWL
tWCH
tRAD
W
Don’t Care
Column
Don’t Care
Don’t Care
tWCS
tWP
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tRAL
tCAL
tRAH
tCAH
Address
Row
Column
tCWL
tRAD
W
Don’t Care
tRWL
Don’t Care
Don’t Care
tWP
tDS
tDH
DQ1 – DQ4
Don’t Care
Valid Data
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
Figure 5. Write-Cycle Timing
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
tCAC
tCLZ
DQ1 – DQ4
tDH
Data
Out
See Note A
tOEA
tDS
tAA
tRAC
OE
Don’t Care
tAWD
tCWD
W
tOHO
Data
In
tOEZ
Don’t Care
tOEH
tOED
Don’t Care
Don’t Care
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tRCD
tPC
tCSH
tRAH
tASR
tASC
Row
tCAL
tCAH
tRAL
Don’t Care
Column
Column
tAA†
tRRH
tRCH
tRCS
W
tCRP
tCAS
CAS
Address
tRSH
tCP
tCAC†
tRAD
tCPA†
tCAC
tAA
tOFF
tOH
tRAC
tCLZ
DQ1 – DQ4
Valid
Out
Valid
Out
See Note A
tOHO
tOEZ
OE
tOEA
Don’t Care
tOEA
† Access time is tCPA, tCAC, or tAA dependent.
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tOHO
tOEZ
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
Don’t Care
Column
Column
tRAD
tCWL
tCWL
tRWL
tWP
W
Don’t Care
Don’t Care
tDH
tDH
tDS
(see Note A)
tDS
(see Note A)
DQ1 – DQ4
tOEH
Valid
In
Valid Data In
tOEH
Don’t Care
tOED
Don’t Care
OE
Don’t Care
Don’t Care
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRSH
tPRWC
tRCD
CAS
tCRP
tCP
tCAS
tASR
tASC
tRAD
tCAH
Row
Address
Column
Don’t Care
Column
tRAH
tCWL
tCWD
tAWD
tRWD
tCPW
tRWL
tWP
W
tCPA
tRCS
tOEH
tDH
tAA
tRAC
Valid Out†
tDS
tCAC
Valid
In
Valid
In
DQ1 – DQ4
tCLZ
Valid Out
tOEZ
tOEA
tOED
tOEH
OE
tOHO
† Output can go from high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
tRPC
Don’t Care
CAS
tASR
tRAH
Don’t Care
Address
Row
W
Don’t Care
DQ1 – DQ4
Don’t Care
OE
Don’t Care
Don’t Care
Row
Figure 10. RAS-Only Refresh Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
tWRH
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 11. Automatic-CBR-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tWRH
tRRH
tWRH
tWRH
tWRP
tWRP
tRCS
tWRP
W
tRAC
tCAC
tAA
tOFF
Valid Data Out
DQ1 – DQ4
tCLZ
tOEZ
tOEA
OE
Figure 12. Hidden-Refresh-Cycle (Read) Timing
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tRRH
tWRH
tWCS
tWRP
tWP
W
tWCH
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 13. Hidden-Refresh-Cycle ( Write) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPC
tRPS
tCSR
tCHS
CAS
tCP
Address
Don’t Care
tWRP
tWRH
W
Don’t Care
OE
Don’t Care
tOFF
DQ1 – DQ4
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tCHR
tRPC
tT
CAS
tWTH
tWTS
Don’t Care
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 15. Test-Mode-Entry-Cycle Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
Don’t Care
Don’t Care
tWRH
Address
Don’t Care
tOFF
DQ1 – DQ4
Hi-Z
Don’t Care
Figure 16. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.148 (3,76)
0.128 (3,25)
0.008 (0,20) NOM
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.275 (6,99)
0.260 (6,60)
0.050 (1,27)
4040092-3 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
MECHANICAL DATA
DGA (R-PDSO-G24/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
26
0.008 (0,21) M
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
1
13
0.679 (17,24)
0.671 (17,04)
Gage Plane
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.004 (0,10)
0.002 (0,05) MIN
4040265-3 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
device symbolization (TMS416400 illustrated)
TI
-SS
Speed ( - 60, - 70, - 80)
Low-Power / Self-Refresh Designator (Blank or P)
TMS416400 DJ
Package Code
W
B
Y
M LLLL P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
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