SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 D D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE description This 16-bit buffer/driver is designed for 3-V to 3.6-V VCC operation. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE The SN74LVCZ16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN74LVCZ16244A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic symbol† 1OE 2OE 1 EN1 48 25 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 40 1 2 8 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 recommended operating conditions (see Note 4) VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage VCC = 3 V to 3.6 V VCC = 3 V to 3.6 V Input voltage MIN MAX 3 3.6 2 V V 0.8 V 0 5.5 V High or low state 0 3-state 0 VCC 5.5 V –24 mA 24 mA VO Output voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 150 Operating free-air temperature –40 VCC = 3 V VCC = 3 V Low-level output current UNIT 10 ns/V µs/V 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 3 V to 3.6 V IOH = –100 µA IOH = –12 mA VOH IOH = –24 mA IOL = 100 µA VOL MIN 3V VCC–0.2 2.4 3V 2.2 TYP† UNIT V 3 V to 3.6 V IOL = 12 mA IOL = 24 mA MAX 0.2 V 3V 0.4 3V 0.55 ±5 µA II Ioff VI = 0 to 5.5 V VI or VO = 5.5 V 3.6 V 0 ±5 µA IOZ VO = 0 to 5.5 V 3.6 V ±5 µA IOZPU VO = 0.5 to 2.5 V, OE = don’t care 0 to 1.5 V ±5 µA IOZPD VO = 0.5 to 2.5 V, VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V‡ OE = don’t care 1.5 V to 0 ±5 µA One input at VCC – 0.6 V, Other inputs at VCC or GND ICC ∆ICC Ci IO = 0 100 36V 3.6 100 3 V to 3.6 V VI = VCC or GND Co VO = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This applies in the disabled state only. 100 µA µA 3.3 V 4.5 pF 3.3 V 6 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B B or A ten OE OE PARAMETER tdis 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 3.3 V ± 0.3 V UNIT MIN MAX 1.1 4.1 ns A or B 1 4.6 ns A or B 1.8 5.8 ns SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per buffer/driver POST OFFICE BOX 655303 Outputs enabled Outputs disabled • DALLAS, TEXAS 75265 f = 10 MHz TYP 32 5.5 UNIT pF 5 SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES277B – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open 500 Ω tw LOAD CIRCUIT VCC VCC Timing Input Input VCC/2 VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 VCC/2 0V tPLZ tPZL VCC Input VCC/2 VCC/2 0V tPLH VCC/2 VCC VCC/2 VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated