SLUS529 – MAY 2002
DESCRIPTION
FEATURES
D Enables Hot Swap in High Availability Optical
D
D
D
D
D
D
D
D
D
D
D
D
The TPS2346 Optical Network Hot Swap Power
Manager (HSPM) provides highly-integrated supply
control of three positive (3.3-V, 5-V, and 5.15-V) and one
negative (–5.2-V) supply rails with a minimum number
of external components. A linear current amplifier (LCA)
in each of the four device channels provides
closed-loop control of load current during insertion and
extraction events. This allows the designer to configure
the plug-in card’s maximum inrush slew rate and
magnitude according to the requirements of the system
supplies.
Network Systems
Programmable Current Slew Rate
Power Supply Sequencing
Sense Resistors Set Peak Current (IMAX)
Overcurrent Circuit Breaker at 2× IMAX
Precharge Output
Logic Low Power Good Output
Logic Low Enable Input
On-Chip Charge Pump
Low Sleep Mode Current
Undervoltage Lockout (UVLO)
Minimal External Parts Count
24-pin TSSOP Package
APPLICATIONS
D Hot Swap of ONET Modules
D Supply Power-Up/Power-Down Sequencing
TYPICAL APPLICATION
R1
Q1
PLUG–IN MODULE
5.15V
5.15 V
R2
2 mΩ
3 mΩ
5V
5V
R7
1.2 kΩ
D1
6.8 V
C1
0.1 µF
VIN1
CS1 GATE1
VS1
VIN2
CS2
ENABLE
ENABLE
CPUMP
RGND
GND
TPS2346
AGND
CPGND
IRAMP
C2
0.39 µF
PRECHG
VIN4
D2 6.8 V
C3
0.1 µF
VS2
PG
PG
GATE2
VS3
CS4 GATE4
VS4
VIN3
CS3
GATE3
3.3 V
3.3 V
R4
0.2 Ω
R5
10 kΩ
Q4
R3
2 mΩ
–5.2 V
Q3
–5.2 V
R8
10 Ω
RP
AD[00]
AD[XX:01]
BACK–END
POWER PLANES
R6
10 kΩ
BACKPLANE
Q2
BRIDGE DEVICE
EXAMPLE SIGNAL LINE
AD[00]
AD[XX:01]
ADDRESS/DATA BUS
UDG–02080
Copyright 2002, Texas Instruments Incorporated
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1
SLUS529 – MAY 2002
description (continued)
Fully programmed sequencing control ramps the back-end plane voltages in order, and during shutdown from
a healthy state, turns off the back-end supplies in the reverse order. In addition, electronic circuit breakers
provide continuous protection for the system supplies during the plug-in operation. The TTL/CMOS-compatible
ENABLE input and the board power good signal (PG) can interface directly to the individual backplane slot
control and status signals. A precharge pin (PRECHG) provides a 1-V bias supply for the I/O signals.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range, VIN1, VIN2, VIN3, ENABLE, PG, PRECHG . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
VS1, VS2, VS3, CS1, CS2, CS3 . . . . . –0.3 V to VIN +0.3 V of corresponding channel
CPUMP, GATE1, GATE2, GATE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 25 V
VIN4, VS4, GATE4, CS4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to 0.3 V
IRAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI(VIN1) +0.3 V
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.
Currents are positive into, and negative out of the specified terminal.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
TSSOP (PW)
–40_C to 85_C
TPS2346PW
{The PW package is available taped and reeled. Add TR suffix to device type
(e.g. TPS2346PWTR) to order quantities of 2,000 devices per reel and 90
units per tube.
PW PACKAGE
(TOP VIEW)
GATE1
VS1
VIN1
CS1
IRAMP
ENABLE
RGND
PRECHG
CS3
VIN3
VS3
GATE3
2
1
2
3
4
5
6
7
8
9
10
11
12
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24
23
22
21
20
19
18
17
16
15
14
13
GATE2
VS2
VIN2
CS2
CPUMP
CPGND
AGND
PG
CS4
VIN4
VS4
GATE4
SLUS529 – MAY 2002
electrical characteristics VI(VIN1) = 5.15 V, VI(VIN2) = 5 V, VI(VIN3) = 3.3 V, VI(VIN4) = –5.2 V,
TA = –40_C to 85_C (unless otherwise noted)
input supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ICC1
ICC2
Supply current, VIN1
6
8
Supply current, VIN2
1
2
ICC3
ICC4
Input current, VIN3
0.5
1
Input current, VIN4
–1.5
–3
ICC1(SLP)
ICC2(SLP)
Sleep mode current, VIN1
ICC3(SLP)
ICC4(SLP)
Sleep mode current, VIN3
Sleep mode current, VIN2
Sleep mode current, VIN4
VI(ENABLE) = 5 V
VI(ENABLE) = 5 V
0.5
VI(ENABLE) = 5 V
VI(ENABLE) = 5 V
100
UNIT
mA
1
µA
A
–400
charge pump
PARAMETER
VO(MAX)
ISOURCE
Maximum output voltage
ZO
Charge pump source impedance
Peak output current
TEST CONDITIONS
IO(CPUMP) = –25 µA
VO(CPUMP) = 15 V
MIN
TYP
17
1V
ǒIO (CPUMP+17 V)Ǔ * ǒIO (CPUMP+16 V)Ǔ
MAX
23
UNIT
V
–120
µA
200
kΩ
precharge output
PARAMETER
VO(PCHG)1
Output voltage
VO(PCHG)2
Output voltage, sourcing
TEST CONDITIONS
VI(VIN2) = 4 V,
VI(VIN2) = 4 V,
IO(PRECHG) = –5 mA
VI(VIN1/3/4) = 0 V
VI(VIN1/3/4) = 0 V,
VI(VIN1/3/4) = 0 V,
VI(VIN1/3/4) = 0 V
VO(PCHG)3
Output voltage, sinking
VI(VIN2) = 4 V,
IO(PRECHG) = 5 mA
tSTART
Startup time
VI(VIN2) = 4 V,
MIN
TYP
MAX
0.9
1
1.1
0.8
1
1.2
0.8
1
1.2
UNIT
V
µs
200
linear current amplifiers 1, 2, 3
PARAMETER
MIN
TYP
MAX
VMAX1
VMAX2
IMAX sense voltage (VIN1 – CS1)
TEST CONDITIONS
16
20
24
IMAX sense voltage (VIN2 – CS2)
16
20
24
VMAX3
IPK
IMAX sense voltage (VIN3 – CS3)
16
20
24
ISINK
IFAULT
Output current sink
Output current sink
Fault shutdown
VOL
VOH
Low-level output voltage
Fault shutdown,
High-level output voltage
IO(GATEx) = –4 µA
Output peak current
–25
UNIT
mV
–5
0.2
10
mA
150
IO(GATEx) = 10 mA
0.5
V
VCPUMP–1
linear current amplifier 4
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–75
–150
–225
mV
VMAX4
IMAX sense voltage (VIN4 – CS4)
IOL1
IOL2
Output leakage current
Fault shutdown
–10
10
Output leakage current
Sleep mode
–10
10
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A
µA
3
SLUS529 – MAY 2002
electrical characteristics VI(VIN1) = 5.15 V, VI(VIN2) = 5 V, VI(VIN3) = 3.3 V, VI(VIN4) = –5.2 V,
TA = –40_C to 85_C (unless otherwise noted) (continued)
overcurrent comparators 1, 2, 3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOC1
Overcurrent threshold voltage
(VIN1 – CS1)
34
45
56
VOC2
Overcurrent threshold voltage
(VIN2 – CS2)
29
40
51
VOC3
Overcurrent threshold voltage
(VIN3 – CS3)
29
40
51
tR
Response time
1
5
UNIT
mV
µs
overcurrent comparator 4
PARAMETER
VOC4
Overcurrent threshold voltage
(VIN4 – CS4) relative to VMAX4
tR
Response time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–50
–225
mV
1
5
µs
undervoltage (UV)
PARAMETER
MIN
TYP
MAX
VUV1
VUV2
Channel 1 undervoltage limit
TEST CONDITIONS
4.35
4.53
4.71
Channel 2 undervoltage limit
4.22
4.40
4.58
VUV3
VUV4
Channel 3 undervoltage limit
2.78
2.90
3.02
Channel 4 undervoltage limit
-4.76
-4.58
-4.30
MIN
TYP
MAX
UNIT
V
overvoltage (OV)
PARAMETER
TEST CONDITIONS
VOV1
VOV2
Channel 1 overvoltage limit
5.54
5.77
6.00
Channel 2 overvoltage limit
5.38
5.60
5.82
VOV3
VOV4
Channel 3 overvoltage limit
3.55
3.70
3.85
Channel 4 overvoltage limit
-7.00
-5.82
-5.54
MIN
TYP
MAX
–46
–58
–68
1.3
1.8
2.5
MIN
TYP
MAX
UNIT
V
IRAMP output
PARAMETER
ICHG
IDSG
Source current, charging
Sink current, discharging
TEST CONDITIONS
VO(IRAMP) = 0.5 V
VO(IRAMP) = 0.5 V
UNIT
µA
A
undervoltage lockout (UVLO)
PARAMETER
VUVLO–L
VUVLO–H
VIN1 UVLO, input rising
VHYS
VIN1 UVLO hysteresis
VIN1 UVLO, input falling
TEST CONDITIONS
VI(VIN2) = VI(VIN3) = VI(VIN4) = 0 V
UNIT
2.1
2.4
2.9
1.90
2.25
2.70
V
TYP
MAX
UNIT
0.05
ENABLE input
PARAMETER
VIL
VIH
Low-level input voltage
IIH
High-level input leakage current
4
TEST CONDITIONS
MIN
0.8
High-level input voltage
V
2
VI(ENABLE) = 5 V
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50
µA
SLUS529 – MAY 2002
electrical characteristics VI(VIN1) = 5.15 V, VI(VIN2) = 5 V, VI(VIN3) = 3.3 V, VI(VIN4) = –5.2 V,
TA = –40_C to 85_C (unless otherwise noted) (continued)
PG output
PARAMETER
TEST CONDITIONS
IOH
VOL
High–level output (leakage) current
Low-level output voltage
VI(ENABLE) = 5 V,
VI(ENABLE) = 0 V,
VOH = 5 V
ISINK = 0.1 mA
IOL
Low-level output (sink) current
VI(ENABLE) = 0 V,
VOL = 0.5 V
MIN
4
TYP
MAX
UNIT
1
µA
0.5
V
10
mA
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
18
I
Analog ground
ENABLE
6
I
Logic low enable input for back-end power
CPGND
19
I
Charge pump ground
CPUMP
20
I/O
CS1
4
I
Channel 1 (5.15-V) current sense input
CS2
21
I
Channel 2 (5-V) current sense input
CS3
9
I
Channel 3 (3.3-V) current sense input
CS4
16
I
Channel 4 (–5.2-V) current sense input
GATE1
1
O
Gate drive for Channel 1 (5.15-V) external pass FET
GATE2
24
O
Gate drive for Channel 2 (5-V) external pass FET
GATE3
12
O
Gate drive for Channel 3 (3.3-V) external pass FET
GATE4
13
O
Gate drive for Channel 4 (–5.2-V) external pass FET
PG
17
O
Open drain output asserted low for back-end power good
IRAMP
5
O
Current ramp programming pin
PRECHG
8
O
Bias supply of 1V for bus signal precharge
RGND
7
I
Reference ground
VIN1
3
I
Channel 1 supply (5.15-V) input voltage sense
VIN2
22
I
Channel 2 supply (5-V) input voltage sense
VIN3
10
I
Channel 3 supply (3.3-V) input voltage sense
VIN4
15
I
Channel 4 supply (–5.2-V) input voltage sense
VS1
2
I
5.15-V supply back-end voltage sense
VS2
23
I
5-V supply back-end voltage sense
VS3
11
I
3.3-V supply back-end voltage sense
VS4
14
I
–5.2-V supply back-end voltage sense
Charge pump resevoir capacitor connection
DISSIPATION RATING TABLE
PACKAGE
TSSOP (PW)
TA 25_C
800 mW
DERATING FACTOR
10 mW/_C
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TA = 85_C
200 mW
5
SLUS529 – MAY 2002
pin descriptions
AGND: Analog ground reference for the device.
CPGND: Charge pump ground pin for the device.
CPUMP: Charge pump resevoir capacitor connection. An external capacitor of value 0.1 µF to 1 µF must be
connected between this pin and CPGND. The capacitor provides charge storage for the internal charge pump
for gate drive of the external N-channel FETs in line with the three positive-voltage loads.
CS1, CS2, CS3: These pins tie to the load side of the Channel 1, 2, and 3 current sense resistors, respectively.
They are used in conjunction with the VIN1, VIN2 and VIN3 inputs to provide load current magnitude information
to each of the positive rail LCAs.
CS4: This pin ties to the more positive side of the Channel 4 current sense resistor (common with the pass FET
source). It is used in conjunction with the VIN4 input to provide Channel 4 current magnitude information to the
negative rail LCA.
ENABLE: Logic low enable input for back-end power. This pin ties to the module enable input at the plug-in
slot. When the input supplies are above the device minimums, and this pin is asserted low the TPS2346 begins
the sequential ramp–up of the back-end supplies. Pulling this input high (>2 V) turns off power to the back-end
planes, and puts the TPS2346 into low-power sleep mode.
GATE1, GATE2, GATE3, GATE4: Gate drive outputs for the Channel 1 through Channel 4 pass FETs,
respectively. The gates are driven according to the supply voltage, enable, sequence programming and load
current conditions of the add-in board.
IRAMP: Current ramp programming pin. A capacitor connected between this pin and ground determines the
maximum slew rate of the load current during ramp-up and ramp-down of the three positive back-end voltages.
This same capacitor is also used to establish the time limit for ramping each of the supply outputs.
PG: Open-drain output asserted low to signal a back-end power-good condition. During a turn-on event, if each
of the load rails ramps up successfully to within the factory-programmed tolerances of the undervoltage (UV)
and overvoltage (OV) comparators, this output is subsequently asserted low. The output is false when back-end
power is not enabled, if any of the back-end voltages is not within its UV/OV window, as a result of an overcurrent
indication on any supply controller, or as a result of a fault timeout during linear ramp-up of any load voltage.
PRECHG: Bias supply of 1 V for bus signal precharge. During plug-in insertion and extraction events, this
output provides a bias supply that can be used to precharge the signal and control lines of the system’s
address/data bus.
RGND: Reference ground input for the device.
VIN1: Channel 1 supply (5.15-V) input voltage sense. This pin is connected to the 5.15-V power supply input
to the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 5.15-V plane. The input supply also serves as the reference potential for the internally generated
current limit (IMAX) reference of the Channel 1 LCA. This pin also serves as the VCC supply for the TPS2346.
VIN2: Channel 2 supply (5-V) input voltage sense. This pin is connected to the 5-V power supply input to the
add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 5-V plane. The input supply also serves as the reference potential for the internally generated current
limit (IMAX) reference of the Channel 2 LCA. This pin also serves as the supply input for the precharge bias
output.
VIN3: Channel 3 supply (3.3-V) input voltage sense. This pin is connected to the 3.3-V power supply input to
the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 3.3-V plane. The input supply also serves as the reference potential for the internally generated
current limit (IMAX) reference of the Channel 3 LCA.
6
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SLUS529 – MAY 2002
pin descriptions (continued)
VIN4: Channel 4 supply (–5.2-V) input voltage sense. This pin is connected to the –5.2-V power supply input
to the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end –5.2-V plane. The input supply also serves as the reference potential for the internally generated
current limit (IMAX) reference of the Channel 4 LCA.
VS1, VS2, VS3: Voltage sense inputs for the positive back-end power busses. These pins connect to the source
nodes (load side) of the external pass FETs. After the programmed voltage ramp period for each supply, these
inputs are monitored to verify that the load voltages remain within the specified tolerances.
VS4: Voltage sense input for the negative back-end power bus. This pin connects to the drain (load side) of
the Channel 4 external pass FET. After the programmed voltage ramp period for the negative supply, this input
is monitored to verify that the load voltage remains within the specified tolerance.
functional overview
When an add-in printed circuit board (PCB) is inserted into a live chassis slot, the discharged supply bulk
capacitance on the board can draw huge transient currents from the system supplies. Limited only by the ESR
of the bulk capacitors and the impedance of the interconnect, these transients can reach sufficient magnitude
to cause immediate damage to connector pins, PCB etch and plug-in and supply components, or cause latent
defects reducing long-term reliability. In addition, current spikes can cause glitches on the power busses,
causing other boards in the system to reset.
The TPS2346 is designed to actively limit inrush current slew rate and magnitude during insertion and extraction
processes, in order to manage the safe, reliable hot swap of four supply voltages. N-channel MOSFETs in series
with each supply provide isolation between the system supply planes (the backplane) and the back-end power
planes during hot swap events. Back-end power refers to the switched side of a board’s power bus. With the
exception of the interface circuitry itself, all the board’s load (logic, processors, modules, etc) derives power
from the back-end planes. Consequently, the majority of the bulk capacitance is also on these planes. The in-line
FETs on each supply function as switches for the back-end power, and transition to a low-impedance supply
path once a board is fully seated and enabled, until such time as it is extracted. Low ohmic-value sense resistors
between each input and pass MOSFET feed back current information to the device. The TPS2346 uses load
current sensing along with the peripheral slot enable command, ENABLE, to determine the appropriate gate
drive status for each of the four MOSFETs. In this manner, the device provides for the controlled application of
power to and removal from the back-end planes.
The TPS2346 derives its VCC power from the 5.15–V supply; however, the absence of any one of the supplies,
including the VCC supply, causes the device to maintain pull-downs on the four gate pins, keeping the pass
MOSFETs off. A pull-up on the ENABLE pin, which should be provided on-board, also keeps the gate outputs
off even after all supply voltages are present. Once the plug-in is powered, a system-generated logic low signal
on the ENABLE input starts the turn-on of power to the back-end loads.
During a ramp-up sequence, the four supply inputs are validated against the pre-programmed undervoltage
(UV) and overvoltage (OV) thresholds. As each positive voltage load is enabled, current to the load is ramped
at a user-programmable rate, easily set by a capacitor on the current ramp control pin, IRAMP. The supplies
are sequenced up in the following order: 5.15-V, 5-V, 3.3-V and –5.2-V. The ramp of supply current on each
channel is limited to a maximum value, herein referred to as IMAX. The IMAX limit is individually selectable for
each channel, by selecting the appropriate value of the sense resistor. If the IMAX current level is attained on
any channel during an insertion, charging of that channel’s input bulk capacitance completes at that current limit,
as required.
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7
SLUS529 – MAY 2002
functional overview (continued)
As each back-end voltage is ramped, its level is validated to ensure it is within the established UV and OV
tolerances at the expiration of a programmable time period, protecting against start-up into faulted loads. The
same capacitor at the IRAMP pin which sets the current ramp rate is also used to establish this ramp-up time
limit. If all four supplies successfully reach a known good state, the PG output signal is pulled low to allow
enumeration of the add-in card.
To protect the backplane power bus, the TPS2346 provides an electronic circuit breaker that trips upon detecting
an overcurrent event. The detection threshold of an overcurrent event is internally set to approximately two
times (2x) IMAX. The –5.2-V channel also includes a circuit breaker function; its trip threshold is always a
minimum of 50 mV above the current-limit sense voltage. If any channel trips the circuit breaker, all supply
outputs are rapidly turned off, and remain latched off. Also, the PG output becomes high-impedance. The
TPS2346 can be reset by cycling either the ENABLE input or power to the device.
The low, 20-mV (150 mV on the –5.2-V channel) nominal sense voltage limit allows the use of low-value sense
resistors, or for high-current applications, the use of PC board copper trace. This helps minimize the insertion
loss across the hot swap interface. Further insertion loss reduction is achieved via the on-chip charge pump,
which ensures maximum gate overdrive on each of the three external pass MOSFETs on the positive supply
channels. This feature helps users obtain lower RDS(on) characteristics with their preferred N-channel
MOSFETs.
Under a normal PC board shutdown event, the TPS2346 also turns off power in a controlled manner. To initiate
a shutdown, ENABLE is brought to a logic high during a healthy supply state (outputs on and no faults present).
The supply outputs are then sequentially ramped off in the reverse order of the ramp-up sequence. After all
supply outputs are off, the TPS2346 goes into a low-current sleep mode.
8
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SLUS529 – MAY 2002
detailed description
The primary circuit blocks of the TPS2346 include internal supply generation, a charge pump, a state machine,
programmable ramp generator, precharge circuitry, and a ROM data cell. In addition, each of the four channels
contains a gate control block which includes the linear control amplifier (LCA), programmable current source,
and the voltage sense circuitry (see Figure 1). The gate drive blocks are virtually identical, except that the
Channel 4 block, controlling the negative voltage channel, adds some scaling and level shift circuitry to adjust
the polarity of the sense signals to that of the internal circuitry.
CS1
GATE1
VS1
CPGND
CPUMP
VS2
GATE2
CS2
4
1
2
19
20
23
24
21
SUPPLY
SECTION
CHARGE
PUMP
UVOV2
UVOV1
+
3
LCA/
V–SNS1
VIMAX1
OC1
CPOK
UVOV[4:1]
EN1
OC[4:1]
6
PG
17
VA
UVLO
/CHG
EN4
+
CH_SEL[4:1]
100 µS
/FLT
EN2
RAMP
GENERATOR
EN3
CPOK
VIMAX2
+
EN2
STATE
MACHINE
UVLO
2.5V
22 VIN2
LCA/
V–SNS2
OC2
VA
EN1
ENABLE
+
+
+
VIN1
VIN1
UP
EN
5
IRAMP
7
RGND
LEVEL[15:0]
FS
ORD[8:0]
VIN2
MUX 3
ROM
DATA
EN3
EN4
+
LCA/
V–SNS3
+
OC3
1V
UVOV3
+
OC4
PRE–
CHARGE
UVOV4
LCA/
VIMAX4
V–SNS4
+
+
VIMAX3
VIN3 10
DAC
LS
9
12
11
18
8
14
13
16
CS3
GATE3
VS3
AGND
PRECHG
VS4
GATE4
CS4
15 VIN4
Figure 1. TPS2346 block diagram
The supply generation block contains voltage regulators and references to generate the various bias voltages
used internally by the TPS2346. An undervoltage lockout (UVLO) function is used to ensure proper device
turn-on once the VIN1 input has attained the UVLO threshold of about 2.5 V. In addition, an on-chip charge pump
steps up the VIN1 input to generate the high voltage used by the LCAs to drive the pass MOSFET gates. Burst
regulation of the charge pump limits the output to about 20.5 V (peak), with about a 1-V hysteresis. During
steady-state load operation, sufficient gate overdrive is ensured to fully enhance the external MOSFETs, while
not exceeding the typical 20-V VGS rating of common N-channel MOSFETs.
The state machine block contains the logic to control the ramp-up and ramp-down sequencing, ramp generator
operation, and fault management. It uses voltage and current monitor outputs, along with the device enable
status and programmed order information to determine which channel is to be acted on, whether ramp-up,
ramp-down or steady-state operation is required, and the present healthy or faulted states of the back-end
supplies. A nominal 100–µS digital filter is applied to the ENABLE input to help protect against false triggering
in systems not implementing hardware connection control. The filter acts on both high-to-low and low-to-high
transitions of the enable input.
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SLUS529 – MAY 2002
detailed description (continued)
The ramp generator consists of a series of multiplexers feeding a digital-to-analog converter (DAC) circuit which
sets the magnitude of an internal current source. When active, the current source is used to establish a constant
value source or sink current at the IRAMP pin. This current is used to alternately charge and discharge a
capacitor connected between IRAMP and ground, generating a series of sawtooth timing pulses. During turn-on
of the back-end voltages, the capacitor is charged with a 58-µA current, then subsequently discharged with a
1.8-µA load. A comparator in the ramp generator circuit monitors the IRAMP voltage against two alternating
thresholds, such that the voltage charges up to 1.5 V and back down to 0 V. During the rising edge of this
waveform, the voltage at IRAMP is used to develop the reference threshold at the inverting input of the active
channel’s LCA. The other input is connected to the channel’s current sense (CSx) input. The LCA slews the
GATEx output to maintain the CSx pin at the reference value. Since the CSx voltage is developed as the drop
across the external sense resistor due to load current, the current to the load is therefore ramped at a linear rate
set by the dV/dt on the IRAMP pin. Therefore, inrush slew rate limiting is easily programmed by the user with
the IRAMP capacitor, CIRAMP. For Channel 4, internal device offsets may cause the inrush profile to deviate from
the programmed curve, particularly at initial turn-on. However, the maximum sourcing limit imposed by the
VMAX4 threshold still applies.
During a load turn-on, the current sense voltage, if required in order to fully charge the back-end plane, can track
the IRAMP waveform up to approximately 1.35 V on the IRAMP pin. If the charging current achieves that level,
the LCA reference is switched automatically to the fixed IMAX reference. Load charging then continues at that
fixed level until complete or until timer expiration, whichever occurs first. For Channels 1, 2 and 3, the IMAX level
has been set to 20 mV at the CSx pin, referenced to VINx. For Channel 4, the IMAX level is 150 mV.
The precharge circuitry is powered from the VIN2 supply input. Therefore, when the 5-V supply and GND pins
mate during an insertion, or until they break contact during an extraction, the precharge actively biases the bus
signal lines to 1.0 V. The precharge block consists of a 1-V reference generator and a unity gain amplifier. The
amplifier provides source and sink capability up to 5 mA.
The ROM data cell sets the configuration information for the TPS2346. These parameters include the order of
channel sequencing, the magnitude of the charge and discharge currents at IRAMP, and the nominal voltage
range of each channel. This information is all pre-programmed at the factory; no programming by the user is
necessary.
10
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SLUS529 – MAY 2002
detailed description (continued)
The basic functional blocks of the LCA/voltage sense circuits is shown in greater detail in Figure 2. The LCA
has as its inputs the reference voltage generated by the current sources, and the current sense input. During
a supply turn-on, it slews the pass MOSFET gate to force the load current to track the selected source. After
load charging completes, and the current decays to the nominal operating level, the LCA drives the GATEx
output to its input supply level, the charge pump output voltage.
VCPUMP
CSx
+
LCA
VINx
GATEx
MUX
2:1
VSx
R
VINX
R
VSEL
OCA
5
IRAMP
REF_Vx
VIMAX
10
5
DAC
DAC
OV
OCx
OV
UVOVx
UV
UV
UDG–02004
Figure 2. Linear Control Amplifier Block
The supply voltage is monitored by the undervoltage (UV) and overvoltage (OV) comparators. A voltage
multiplexer (MUX) selects from either the input supply voltage (VINx) or the load voltage (VSx), and provides
that signal to the comparator inputs. Once the Channel 1 supply is above the UVLO threshold, and the ENABLE
input has been pulled low, but prior to the ramp-up of the first channel, the comparators monitor the input
supplies. Any supply outside its UV/OV window causes all pass MOSFETs to be held off. If all inputs are within
tolerance, a ramp-up sequence can start, at which time the comparator inputs are switched over to the load,
or VSx, voltages. Within the state machine, monitoring of the ORed status of the UV and OV comparators of
any channel is enabled at the turn-on of the next channel, or approximately at the leading edge of the next
IRAMP pulse.
Finally, a fast overcurrent comparator (OCA in the diagram) also monitors the CSx input. This comparator
threshold is set to approximately 2 times the current limit threshold, (2 × IMAX) for the three positive supplies.
In the event of a short-circuit or other fast overcurrent event, the OCA trips, disabling the LCA, and causing
additional gate discharge paths to be turned on for a rapid shutdown of the loads.
A 1-µS to 2-µS filter is applied to all overcurrent and voltage faults to guard against nuisance trips. If the duration
of a fault condition on any one channel exceeds the filter length, the fault is latched, the open-drain device at
the PG output is turned off, and all four channels are shut down.
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SLUS529 – MAY 2002
TYPICAL CHARACTERISTICS
NORMAL TURN-OFF SEQUENCE
NORMAL TURN-ON SEQUENCE
ENABLE
(5 V/div)
IRAMP
(500 mV/div)
5.15VOUT
(2 V/div)
5VOUT
(2 V/div)
3.3VOUT
(2 V/div)
–5.2VOUT
(2 V/div)
PG
(5 V/div)
CIRAMP = 0.33 µF
CL1 = 690 µF
CL2 = 690 µF,
CL3 = 690 µF
CL4 = 69 µF
CIRAMP = 0.01 µF
CL1 = 690 µF
CL2 = 690 µF
CL3 = 690 µF
CL4 = 69 µF
RL1 = 2.5 Ω
RL2 = 2.5 Ω,
RL3 = 1.6 Ω
RL4 = 17 Ω
t – Time – 5 ms/div
t – Time – 10 ms/div
Figure 4
Figure 3
12
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SLUS529 – MAY 2002
TYPICAL CHARACTERISTICS
LOAD CURRENT LINEAR RAMP
EXAMPLE: 5.15-V LOAD
START-UP INTO A SHORT
ON 3.3 V LOAD
CIRAMP = 0.33 µF
CLOAD = 690 µF
RLOAD = 2.5 Ω
IRAMP (1 V/div)
IRAMP (1 V/div)
5.15VOUT (2 V/div)
5.15VOUT (2 V/div)
5VOUT (2 V/div)
5.15V_LOAD (1 A/div)
3.3VOUT
(200 mV/div)
t – Time – 1 ms/div
Figure 5
3.3V_LOAD
(2 A/div)
CIRAMP = 0.33 µF
CLOAD1 = 690 µF
RLOAD1 = 2.5 Ω
CLOAD2 = 690 µF
RLOAD2 = 2.5 Ω
RSNS2 = 2.5 mΩ
RSNS3 = 2.5 mΩ
3.3VOUT: Shorted
t – Time – 50 ms/div
Figure 6
.
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.
13
SLUS529 – MAY 2002
HIGH LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE, LCA1
UNDERVOLTAGE FAULT RESPONSE
5-V CHANNEL
25
VI(VIN1) = 5.15 V
IO(GATE1) = –4 µA
5VOUT (2 V/div)
GATE1 (10V/div)
CLOAD1 = 690 µF
RLOAD1 = 2.5 Ω
CLOAD2 = 100 µF
RLOAD2 = 2.5 Ω
GATE3 (10V/div)
VOH – GATE1 Voltage – V
20
CLOAD3 = 690 µF
RLOAD3 = 1.6 Ω
CLOAD4 = 69 µF
RLOAD4 = 17 Ω
15
10
5
GATE4 (2V/div)
0
t – Time – 5 µs/div
–40
Figure 8
Figure 7
14
–15
10
35
60
TA – Ambient Temperature – _C
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SLUS529 – MAY 2002
TYPICAL CHARACTERISTICS
HIGH LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE, LCA2
HIGH LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE, LCA3
25
25
VI(VIN1) = 5.15 V
IO(GATE3) = –4 µA
VI(VIN1) = 5.15 V
IO(GATE2) = –4 µA
20
VOH – GATE3 Voltage – V
VOH – GATE2 Voltage – V
20
15
15
10
10
5
5
0
0
–40
–15
10
35
60
TA – Ambient Temperature – _C
–40
85
–15
10
35
60
TA – Ambient Temperature – _C
Figure 10
Figure 9
HIGH LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE, LCA4
IRAMP OUTPUT CURRENT
vs
AMBIENT TEMPERATURE
0
–48
–1
ICHG – IRAMP Output Current – µA
VOH – GATE4 Voltage – V
85
–2
–3
–4
IO(GATE4) = –0.5 mA
–5
–40
–15
10
35
60
85
VO(IRAMP) = 0.5 V
Current Source Mode
–50
–52
–54
–56
–58
–60
–62
TA – Ambient Temperature – _C
–40
–15
10
35
60
85
TA – Ambient Temperature – _C
Figure 12
Figure 11
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SLUS529 – MAY 2002
TYPICAL CHARACTERISTICS
IRAMP INPUT CURRENT
vs
AMBIENT TEMPERATURE
IRAMP MODE TRIP THRESHOLD
vs
AMBIENT TEMPERATURE
2.4
1.56
VTRIP – IRAMP Trip Threshold – V
IDSG – IRAMP Input Current – µA
VI(IRAMP) = 0.5 V
Current Sink Mode
2.2
2.0
1.8
1.6
1.54
1.52
1.50
1.48
1.46
1.44
1.4
–40
–15
10
35
60
–40
85
TA – Ambient Temperature – _C
–15
10
35
60
TA – Ambient Temperature – _C
85
Figure 14
Figure 13
PRECHG OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
PRECHG OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
1.2
1.10
1.08
IO(PRECHG) =5mA
0.8
VO(PCHG) – Output Voltage – V
VO(PCHG) – Output Voltage – V
1.0
IO(PRECHG) = –5 mA
0.6
0.4
0.2
VI(VIN2) = 4 V
VI(VIN1) = VI(VIN3) = VI(VIN4) = 0 V
–15
10
35
60
85
TA – Ambient Temperature – _C
1.04
1.02
VI(VIN3) = 3.3 V
VI(VIN1) = VI(VIN4) = FLOAT
TA = 25_C
1.00
0.98
0.96
IOUT = –5 mA
0.94
0.90
4.0
4.5
5.0
5.5
VI(VIN2) – Input Voltage – V
Figure 16
Figure 15
16
IOUT = 5 mA
0.92
0.0
–40
1.06
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6.0
SLUS529 – MAY 2002
TYPICAL CHARACTERISTICS
PRECHARGE OUTPUT VOLTAGE
vs
OUTPUT CURRENT, SOURCING
PRECHARGE OUTPUT VOLTAGE
vs
OUTPUT CURRENT, SINKING
1.1
VO(PCHG) – Output Voltage – V
1.0
VO(PCHG) – Output Voltage – V
1.4
VI(VIN2) = 4.75 V
VI(VIN3) = 3.30 V
VI(VIN1) =VI(VIN4) = FLOAT
TA = 25_C
0.9
0.8
0.7
0.6
0.5
0.4
–8
–7
–5
–4
–3
–2
–1
IO(PCHG) – Output Current – mA
–6
0
VI(VIN2) = 5.25 V
VI(VIN3) = 3.30 V
VI(VIN1) =VI(VIN4) = FLOAT
TA = 25_C
1.3
1.2
1.1
1.0
0.9
0.8
0
2
4
6
8
10
12
14
IO(PCHG) – Output Current – mA
16
Figure 18
Figure 17
APPLICATION INFORMATION
The connections to set up the TPS2346 for operation in an ONET plug-in are shown in the typical application
diagram.The TPS2346 works in conjunction with four external N-channel MOSFETs to provide isolation of the
back-end power planes when disabled, and to provide a low-impedance power path when the load voltages are
at the full-input dc potential. For proper operation, each channel of the device must be connected to the
appropriate supply as listed in Table 1.
Table 1. TPS2346 Channel to Back-Plane Supply Connections
TPS2346
CHANNEL
BACKPLANE
SUPPLY
1
5.15 V
2
5V
3
3.3 V
4
–5.2 V
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SLUS529 – MAY 2002
APPLICATION INFORMATION
The TPS2346 is shown in the typical application diagram being used in conjunction with a connector providing
three levels of pin staging. Although not an absolute requirement for device operation, pin staging provides
several benefits to the overall performance of the hot swap circuit. In order to use the precharge function
provided by the TPS2346, a minimum of two levels of staging is needed. The precharge supply is derived from
the 5-V supply input (VIN2); therefore, this supply must be present at some time before the board’s bus lines
make contact with the backplane address/data bus in order to allow precharge before mating. A second benefit
of pin staging is it provides a mechanism for current-limited charging of the early power planes. Early power is
any plane which is on the unswitched side of the hot swap interface. Parasitic capacitance associated with the
interconnect system and the PCB planes, along with any bypass capacitance of the interface devices (e.g., the
hot swap controller, bus switches, the bridge device) appears on the input side of the connection hardware.
Therefore, it can still induce current spikes during hot swap even though the bulk capacitance is isolated. If
longer power pins are provided by the connector, they can be used for charging this smaller input capacitance
via simple resistive limiting. The resistors are subsequently bypassed when shorter power pins mate to establish
the low impedance power connection.
Finally, if a third level of staging is implemented, one of the shortest pins should be assigned to the ENABLE
input, as shown in the diagram. This helps ensure that all four supply voltages are stabilized at the controller
inputs before the ENABLE can be asserted. It also allows this input to be grounded on the backplane in systems
not implementing individual slot control of plug-in electrical connection status.
Sense resistors R1 through R4 connect between the VINx and CSx pins of their respective supplies, and
provide load current magnitude information to the TPS2346. To turn on the negative voltage channel, the device
pulls the gate of MOSFET Q4 towards ground potential. Resistor R5 provides a gate pull down when the LCA
turns off, as the Channel 4 LCA does not drive to the negative rail.
Resistor R7 provides a pull-up on the ENABLE pin. This should be provided on-board, so that it is present
regardless of the connection status of this pin during hot swap events. Resistor R6 provides a pull-up on the
open–drain PG signal; a 10-kΩ resistor should suffice for this function. These two pull-ups are shown connected
to the early 5.15-V supply; they could conceivably be connected to any of the positive early plane voltages. For
most reliable operation, R7 should be connected to any of the earliest power pins, if pin timing is established
via a staged-pin connector; otherwise, it should be tied to VIN1 as shown.
A capacitor with a value between 0.1 µF and 1 µF (C3 in the diagram) is required between the CPUMP pin and
ground. This capacitor provides charge storage for the on-board charge pump. A 0.1-µF ceramic is sufficient
for most applications.
ramp-up sequence
A successful ramp-up of the four back-end supplies consists of five pulses on the TPS2346 IRAMP pin. One
load voltage is ramped up during each of the first four IRAMP pulses. The fifth pulse enables the fault logic of
the last channel to turn on (Channel 4). This is shown graphically in Figure 19.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
ENABLE
1.5 V
1.35 V
VO(IRAMP)
0V
5.15 V
BACK-END
5.15-V
0V
5V
BACK-END
5-V
0V
3.3 V
BACK-END
3.3-V
0V
0V
BACK-END
–5.2-V
–5.2 V
PG
t0 t1 t2
t0:
t1:
t2:
t3:
t4:
t5:
t6:
t7:
t8:
t9:
t10:
t11:
t12:
t13:
t14:
t15:
t16:
t17:
t18:
t3
t4
t5 t6
t7
t8
t9 t10
t11
t12
t13 t14
t15
t16
t17 t18
UDG–02006
ENABLE input brought low to initiate a turn-on sequence.
Channel 1 (5.15V) gate enabled; IRAMP capacitor starts charging with slow turn-on clamp.
Slow charging of load voltage (back-end 5.15V) begins.
Slow turn-on period ends; linear ramp of current to the load begins.
Constant di/dt period ends; load voltage ramping continues at IMAX rate.
Back–End 5.15 V reaches input DC potential.
Channel 2 (5V) gate is enabled. Slow charging of load voltage (back-end 5V) begins. Fault monitoring on Ch. 1 enabled.
Slow turn-on period ends; linear ramp of current to load begins.
Constant di/dt period ends. Load voltage ramping continues at IMAX rate.
Back–End 5V reaches input DC potential.
Channel 3 (3.3V) gate is enabled. Slow charging of load voltage (back-end 3.3V) begins. Fault monitoring on Ch. 2 enabled.
Slow turn–on period ends; linear ramp of current to the load begins.
Constant di/dt period ends. Load voltage ramping continues at IMAX rate.
Back–End 3.3V reaches input DC potential.
Channel 4 (–5.2V) gate is enabled. Slow charging of load voltage (back-end –5.2V) begins. Fault monitoring on Ch. 3 enabled.
Slow turn-on period ends; linear ramp of current to load begins.
Constant di/dt period ends; load voltage ramping continues at IMAX rate.
Back-end –5.2 V reaches input DC potential.
Channel 4 UV/OV fault enable pulse.
PG output pulled low.
Figure 19. TPS2346 Ramp-Up Sequence
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SLUS529 – MAY 2002
APPLICATION INFORMATION
A turn-on sequence is initiated when the ENABLE input is brought low (less than 0.8 V), assuming that all four
input supplies (at the VINx pins) are within their UV/OV tolerance windows. A voltage fault at any input supply
causes all loads to be held off. When ENABLE is asserted, the Channel 1 amplifier is enabled, and a 58-µA
current source begins charging the IRAMP capacitor to generate the first IRAMP pulse. During the linear rising
edge portion of the IRAMP waveform, current is linearly ramped to the 5.15-V back-end plane. Once the voltage
at IRAMP reaches 1.5 V, the source is replaced with a 1.8-µA sink that discharges IRAMP to 0 V. During this
discharge period, load charging current, if still required, is limited to IMAX, the current sense voltage (VMAX)
divided by the sense resistor value, RSNSx, or IMAXx = VMAXx / RSNSx, where “x” refers to any of the four
channels.
At the completion of the first pulse on IRAMP, the TPS2346 moves to the second voltage to be ramped up,
Channel 2, enables its LCA and begins generating the second pulse in the IRAMP train. At this time, fault
monitoring is enabled on the Channel 1 output. Therefore, if Channel 1 has failed to attain at least the
undervoltage threshold potential, a fault is detected, any active channels turned off, and the turn-on sequence
aborted. In this manner, the maximum time allowed for ramp-up of any of the channels is the duration of one
(1) IRAMP pulse. This protects against indefinite sourcing into faulted loads.The TPS2346 latches off in
response to faults, and can be reset either by toggling the ENABLE input high and then low again, or by cycling
power to the device.
After the Channel 2 ramp pulse, the back–end planes for Channel 3 and Channel 4 are ramped up in similar
fashion. Channel 2 fault detection is enabled at the start of the Channel 3 ramp pulse, and so on. Once all four
supplies are ramped up, Channel 4 fault detection is enabled on the fifth IRAMP pulse. This last pulse is of
relatively short duration, as charge and discharge currents of approximately 256 µA are selected for the UV/OV4
enable pulse. If all four channels reach a known good state, the PG output is asserted low.
Each load current waveform, at load turn-on, may have up to three distinct periods, as shown in Figure 20.
Initially after being enabled, the ramp generator output voltage is clamped to less than 100 mV. This results in
a corresponding clamp on load current of about 7% of the programmed IMAX value (with some variance due
to internal device offset). This temporary limit applies during approximately the first 500 µs of output ramping
time. The purpose of this slow ramp period is to ensure the LCA is pulled out of saturation, and is closely tracking
the CS input, prior to enabling fast charging of the load. During this time, appreciable ramping of the back-end
voltage may or may not occur, depending on a number of factors including the IMAX value, the amount of bulk
capacitance on the load, and the magnitude and polarity of inherent offsets in the current control loop.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
1.5 V
IRAMP
VOLTAGE
0V
GATE
VOLTAGE
0V
IIMAX
LOAD
CURRENT
0A
VIN
BACK–END
VOLTAGE
0V
t1
t1: Slow turn-on period
t2
t3
TIME
32 x tCHG
tCHG
t2: Linear current ramp (di/dt)
t3: Constant-current load charging
tCHG: IRAMP capacitor charge time, (1.4 × CIRAMP/58)
UDG–02005
Figure 20. Load Current at Startup
Once the slow ramp period has expired, the clamp is removed, and the IRAMP voltage continues to ramp up
at a constant rate of:
IO
58 mA
+
C IRAMP
C IRAMP
Since the linear amplifier acts to maintain equal voltages at its inputs (see Figure 2), it slews the GATEx output
such that the CSx voltage tracks the internally generated reference at its inverting input. Therefore, the linear
voltage ramp at the IRAMP pin results in a linear current ramp to the three positive loads.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
The LCA reference ramp tracks the IRAMP pin voltage up to a level of VO(IRAMP) ` 1.35 V. This corresponds
to the maximum sense voltage (VINx – CSx) of 20 mV (150 mV for Channel 4). If charging of the load input bulk
capacitance completes during the constant di/dt section of channel turn-on (the set of dashed lines in Figure 20),
the load current decays to the steady-state operating level. With decreasing load current, the CSx input is pulled
to the VINx potential, and the pass MOSFET gate is driven to the LCA supply rail, fully enhancing the external
MOSFET. However, under certain combinations of bulk capacitance, IMAX, and inrush di/dt relative values, the
current ramp may reach the IMAX limit. The variable current source is switched out for the constant current
source which sets the VMAX reference level (see Figure 2). This defines the third stage of the load current
waveform. Load voltage ramping completes at the IMAX level, as shown by the set of solid lines in Figure 20.
Again, once the current demand rolls off, the LCA drives the pass MOSFET gate high to fully enhance the
MOSFET.
ramp-down sequence
A normal shutdown sequence occurs when the ENABLE input is brought high ( greater than 2 V) with the output
supplies in a healthy state (no overvoltage, undervoltage or overcurrent faults). PG is deasserted and the
back-end voltages are sequenced off in the reverse order of turn on: –5.2-V, 3.3-V, 5-V and 5.15-V (Channel 4,
Channel 3, Channel 2 and then Channel 1). The turn off is also controlled by five pulses at the IRAMP pin. The
first pulse, which is of short duration, disables the voltage fault monitoring on Channel 4 (–5.2 V). Starting with
the second pulse, each supply is turned off in order. At the start of each pulse at IRAMP, voltage fault monitoring
is disabled for the next successive channel to be turned off. The IRAMP capacitor is charged rapidly, up to the
1.5-V threshold, at which point the variable current source in the LCA block is reselected to generate the current
limit reference. At the same time, the charging source at IRAMP is replaced with a 58-µA discharge load, such
that the IRAMP capacitor is discharged at the same rate used for di/dt control during turn on. This causes the
current limit to decrease linearly, so that available load current is forced off no faster than the falling edge at
IRAMP. The LCA is disabled, and additional pull-downs applied to the GATEx pin, when either the output voltage
has decayed to less than 0.9 V, or the IRAMP waveform has decayed to approximately 0.1 V. Under conditions
of light loading during turn off, the bulk capacitance may hold up the back-end voltage even after the MOSFET
switch is turned off. In this situation, the TPS2346 waits for load discharge to less than 0.9 V prior to proceeding
to the next channel. Channel 4 is the exception to this operation; the VS4 status is not monitored during turn off,
and the device sequences to Channel 3 turn-off once the second IRAMP pulse ends.
setting the sense resistor values
Due to the current limiting operation of the internal LCAs, the maximum allowable load current for the application
is easily programmed by selecting the appropriate value sense resistors. The LCA acts to limit the CSx voltage
(relative to VINx) to the internal reference, which during steady-state operation is VMAX. Therefore, a sense
resistor for each channel can be calculated from equation (1).
R SNSx + VMAXx
IMAXx
(1)
where
RSNSx is the the sense resistor value for Channel x,
VMAXx is the IMAX sense voltage limit, and
IMAXx is the Channel x maximum load current.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
When setting the current limits, it is important to consider the device minimum that may be imposed by the
TPS2346. Using the values given in the electrical tables, equations (2) and (3) follow from equation (1).
For Channels 1, 2 and 3:
R SNSx + 16 mV
IMAXx
(2)
where:
x = 1, 2 or 3.
For Channel 4:
R SNS4 + 75 mV
IMAX4
(3)
To ensure proper operation across the range of anticipated load currents on each channel, the maximum load
under normal operating conditions must also be considered. To avoid current-limit operation during steady-state
loading, the IMAX level must be set above the expected load. For example, if the 5-V (Channel 2) and 3.3-V
(Channel 3) supplies of the typical application diagram each need to deliver up to 7.5 A, and a 500-mA margin
is desired, using equation (2) yields:
R2 + R3 + 16 mV + 2 mW
8A
Similarly, for up to 5-A capability on Channel 1, equation (2) indicates R1 ` 3 mΩ. Setting R4 = 200 mΩ, provides
some margin over a 250 mA load.
setting the inrush slew rate
The TPS2346 is easily programmed for the desired maximum current slew rate during turn-on and turn-off
events. A single capacitor at the IRAMP pin (C2 in the diagram) controls the di/dt for all three positive channels.
Once the sense resistor values have been established, the value for CIRAMP, in microfarads, can be determined
from equation (4).
For Channels 1, 2, and 3:
C IRAMPx +
68
67.5
R SNSx
ǒdtdiǓ
(4)
x
where:
CIRAMPx = the capacitor value indicated to achieve the (di/dt)x limit value,
RSNSx = sense resistor in ohms and
(di/dt)x = the maximum di/dt rate, in amps/second.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
To complete the design of the power interface for the plug–in shown in the typical application diagram, assume
that a maximum slew rate of 1.5 A/ms is specified for each of the three positive-voltage loads. A value for
capacitor C2 must still be determined. Inspection of equation (4) indicates that, given the same di/dt requirement
on all supplies, the supply channel(s) with the lowest-value sense resistor dictates the minimum value for the
IRAMP capacitor. Therefore, the 5-V and 3.3-V supplies are suggested in this case for obtaining an initial
estimate for CIRAMP. Using the associated values, equation (4) produces the result shown in equation (5).
C IRAMP2,3 +
67.5
68
(0.002 W)
ǒ1500 AńsǓ
^ 0.336 mF
(5)
A value of 0.33 µF can be used, or the next available standard value of 0.39 µF provides some margin for
capacitor and sense-resistor tolerances. In either case, equation (4) can be rewritten as equation (6), which is
used here to verify that the 5.15-V slew rate is still within specification.
ǒdińdtǓ +
x
67.5
68
R SNSx
C IRAMPx
(6)
where:
RSNSx is in ohms,
CIRAMPx is the value suggested by equation (5) in microfarads, and
(di/dt)x is given in amps/second.
For a CIRAMP of 0.39 µF, the maximum di/dt for the 5.15-V supply is approximately 860 mA/ms which is well
within the example requirement.
protection against faulted loads
The TPS2346 allows the time period of one IRAMP pulse for each back-end plane’s voltage to ramp-up to its
minimum level. After this delay period, the device latches off if an undervoltage fault is subsequently detected.
This nominal delay time, tTIMER, is set by the constant-current charging and subsequent discharging of CIRAMP,
and is therefore determined from equation (7).
t TIMER + C IRAMP
1.4
1 Ǔ
ǒ581 ) 1.8
(7)
where:
CIRAMP is in microfarads.
The resultant fault timer period should be sufficient for most applications; however, it is good design practice
to verify that the delay is long enough for each load.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
Due to the potential three-phase nature of the load current ramp (refer to Figure 20), the increasing load voltage
may also have three distinct periods. The first phase is during the slow turn-on period at the start of each IRAMP
cycle. Depending on a number of factors, significant voltage ramping may or may not occur during this time.
For verification of the fault timeout delay, the worst case situation is no appreciable load charging (i.e., a longer
overall charge time); therefore it is assumed that no voltage ramp occurs here.
The next phase is the linear load current ramp period. For any device channel x, if the IMAX level is not reached
while charging a given load capacitor of CLx, then the time to reach the input dc level, VINx, is estimated by
equation (8).
t SSx +
Ǹ
2
C Lx
C IRAMP K X
58 mA
R SNSx
V INx
(8)
where:
KX = 67.5 for Channels 1, 2, and 3, and
KX = 7.5 for Channel 4.
For example, assuming the 5-V back-end plane in this application has 220-µF bulk capacitance, the anticipated
typical ramp-up time is about 1.41 ms.
During inrush slewing, the load current ramp tracks the voltage ramp on the IRAMP capacitor, up to a voltage
of about 1.35 V on the IRAMP pin. Therefore, the time duration of this ramp activity, tIRAMP, is given by
equation (9).
t IRAMP +
(1.25 V)
C IRAMP
58
(9)
where:
CIRAMP is in microfarads.
If, for any channel, the time for soft-start charging of the load voltage is greater than the current ramp period,
(tSSx > tIRAMP), back-end plane ramp-up completes at the dc IMAX level. In this case, the following procedure
can be used to estimate load ramp-up time.
First, equation (10) is used to determine the load voltage level, vLx(t), attained during the current ramp period.
v Lxǒt IRAMPǓ +
58 mA
2
C Lx
C IRAMP
KX
R SNSx
ǒt IRAMPǓ
2
(10)
Once this voltage level is known, it can be used to estimate the additional charging time required at constant
current to reach the input dc potential, tCCx. This time is calculated from equation (11).
t CCx +
C Lx
ǒVINx * VLx ǒtIRAMPǓǓ
(11)
IMAXx
The sum of tIRAMP and tCCx can then be used to estimate the total load ramp-up time for Channel x.
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25
SLUS529 – MAY 2002
APPLICATION INFORMATION
precharge circuit
The precharge pin generates a 1-V bias voltage intended to be used for precharging the bus signals during hot
swap. The pin’s output stage has both source and sink capability, enabling it to pull lines up from 0 V or down
from the I/O supply potential as needed. In typical implementations, each I/O line requiring precharge is isolated
from the PRECHG source with a biasing resistor, RP in the typical application diagram. Common values for RP
range from 10 kΩ to 50 kΩ. However, a number of factors influence precharge resistor value, including the
number of lines requiring precharge, the parasitic capacitance associated with each line (both stub and I/O
device), the precharge rate needed, and the system requirements for high- and low-level input current (IIH, IIL)
on each I/O line. Several manufacturers offer integrated bus switches useful for precharge disconnect wherever
input current is an issue.
A stub resistor (R8) is also shown, which is inserted in each I/O line to provide some series damping. Typical
stub resistor value is 10 Ω, and it should be placed close to the connector.
protecting ICs from voltage transients
Parasitic inductance associated with the power distribution network can cause large voltage spikes on the
supply rails if the current is suddenly interrupted by the TPS2346 during a fault condition. Since the absolute
maximum voltage rating of the device is 15 V, there should be sufficient margin from the supply nominal values
to prevent damage. However, it may be necessary in certain applications to protect either the TPS2346 or other
low-voltage devices connected directly to the plug-in’s input rails. There are several techniques that may be
used to improve the transient performance of the plug-in and host system.
D As a general rule, always use dedicated PCB planes for the power supply and ground nodes, and maximize
the trace width of high-current runs. This minimizes the parasitic inductance of the power distribution
network. This is recommended on both the backplane and plug-in modules.
D Add small-value capacitors to the supply pins of devices needing protection from transients, connected to
ground. To reduce inrush, these capacitors should be 0.1 µF or less. For this function, higher ESR capacitors
are actually preferable to low-ESR capacitors, as they provide some RC damping against high-frequency
ringing of the supply voltage. As these capacitors generally reside on the input (non-isolated) side of a
plug-in module, ESR also limits inrush current generated by the added capacitance.
D In some cases, it may be necessary to add a resistor in series with the input capacitor to improve the
damping response of the circuit. Generally, this is a low-value resistor of about 10 Ω or less.
D Clamp the voltage at sensitive IC supply pins with a Zener diode. The maximum breakdown of these
protection devices must be less than the absolute maximum rating of the device being protected. If possible,
select a clamp which is inactive during normal steady-state operation of the module to minimize or eliminate
power dissipation in the protection circuitry. For example, if the VIN1 or VIN2 pins of the TPS2346 require
protection, a 6.8 V, 6% Zener (e.g., BZX84C series) clamps spikes well below the 15-V threshold, but is off
when the supplies are at nominal levels. In addition, even with worst-case tolerances and accounting for
some temperature coefficient, this device should not inhibit the OV detection function of the TPS2346 on
these rails.
D Place any protection devices, capacitors or diodes, close to the device being protected, with short trace
lengths back to the VCC/VDD and GND pins.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
layout considerations
To optimize the performance of the TPS2346, care should be taken to use good layout practice with the parts
placement and etch routing of the hot swap circuit components. This includes any protection devices as well
as the sense and pass elements. Protection devices should be located close to the hot swap controller, and
trace-lengths back to their respective pins kept to a minimum. If a decoupling capacitor is used on the VIN1
supply, it also should be placed close to the part.
Mount the charge pump reservoir capacitor (C6 in the application diagram) close to the TPS2346, with minimal
trace lengths back to the CPUMP and CPGND pins.
For proper operation, the three ground pins of the TPS2346 must be connected together near the device. The
ground leads of the ramp and charge pump capacitors, protection diodes, and any decoupling capacitors should
also tie into this node close to the part. This junction should be routed separately back to the J1 connector, where
it can tie into the PCB GND node, as opposed to tying into the ground plane elsewhere in the high-current return
path.
Use wide traces when connecting the sense resistors and power FETs into their respective current paths. When
feeding these connections through from an internal power plane, use multiple vias to reduce the overall
impedance of the current path. This helps reduce insertion loss across the hot swap interface, and improve the
thermal performance of the PCB. Additional copper plane used on the land patterns of these devices can
significantly reduce their thermal impedance, reducing temperature rise in the module and improving overall
reliability of the power devices.
Connections to the sense resistors for the VINx and CSx device pins should be made with good Kelvin
connections to optimize the accuracy of the current-limit thresholds and slew-rate control. This is especially
important on high-current supplies. When typical load levels on these supplies are high, board trace resistance
between elements in the supply current paths becomes significant. The two sense traces for each supply should
connect symmetrically to the sense resistor land pattern, in close proximity to the element leads, and not
upstream or downstream from the device. Trace routing back to the TPS2346 should be fairly well balanced.
Figure 22 illustrates two recommendations for the current sense layout.
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SLUS529 – MAY 2002
APPLICATION INFORMATION
LOAD CURRENT PATH
LOAD CURRENT PATH
22
21
22
21
SENSE
RESISTOR
TPS2346*
TPS2346*
(a)
(b)
UDG–02014
*Additional details ommited for clarity
Figure 21. Recommended Layout for SMD Chip-Sense Resistor for 5-V Rail
28
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