LH521028A ALE 1 52 51 50 49 48 47 46 A14 2 A13 3 G 4 A15 VSS 5 W 6 DQ8 45 DQ7 10 44 DQ6 11 43 VCC DQ11 12 42 VSS DQ12 13 41 DQ5 DQ13 14 40 DQ4 DQ14 15 39 DQ3 DQ2 DQ10 9 VCC VSS 18 36 VCC DQ16 19 35 DQ1 DQ17 34 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ0 A11 VSS DQ15 A12 38 37 A10 16 17 A8 VSS VCC A9 This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH).The Byte-select controls, S H 7 8 DQ9 VCC The control signals include Write Enable (W), Chip Enable (E), High and Low Byte Select (S L and SH), Output Enable (G) and Address Latch Enable (ALE). The wide word provides for reduced component count, improved density, reduced Address bus loading and improved performance. The wide word also allows for byte-parity with no additional RAM required. TOP VIEW VCC The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation. 52-PIN PLCC A7 FUNCTIONAL DESCRIPTION PIN CONNECTIONS VSS • Package: 52-Pin PLCC SH • JEDEC Standard Pinout SL • 2 V Data Retention A6 • 5 V ± 10% Supply When E and either SH or SL are LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address with ALE HIGH. E • TTL Compatible I/O A5 • Low-Power Stand-by Mode when Deselected A4 • Reduced Loading on Address Bus A1 • Transparent Address Latch Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is transferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control (G) can prevent bus contention. A0 • Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity A3 • Fast Access Times: 15/17/20/25/35 ns and SL, are also used to enable or disable Read and Write operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applications not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address bus buffers and/or latches. A2 FEATURES CMOS 64K × 18 Static RAM 521028-1D Figure 1. Pin Connections for PLCC Package 1 CMOS 64K × 18 Static RAM LH521028A ALE A8 A7 A6 A5 A4 A3 A2 A1 A0 ... I/O CIRCUIT ... ... DQ0 TRANSPARENT LATCH ROW DECODE SL A15 A14 A13 E A12 W SH A11 A10 TRANSPARENT LATCH DQ8 BLOCK DECODE COLUMN DECODE MEMORY ARRAY (65,536 x 18) A9 G ... ... DQ9 I/O CIRCUIT DQ17 ... 521028-12 Figure 2. LH521028A Block Diagram 2 CMOS 64K × 18 Static RAM LH521028A TRUTH TABLE ADDRESS E SH SL ALE G W DQ 0-DQ 8 DQ 9-DQ 17 MODE I CC Don’t Care H X X H X X High-Z High-Z Standby ISB Valid L L H H L H Active High-Z Read ICC1 Valid L H L H L H High-Z Active Read ICC1 Valid L L L H L H Active Active Read ICC1 Valid L L L H H H High-Z High-Z Read ICC1 Don’t Care L L L L L H Data Out Data Out Read ICC1 Valid L L H H X L Data In Don’t Care Write, low byte ICC1 Valid L H L H X L Don’t Care Data In Write, high byte ICC1 Valid L L L H X L Data In Data In Write, both bytes ICC1 Valid L H H H X L Don’t Care Don’t Care Write, inhibited ICC1 Don’t Care L L L L X L Data In Data In Write, both bytes ICC1 NOTE: X = Don’t Care, L = LOW, H = HIGH PIN DESCRIPTIONS PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 1 VSS 14 DQ13 27 VSS 40 DQ4 2 VCC 15 DQ14 28 VCC 41 DQ5 3 SL 16 VSS 29 A8 42 VSS 4 SH 17 VCC 30 A9 43 VCC 5 E 18 DQ15 31 A10 44 DQ6 6 A0 19 DQ16 32 A11 45 DQ7 7 A1 20 DQ17 33 A12 46 DQ8 8 DQ9 21 A2 34 DQ0 47 A13 9 DQ10 22 A3 35 DQ1 48 A14 10 VCC 23 A4 36 VCC 49 A15 11 VSS 24 A5 37 VSS 50 G 12 DQ11 25 A6 38 DQ2 51 ALE 13 DQ12 26 A7 39 DQ3 52 W 3 CMOS 64K × 18 Static RAM LH521028A PIN DEFINITIONS V CC Positive Supply Voltage Terminals V SS Reference Terminals A0 – A15 Address Bus Input The Address bus is decoded to select one 18-bit word out of the total 64K words for Read and Write operations. E Chip Enable byte and prevent Read or Write operations. When the Select signal is LOW and Chip Enable is LOW, a Read or Write operation is performed at the location determined by the contents of the Address bus. When Chip Enable is HIGH, the Select signals are Don’t Care. Select Low (S L) is assigned to DQ0 – DQ8 and Select High (SH) is assigned to DQ9 – DQ17. ALE Active LOW Input Address Latch Enable Active High Input Chip Enable is used to enable the device for Read and Write operations. When HIGH, both Read and Write operations are disabled and the device is in a reduced power state. When LOW, a Read or Write operation is enabled. The Address Latch Enable signal is used to control the Transparent latches on the Address bus. The Latches are transparent when HIGH and are latched when LOW. If not required, Address Latch Enable may be tied HIGH, leaving the Address bus in a transparent condition. W DQ0 – DQ17 Data Bus Write Enable Active LOW Input Write Enable is used to select either Read or Write operations when the device is enabled. When Write Enable is HIGH and the device is Enabled, a Read operation is selected. When Write Enable is LOW and the device is enabled, a Write operation is selected. A Bytewrite operation is available by using the Byte-select controls. S H, S L Select High Select Low Active LOW Inputs The Select High and Select Low signals, in conjunction with the Chip Enable and Write Enable signals, allow the selection of the individual bytes for Read and Write operations. When High, the Select signal will deselect its 4 Input/Output DQ0 – DQ8 comprise the Low byte, selected by SL, and DQ9 – DQ17 comprise the High Data byte, selected by SH. The Data Bus is in a high impedance input mode during Write operations and standby. The Data bus is in a low-impedance output mode during Read operations. G Output Enable Active LOW Input The Output Enable signal is used to control the output buffers on the Data Input/Output bus. When G is HIGH, all output buffers are forced to a high impedance condition. When G is LOW, the output buffers will become active only during a Read operation (E and SH / S L are LOW, W is HIGH). CMOS 64K × 18 Static RAM LH521028A ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING VCC to V SS Potential –0.5 V to 7 V Input Voltage Range –0.5 V to VCC + 0.5 V DC Output Current ± 40 mA 2 Storage Temperature Range –65oC to 150oC Power Dissipation (Package Limit) 2W NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGES SYMBOL PARAMETER MIN TA Temperature, Ambient VCC Supply Voltage VSS Supply Voltage VIL Logic ‘0’ Input Voltage VIH Logic ‘1’ Input Voltage TYP 0 1 MAX UNIT 70 oC 4.5 5.0 5.5 V 0 0 0 V –0.5 0.8 V 2.2 VCC + 0.5 V NOTE: 1. Negative undershoot of up to 3.0 V is permitted once per cycle. DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS 1 MIN tCYCLE = minimum TYP MAX UNIT 300 mA ICC1 Operating Current ISB1 Standby Current E ≥ VCC – 0.2 V VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V f=0 4 mA ISB2 Standby Current E ≥ VIH VIN = V IH or VIL 50 mA ILI Input Leakage Current VIN = 0 V to VCC –2 2 µA ILO I/O Leakage Current VIN = 0 V to VCC –2 2 µA VOH Output High Voltage IOH = –4.0 mA 2.4 VOL Output Low Voltage IOL = 8.0 mA V 0.4 V NOTE: 1. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open. 5 CMOS 64K × 18 Static RAM LH521028A AC TEST CONDITIONS PARAMETER Input Pulse Levels V SS to 3 V Input Rise and Fall Times 5 ns Input and Output Timing Ref. Levels 1.5 V Output Load, Timing Tests +5 V RATING Figure 3 480 Ω DQ PINS 255 Ω CLOAD=30 pF * CAPACITANCE 1,2 PARAMETER RATING CIN (Input Capacitance) 5 pF CDQ (I/O Capacitance) 7 pF * INCLUDES JIG AND SCOPE CAPACITANCES NOTES: 1. Capacitances are maximum values at 25oC measured at 1.0 MHz with VBias = 0 V and VCC = 5.0 V. 2. Guaranteed but not tested. 6 Figure 3. Output Load Circuit 521028-13 CMOS 64K × 18 Static RAM LH521028A AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL –1 5 DESCRIPTION MIN –17 MAX MIN –20 MAX MIN –25 MAX MIN –35 MAX MIN UNITS MAX READ CYCLE tRC Read Cycle Timing 15 17 tAA Address Access Time tASL Address Setup to Latch Enable 2 2 2 2 2 ns tAHL Address Hold from Latch Enable 3 3 4 4 4 ns 15 20 17 25 20 35 25 ns 35 ns tLEA Latch Enable to Data Valid tLHM Latch Enable High Pulse Width 5 5 5 5 5 ns tOH Output Hold from Address Change 4 4 4 4 4 ns tLH Output Hold from Latch High 4.5 4.5 4.5 4.5 4.5 ns tEA E Low to Valid Data 16 18 15 2,3 21 17 26 20 36 25 ns 35 ns tELZ E Low to Output Active tEHZ E High to Output High-Z 2,3 9 10 10 12 20 ns tSA S Low to Valid Data 7 8 10 12 20 ns tSLZ S Low to Output Active 3 2,3 tSHZ S High to Output High-Z 3 2 2 2,3 tGA G Low to Valid Data tGLZ G Low to Output Active 2,3 tGHZ G High to Output High-Z 2,3 tRCS Read Setup from W High tRCH Read Hold from W Low 10 ns 20 12 0 8 ns 3 12 9 0 8 3 3 10 8 0 7 3 2 10 7 0 3 3 20 0 10 ns ns ns 20 ns 0 0 0 0 0 ns 0 0 0 0 0 ns tPU E LOW to Power Up Time tPD E HIGH to Power Down Time 3 15 17 20 25 35 ns tWA Access Time From Write Enable HIGH 18 20 20 25 35 ns tWC Write Cycle Time 15 17 20 25 35 ns tEW E Low to End of Write 11 12 13 20 30 ns tSW S LOW to End of Write 7 8 10 20 30 ns tAW Address Valid to End of Write 11 12 13 20 30 ns tAS Address Setup to Start of Write 0 0 0 0 0 ns tAH Address Hold from End of Write 0 0 0 0 0 ns tASL Address Setup to Latch Enable 2 2 2 2 2 ns tAHL Address Hold from Latch Enable 3 3 4 4 4 ns 0 0 0 0 0 ns WRITE CYCLE tLHW Latch Hold from W High 0 0 0 0 0 ns tLHM Latch Enable HIGH Pulse Width 5 5 5 5 5 ns tWP W Pulse Width 11 12 13 20 30 ns tDW Input Data Setup Time 7 8 9 10 15 ns tDH Input Data Hold Time 0 0 0 0 0 ns 2,3 tWHZ W Low to Output High-Z tWLZ W High to Output Active 2,3 7 3 8 3 8 3 10 3 14 3 ns ns NOTES: 1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels. 2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load. CLoad = 5 pF. 3. Guaranteed but not tested. 7 CMOS 64K × 18 Static RAM LH521028A Read Cycle No. 2 (Unlatched Chip Enable Controlled Read) TIMING DIAGRAMS – READ CYCLE Read Cycle No. 1 (Unlatched Address Controlled Read) Chip is in Read Mode: ALE is HIGH (transparent mode). Read cycle timing is referenced from when E, S, and G are stable until the first address transition. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid. Chip is in Read Mode: ALE is HIGH (transparent mode), E and G are LOW. Read cycle timing is referenced from when all addresses are stable until the first address transition. Following a W-controlled Write cycle, tWA and tAA must both be satisfied to ensure valid data. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA. tRC ADDRESS VALID ADDRESS tWA W tAA DQ tOH VALID DATA PREVIOUS DATA 521028-2 Figure 4. Read Cycle No. 1 ADDRESS VALID ADDRESS tRCS tRCH W tEA E tEHZ tSA SL, SH tSHZ tGA G tGLZ tGHZ tSLZ tELZ DQ VALID DATA 521028-3 Figure 5. Read Cycle No. 2 8 CMOS 64K × 18 Static RAM LH521028A TIMING DIAGRAMS – READ CYCLE (cont’d) Read Cycle No. 3 (Latched Address Controlled Read) Chip is in Read Mode: W is HIGH, E, SH, SL and G are LOW. Both tAA and tLEA must be met before valid data is available. If the address is valid prior to the rising edge of ALE, then the access time is tLEA. If the address is valid after ALE is HIGH (or if ALE is tied HIGH) then the access time is tAA. Crosshatched portion of Data Out implies that data lines are in the Low-Z state but the data is not guaranteed to be valid until tAA. E, SH, SL tLHM ALE tASL ADDRESS tAHL VALID ADDRESS tLH tAA DQ PREVIOUS DATA VALID DATA tLEA 521028-4 Figure 6. Read Cycle No. 3 9 CMOS 64K × 18 Static RAM LH521028A TIMING DIAGRAMS – READ CYCLE (cont’d) Read Cycle No. 4 Chip is in Read Mode: Timing illustrated for the case when addresses are valid before E goes LOW. Data Out is not specified to be valid until tEA, tSA and tGA, but may become active as early as tELZ, tSLZ or tGLZ. tASL ADDRESS tAHL VALID ADDRESS tLHM ALE tLEA tEA E tRCH tRCS W tSA SL, SH tEHZ tRC tGA G tGLZ tGHZ tSLZ tELZ DQ VALID DATA 521028-5 Figure 7. Read Cycle No. 4 10 CMOS 64K × 18 Static RAM LH521028A TIMING DIAGRAMS – WRITE CYCLE Write Cycle No. 1 (Unlatched W Controlled Write) Addresses must be stable during unlatched Write cycles. The outputs will remain in the High-Z state if W is LOW when E and SH / SL go LOW. If G is HIGH, the outputs will remain in the High-Z state. Although these examples illustrate timing with G active, it is recommended that G be held HIGH for all Write cycles. This will prevent the LH521028’s outputs from becoming active, preventing bus contention, thereby reducing system noise. Chip is selected: E, G, and SH / S L are LOW, ALE is High. Using only W to control Write cycles may not offer the best performance since both tWHZ and tDW timing specifications must be met. Write Cycle No. 2 (E, S L, S H Controlled Write) G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edge of E, SH /SL if G is LOW. tWC ADDRESS VALID ADDRESS tAH tAW tAS tWP W tWLZ tWHZ tDW tDH DQ PREVIOUS OUTPUT VALID DATA 521028-6 Figure 8. Write Cycle No. 1 tWC ADDRESS VALID ADDRESS tEW E, SL, SH tAS tWP tAH W tELZ tWHZ DQ tDW tDH VALID DATA 521028-7 Figure 9. Write Cycle No. 2 11 CMOS 64K × 18 Static RAM LH521028A TIMING DIAGRAMS – WRITE CYCLE (cont’d) Write Cycle No. 3 (Latched W Controlled Write) Write Cycle No. 4 (E Controlled) Chip is selected: E, G, and S H / SL are LOW. G is LOW. DQ lines may transition to Low-Z if the falling edge of W occurs after the falling edges of E and SH/SL. tWC tLHM ALE tASL tAHL ADDRESS VALID ADDRESS tAW tAS tLHW tWP W tWLZ tWHZ tDW tDH DQ PREVIOUS OUTPUT VALID DATA 521028-8 Figure 10. Write Cycle No. 3 tWC tLHM ALE tASL tAHL ADDRESS VALID ADDRESS tEW E, SH / SL tWP tAS tLHW W tELZ tSLZ DQ tDW tWHZ tDH VALID DATA 521028-9 Figure 11. Write Cycle No. 4 12 CMOS 64K × 18 Static RAM LH521028A BYTE OPERATIONS Byte Read Description (Figure 12) To read individual bytes, the device must be enabled (E is LOW), W must be HIGH, the outputs must be enabled (G is LOW) and the addresses must be either stable or latched with ALE. Figure 12 is one example of the byte read capabilities of this device. The example shows two read operations. The first is a read of the high byte of the current memory location and the second is a read of the low byte of the memory location. (1) At the beginning of the cycle both SL and SH are HIGH. ADDRESS (2) SH goes LOW initiating a Read on the upper byte DQH(9-17). SL remains HIGH keeping the lower byte DQL(0-8) disabled and in a high-impedance mode. (3) SL goes LOW activating DQL(0-8).Valid data is available in tSA following SL going LOW. (4) When SH goes HIGH, DQH(9-17) remains valid for tSHZ before returning to a high-impedance condition. (5) Finally, the Read for the lower byte is terminated by deasserting SL (HIGH). DQL(0-8) remains active for tSHZ following SL going HIGH. VALID ADDRESS ALE G SL SH VALID DATA DQL (0-8) DQH (9-17) VALID DATA (1) (2) (3) (4) (5) 521028-10 Figure 12. Byte Read (E is LOW and W is HIGH) 13 CMOS 64K × 18 Static RAM LH521028A BYTE OPERATIONS (cont’d) Byte Write Description (Figure 13) To do individual byte-write operations, the device must be enabled (E is LOW, G is don’t care) and addresses must be either stable or latched. Figure 13 is one example of the byte-write capabilities of this device. The diagram shows two write operations with unlatched addresses. The first is a write to the low byte of memory location N and the second is a write to the high byte of memory location M. (4) Address N is changed to M. (5) The Write operation is now initiated on the upper byte DQH(9-17) by bringing SH LOW. SL remains HIGH preventing a Write operation from occurring in the lower byte DQL(0-8) of memory location N+ 1. (6) SH now goes HIGH terminating the Write operation on the upper byte of address M. (1) W goes LOW while SL and SH remain HIGH. (2) SL goes LOW initiating a Write into the lower byte DQL(0-8) of memory location N. SH remains HIGH preventing a Write into the upper byte DQL(9-17) of memory location N. ADDRESS (3) SL now goes HIGH terminating the Write operation on the lower byte of memory location N. (7) W goes HIGH, ending the Write operation. VALID ADDRESS N VALID ADDRESS M ALE W SL SH DQL (0-8) DATA IN (N) DQH (9-17) DATA IN (M) (1) (2) (3) (4) (5) (6) (7) 521028-11 Figure 13. Byte Write (E is LOW) 14 CMOS 64K × 18 Static RAM LH521028A PACKAGE DIAGRAM 19.69 [0.775] 18.67 [0.735] 20.57 [0.810] 19.56 [0.770] 18.8 [0.740] 17.78 [0.700] 19.69 [0.775] 18.67 [0.735] 20.57 [0.810] 19.56 [0.770] 4.06 [0.160] 3.56 [0.140] 0.10 [0.004] 1.27 [0.050] TYP. .58 [0.023] .33 [0.013] DIMENSIONS IN MM [INCHES] 0.76 [0.030] 1.38 [0.015] MAXIMUM LIMIT MINIMUM LIMIT 52PLCC-A 52-Pin PLCC ORDERING INFORMATION LH521028A Device Type U Package - ## Speed 15 17 20 Access Time (ns) 25 35 52-pin, Plastic Leaded Chip Carrier (PLCC52-P-750) CMOS 64K x 18 Static RAM Example: LH521028AU-15 (CMOS 64K x 18 Static RAM, 15 ns, 52-pin, Plastic Leaded Chip Carrier) 521028AM 15