LH531024 FEATURES • 65,536 words × 16 bit organization CMOS 1M (64K × 16) MROM PIN CONNECTIONS 40-PIN DIP 40-PIN SOP TOP VIEW • Access time: 100 ns (MAX.) • Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 µW (MAX.) VCC NC 1 40 CE 2 39 NC D15 3 38 NC D14 4 37 A15 D13 5 36 A14 A13 • Static operation D12 6 35 D11 7 34 A12 • TTL compatible I/O D10 8 33 A11 9 32 A10 • Three-state outputs D9 D8 10 31 A9 GND 11 30 GND D7 12 29 A8 • JEDEC standard EPROM pinout (DIP) D6 13 28 A7 D5 14 27 A6 • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) D4 15 26 A5 D3 16 25 A4 • Single +5 V power supply D2 17 24 A3 D1 18 23 A2 D0 19 22 A1 OE 20 21 A0 DESCRIPTION Figure 1. Pin Connections for DIP and SOP Packages TOP VIEW D13 D14 D15 CE NC NC VCC NC NC A15 A14 44-PIN PLCC 6 5 4 3 2 1 44 43 42 41 40 D12 7 39 A13 D11 8 38 A12 D10 9 37 A11 D9 10 36 A10 D8 11 35 A9 GND 12 34 GND NC 13 33 NC D7 14 32 A8 D6 15 31 A7 D5 16 30 A6 D4 29 17 18 19 20 21 22 23 24 25 26 27 28 A5 D3 D2 D1 D0 OE NC A0 A1 A2 A3 A4 The LH531024 is a mask-programmable ROM organized as 65,536 × 16 bits. It is fabricated using silicon-gate CMOS process technology. 531024-1 531024-2 Figure 2. Pin Connections for QFJ (PLCC) Package 1 LH531024 CMOS 1M MROM A15 37 A14 36 A13 35 ADDRESS BUFFER A12 34 A11 33 A10 32 ADDRESS DECODER MEMORY MATRIX (65,536 x 16) A9 31 A8 29 A7 28 A6 27 A5 26 A4 25 A3 24 A2 23 A1 22 COLUMN SELECTOR A0 21 CE 2 CE BUFFER OE 20 OE BUFFER TIMING GENERATOR SENSE AMPLIFIER OUTPUT BUFFER 40 VCC 11 30 GND 19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15 NOTE: Pin numbers apply to the 40-pin DIP or SOP. 531024-3 Figure 3. LH531024 Block Diagram PIN DESCRIPTION SIGNAL A0 – A15 D0 – D15 CE 2 PIN NAME Address input SIGNAL PIN NAME OE Output enable input Data output VCC Power supply (+5 V) Chip Enable input GND Ground CMOS 1M MROM LH531024 A15 41 A14 40 A13 39 A6 30 A5 29 A4 28 ADDRESS DECODER A8 32 A7 31 ADDRESS BUFFER A12 38 A11 37 A10 36 A9 35 MEMORY MATRIX (65,536 x 16) A3 27 A2 26 A1 25 COLUMN SELECTOR A0 24 CE 3 CE BUFFER OE 22 OE BUFFER TIMING GENERATOR SENSE AMPLIFIER OUTPUT BUFFER 12 34 GND 44 VCC 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15 NOTE: Pin numbers apply to the 44-pin QFJ. 531024-4 Figure 4. LH531024 Block Diagram 3 LH531024 CMOS 1M MROM TRUTH TABLE CE OE H X L H L L D0 – D15 SUPPLY CURRENT NOTE Standby (ISB) 1 High-Z Operating (ICC) D0 – D15 NOTE: 1. X = H or L. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC –0.3 to +7.0 V Input voltage VIN –0.3 to V CC +0.3 V Output voltage VOUT –0.3 to V CC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input ‘Low’ voltage VIL –0.3 0.8 V Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Output ‘Low’ voltage VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC Output leakage current | ILO | V OUT = 0 V to VCC 10 µA ICC1 t RC = 100 ns 75 mA ICC2 t RC = 1 µs 65 mA ICC3 t RC = 100 ns 70 mA ICC4 t RC = 1 µs 60 mA ISB1 CE = VIH 3 mA ISB2 CE = VCC – 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance COUT NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 4 MIN. 0.4 2.4 NOTE V V 10 µA 1 2 3 CMOS 1M MROM LH531024 AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL MIN. tRC 100 Read cycle time TYP. MAX. UNIT NOTE ns Address access time tAA 100 ns Chip enable access time tACE 100 ns 50 ns Output enable delay time tOE Output hold time tOH CE to output in High-Z tCHZ 50 ns OE to output in High-Z tOHZ 50 ns 5 ns 1 NOTE: 1. This is the time required for the output to become high-impedance. AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude 0.4 V to 2.6 V Input signal rise time 10 ns Input/output reference level 1.5 V Output load condition 1TTL +100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC pin and the GND pin. tRC A0 - A15 tAA (NOTE) CE tACE (NOTE) tCHZ OE tOHZ tOE (NOTE) D0 - D15 tOH DATA VALID NOTE: Data becomes valid after the intervals, tAA, tACE, and tOE, from address input, chip enable, and output enable, respectively have been met. 531024-5 Figure 5. Timing Diagram 5 LH531024 CMOS 1M MROM PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 20 0.30 [0.012] 0.20 [0.008] 52.30 [2.059] 51.70 [2.035] 15.24 [0.600] TYP. 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 40 21 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 26.50 [1.043] 26.10 [1.028] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40SOP 40-pin, 525-mil SOP 6 CMOS 1M MROM LH531024 44QFJ (QFJ044-P-S650) 1.27 [0.050] TYP. C1.1 6 1 44 40 39 7 16.00 [0.630] 15.20 [0.598] 16.60 [0.654] 17.60 [0.693] 17.40 [0.685] 0.56 [0.022] 0.36 [0.014] 29 17 18 28 0.85 [0.033] 16.60 [0.654] 2.80 [0.110] 2.40 [0.094] 17.60 [0.693] 17.40 [0.685] 1.80 [0.071] 2.35 [0.093] 0.25 [0.010] 4.60 [0.181] 4.20 [0.165] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 44QFJ-1 44-pin, 650-mil QFJ (PLCC) ORDERING INFORMATION LH531024 Device Type X Package D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) U 44-pin, 650-mil QFJ (PLCC) (QFJ044-P-S650) CMOS 1M (64K x 16) Mask-Programmable ROM Example: LH531024N (CMOS 1M (64K x 16) Mask-Programmable ROM, 40-pin, 525-mil SOP) 531024-6 7