LH532000B-1 CMOS 2M (256K × 8/128K × 16) MROM FEATURES PIN CONNECTIONS • 262,144 words × 8 bit organization (Byte mode) 131,072 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) • Mask-programmable control pin (for 40-pin DIP/40-pin SOP): Pin 1 = OE1/OE1/DC Pin 12 = OE/OE • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 12 × 18 mm2 TSOP (Type I) 40-PIN DIP 40-PIN SOP TOP VIEW OE1/OE1/DC 1 40 A8 A7 2 39 A9 A6 3 38 A10 A5 4 37 A11 A4 5 36 A12 A3 6 35 A13 A2 7 34 A14 A1 8 33 A15 A0 9 32 A16 CE 10 31 BYTE GND 11 30 GND OE/OE 12 29 D15/A-1 D0 13 28 D7 D8 14 27 D14 D1 15 26 D6 D9 16 25 D13 D2 17 24 D5 D10 18 23 D12 D3 19 22 D4 D11 20 21 VCC 532000B1-1 Figure 1. Pin Connections for DIP and SOP Packages DESCRIPTION The LH532000B-1 is a CMOS 2M-bit mask-programmable ROM organized as 262,144 × 8 bits (Byte mode) or 131,072 × 16 bits (Word mode) that can be selected by BYTE input pin. It is fabricated using silicon-gate CMOS process technology. 1 LH532000B-1 CMOS 2M MROM 48-PIN TSOP (Type I) TOP VIEW BYTE 1 48 A16 2 47 GND A15 3 46 D15/A-1 A14 4 45 D7 A13 5 44 D14 A12 6 43 D6 A11 7 42 D13 A10 8 41 D5 A9 9 40 D12 A8 10 39 D4 GND NC 11 38 VCC GND 12 37 VCC NC 13 36 GND NC 14 35 D11 OE1/OE1/DC 15 34 D3 A7 16 33 D10 A6 17 32 D2 A5 18 31 D9 A4 19 30 D1 A3 20 29 D8 A2 21 28 D0 A1 22 27 OE/OE A0 23 26 GND CE 24 25 GND NOTE: Reverse bend available on request. 532000B1-2 Figure 2. Pin Connections for TSOP Package 2 CMOS 2M MROM LH532000B-1 A16 32 A15 33 A14 34 ADDRESS DECODER ADDRESS BUFFER A13 35 A12 36 A11 37 A10 38 A9 39 A8 40 A7 2 A6 3 A5 4 MEMORY MATRIX (262,144 x 8 ) (131,072 x 16 ) COLUMN SELECTOR A4 5 A3 6 A2 7 SENSE AMPLIFIER A1 8 A0 9 CE BUFFER CE 10 OE/OE 12 TIMING GENERATOR OE BUFFER OE1/OE1/DC 1 DATA SELECTOR/OUTPUT BUFFER BYTE/WORD SWITCHOVER CIRCUIT BYTE 31 21 VCC 11 GND 30 GND ADDRESS BUFFER 29 A-1 13 15 17 19 22 24 26 28 14 16 18 20 23 25 27 29 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NOTE: Pin numbers apply to 40-pin DIP or SOP. 532000B1-3 Figure 3. LH532000B-1 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A–1 – A16 Address input 1 OE/OE Output enable input 2 D0 – D15 Data output 1 OE1/OE1/DC Output enable input 2 Byte/word mode switch 1 VCC Power supply (+5 V) GND Ground BYTE CE Chip enable input NOTES: 1. D15/A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 2. The active levels of OE/OE and OE1/OE1/DC are mask-programmable. 3 LH532000B-1 CMOS 2M MROM TRUTH TABLE CE OE/OE OE1/OE1 BYTE DATA OUTPUT ADDRESS INPUT A–1 (D15) D0 – D7 D8 – D15 LSB MSB SUPPLY CURRENT H X X X X High-Z High-Z – – Standby (ISB) L L/H X X X High-Z High-Z – – Operating (ICC) L X L/H X X High-Z High-Z – – Operating (ICC) L H/L H/L H – D0 – D7 D8 – D15 A0 A16 Operating (ICC) L H/L H/L L L D0 – D7 High-Z A–1 A16 Operating (ICC) L H/L H/L L H D8 – D15 High-Z A–1 A16 Operating (ICC) NOTE: 1. X = H or L. ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage SYMBOL RATING UNIT VCC – 0.3 to +7.0 V VIN – 0.3 to VCC + 0.3 V Output voltage VOUT – 0.3 to VCC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input ‘Low’ voltage VIL – 0.3 0.8 V Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Output ‘Low’ voltage VOL I OL = 2.0 mA 0.4 V Output ‘High’ voltage NOTE VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 120 ns 50 mA 2 ICC2 t RC = 1 µs 45 mA 2 ICC3 t RC = 120 ns 45 mA 3 ICC4 t RC = 1 µs 40 mA 3 Operating current Standby current Input capacitance Output capacitance 2.4 V ISB1 CE = VIH 3 mA ISB2 CE = VCC - 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF COUT NOTES: 1. CE/OE/OE1 = VIH, OE/OE1 = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 4 MIN. CMOS 2M MROM LH532000B-1 AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER Read cycle time SYMBOL MIN. tRC 120 MAX. UNIT NOTE ns Address access time tAA 120 ns Chip enable access time tACE 120 ns 55 ns Output enable delay time tOE Output hold time tOH CE to output in High-Z tCHZ 55 ns OE to output in High-Z tOHZ 55 ns 5 ns 1 NOTE: 1. This is the time required for the output to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.6 V to 2.4 V Input rise/fall time 10 ns Input reference level 1.5 V Output reference level 0.8 V and 2.2 V Output load condition 1 TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. 5 LH532000B-1 CMOS 2M MROM tRC A-1 - A16 tAA (NOTE) CE tACE (NOTE) tCHZ OE/OE1 OE/OE1 tOHZ tOE (NOTE) tOH D0 - D7 DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE have concluded. 532000B1-4 Figure 4. Byte Mode (BYTE = VIL) tRC A0 - A16 tAA (NOTE) CE tACE (NOTE) tCHZ OE/OE1 OE/OE1 tOHZ tOE (NOTE) tOH D0 - D15 DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE have concluded. 532000B1-5 Figure 5. Word Mode (BYTE = VIH) 6 CMOS 2M MROM LH532000B-1 PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 20 0.30 [0.012] 0.20 [0.008] 52.30 [2.059] 51.70 [2.035] 15.24 [0.600] TYP. 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 40 21 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 26.50 [1.043] 26.10 [1.028] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40SOP 40-pin, 525-mil SOP 7 LH532000B-1 CMOS 2M MROM 48TSOP (TSOP048-P-1218) 0.50 [0.020] TYP. 0.30 [0.012] 0.10 [0.004] 25 48 16.60 [0.654] 16.20 [0.638] 1 18.40 [0.724] 17.60 [0.693] 17.00 [0.669] 24 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] DIMENSIONS IN MM [INCHES] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 48TSOP 2 48-pin, 12 × 18 mm TSOP (Type I) ORDERING INFORMATION LH532000B Device Type X Package -1 120 ns Version D N T TR 40-pin, 600-mil DIP (DIP040-P-0600) 40-pin, 525-mil SOP (SOP040-P-0525) 48-pin, 12 x 18 mm2 TSOP (Type I) (TSOP048-P-1218) 48-pin, 12 x 18 mm2 TSOP (Type I) Reverse bend (TSOP048-P-1218) CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM Example: LH532000BD-1 (CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM, 40-pin, 600-mil DIP) 532000B1-6 8