LH531V00 FEATURES • 131,072 words × 8 bit organization • Access time: 100 ns (MAX.) CMOS 1M (128K × 8) MROM PIN CONNECTIONS TOP VIEW 32-PIN DIP 32-PIN SOP OE1/OE1/DC 1 32 VCC A16 2 31 NC A15 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE • Power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) • Mask-programmable OE1/OE1/DC • Fully-static operation • TTL-compatible I/O • Three-state outputs • Single +5 V power supply • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 × 20 mm2 TSOP (Type I) DESCRIPTION The LH531V00 is a 1M-bit mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. A0 12 21 D7 D0 13 20 D6 D1 14 19 D5 D2 15 18 D4 17 D3 GND 16 531V00-1 Figure 1. Pin Connections for DIP and SOP Packages 32-PIN TSOP (Type I) TOP VIEW A11 1 32 A9 2 31 A10 A8 3 30 CE OE A13 4 29 D7 A14 5 28 D6 NC 6 27 D5 NC 7 26 D4 VCC 8 25 D3 OE1/OE1/DC 9 24 GND A16 10 23 D2 A15 11 22 D1 A12 12 21 D0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 531V00-2 Figure 2. Pin Connections for TSOP Package 1 LH531V00 CMOS 1M MROM A16 A15 A14 A13 2 3 29 MEMORY MATRIX (131,072 x 8) 28 A9 A8 A7 A6 ADDRESS BUFFER A11 25 A10 23 ADDRESS DECODER A12 4 26 27 5 6 A5 7 A4 8 A3 9 A2 10 A1 11 COLUMN SELECTOR A0 12 SENSE AMPLIFIER CE BUFFER CE 22 TIMING GENERATOR OUTPUT BUFFER OE 24 OE BUFFER OE1/OE1/DC 1 32 16 VCC GND 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 NOTE: Pin numbers apply to the 32-pin DIP or SOP. 531V00-3 Figure 3. LH531V00 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 – A16 Address input D0 – D7 NOTE SIGNAL OE1/OE1/DC PIN NAME Output Enable input Data output VCC Power supply (+5 V) CE Chip Enable input GND Ground OE Output Enable input NOTE: 1. Active level of OE1/OE1/DC is mask-programmable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is recommended to apply either HIGH or LOW to the DC pin. 2 NOTE 1 CMOS 1M MROM LH531V00 TRUTH TABLE CE OE OE1/OE1 D0 – D7 SUPPLY CURRENT NOTE H X X High-Z Standby (ISB) 1 L H X High-Z Operating (ICC ) 1 L X L/H High-Z Operating (ICC ) 1 L L H/L D0 – D7 Operating (ICC ) NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC + 0.3 V Output voltage VOUT –0.3 to VCC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER Input ‘Low’ voltage SYMBOL CONDITIONS VIL MIN. TYP. MAX. UNIT –0.3 0.8 V 2.2 VCC + 0.3 V 0.4 V Input ‘High’ voltage V IH Output ‘Low’ voltage VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA ICC1 t RC = 100 ns 50 mA ICC2 t RC = 1 µs 45 mA ICC3 t RC = 100 ns 45 mA ICC4 t RC = 1 µs 40 mA ISB1 CE = VIH 3 mA ISB2 CE = VCC – 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance COUT 2.4 NOTE V 1 2 3 NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 3 LH531V00 CMOS 1M MROM AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL MIN. tRC 100 Read cycle time TYP. MAX. UNIT NOTE ns Address access time tAA 100 ns Chip enable access time tACE 100 ns 50 ns Output enable delay time tOE Output hold time tOH CE to output in High-Z tCHZ 50 ns OE to output in High-Z tOHZ 50 ns 0 ns 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude Input rise/fall time RATING 0.6 V to 2.4 V 10 ns Input/output reference level Output load condition 1.5 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A16 tAA (NOTE) CE tCHZ tACE (NOTE) OE/OE1/OE1 tOE tOHZ (NOTE) D0 - D7 tOH DATA VALID NOTE: The data becomes valid after the intervals, tAA, tACE, or tOE, from address input, chip enable, and output enable, respectively have been met. Figure 4. Timing Diagram 4 531V00-4 CMOS 1M MROM LH531V00 PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 5 LH531V00 CMOS 1M MROM 32TSOP (Type I) (TSOP032-P-0820) 0.30 [0.012] 0.10 [0.004] 0.50 [0.020] TYP. 32 17 18.60 [0.732] 18.20 [0.717] 1 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 16 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP 32-pin, 8 × 20 mm2 TSOP (Type I) ORDERING INFORMATION LH531V00 Device Type X Package D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) CMOS 1M (128K x 8) Mask-Programmable ROM Example: LH531V00D (CMOS 1M (128K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP) 531V00-5 6