PRELIMINARY CMOS 24M (3M × 8/1.5M × 16) Mask-Programmable ROM LH5324P00A FEATURES • 3,145,728 words × 8 bit organization (Byte mode) 1,572,864 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 440 mW (MAX.) Standby: 1650 µW (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Package: 44-pin, 600-mil SOP DESCRIPTION The LH5324P00A is a 24M-bit mask-programmable ROM organized as 3,145,728 × 8 bits (Byte mode) or 1,572,864 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS TOP VIEW 44-PIN SOP NC 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A10 A6 5 40 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 CE 12 33 BYTE GND 13 32 GND OE 14 31 D15/A-1 (LSB) D0 15 30 D7 D8 16 29 D14 D1 17 28 D6 D9 18 27 D13 D2 19 26 D5 D10 20 25 D12 D3 21 24 D4 D11 22 23 VCC 5324P00A-1 Figure 1. Pin Connections for SOP Package 5-307 LH5324P00A PRELIMINARY CMOS 24M Mask-Programmable ROM A20 44 A19 43 A10 40 A9 41 A8 42 A7 4 A6 5 29 D14 27 D13 25 D12 DATA SELECTOR/OUTPUT BUFFER ADDRESS BUFFER A13 37 A12 38 A11 39 31 D15 MEMORY MATRIX (3,145,728 x 8) (1,572,864 x 16) ADDRESS DECODER A18 2 A17 3 A16 34 A15 35 A14 36 A5 6 A4 A3 A2 7 8 9 COLUMN SELECTOR A1 10 A0 11 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 D5 24 D4 21 D3 19 D2 17 D1 CE 12 CE BUFFER OE 14 OE BUFFER BYTE 33 BYTE/WORD SWITCHOVER CIRCUIT TIMING GENERATOR 15 D0 SENSE AMPLIFIER ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND 5324P00A-2 Figure 2. LH5324P00A Block Diagram PIN DESCRIPTION SIGNAL A–1 – A20 D0 – D15 BYTE CE PIN NAME Address input NOTE SIGNAL PIN NAME 1 OE Output Enable input Data output 1 VCC Power supply (+5 V) Byte/word mode switch 1 GND Ground Chip Enable input NC NOTE No connection NOTE: 1. The D15 /A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 5-308 CMOS 24M Mask-Programmable ROM PRELIMINARY LH5324P00A TRUTH TABLE CE OE BYTE DATA OUTPUT ADDRESS INPUT A–1 (D15) D8 – D15 LSB MSB SUPPLY CURRENT NOTE D0 – D7 1 1 H L X H X X X X High-Z High-Z High-Z High-Z – – – – Standby (ISB) Operating (ICC ) L L L L H L – L D0 – D7 D0 – D7 L L L H D8 – D15 D8 – D15 High-Z High-Z A0 A–1 A–1 A20 A20 A20 Operating (ICC ) Operating (ICC ) Operating (ICC ) NOTE: 1. X = H or L; High-Z = High-impedance When the address inputs become ’High’ to both A19 and A20, the data outputs become ‘Unspecified’ since the data does not exist in this address area. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature VCC VIN VOUT – 0.3 to +7.0 – 0.3 to VCC + 0.3 – 0.3 to VCC + 0.3 V V V Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER Input ‘High’ voltage Input ‘Low’ voltage Output ‘High’ voltage Output ‘Low’ voltage Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance SYMBOL V IH VIL VOH VOL | ILI | | ILO | CONDITIONS I OH = –400 µA I OL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC MIN. MAX. UNIT 2.2 – 0.3 2.4 VCC + 0.3 0.8 V V V 0.4 V 10 10 µA ICC1 t RC = 150 ns ICC2 t RC = 1 µs CE = VIH CE = VCC – 0.2 V 3 300 f = 1 MHz T A = 25°C 10 10 ISB1 ISB2 CIN COUT 80 70 NOTE µA 1 mA 2 mA µA pF pF NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 5-309 LH5324P00A PRELIMINARY CMOS 24M Mask-Programmable ROM AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL MIN. Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 120 MAX. 120 120 60 5 50 50 UNIT ns ns ns ns ns ns ns NOTE 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition RATING 0.4 V to 2.6 V 10 ns 1.5 V 1.5 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. 5-310 CMOS 24M Mask-Programmable ROM PRELIMINARY LH5324P00A tRC A-1 - A20 tAA (NOTE) CE tACE tCHZ (NOTE) OE tOHZ tOE (NOTE) D0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 5324P00A-3 Figure 3. Byte Mode (BYTE = VIL) tRC A0 - A20 tAA (NOTE) CE tACE tCHZ (NOTE) OE tOHZ tOE (NOTE) D0 - D15 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 5324P00A-4 Figure 4. Word Mode (BYTE = VIH) 5-311 LH5324P00A PRELIMINARY CMOS 24M Mask-Programmable ROM PACKAGE DIAGRAM 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 44 23 13.40 [0.528] 13.00 [0.512] 1 16.40 [0.646] 15.60 [0.614] 14.40 [0.567] SEE DETAIL 22 0.20 [0.008] 0.10 [0.004] 28.40 [1.118] 28.00 [1.102] 2.9 [0.114] 2.5 [0.098] DETAIL 1.275 [0.050] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 2.9 [0.114] 2.5 [0.098] 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] 0 - 10° 0.80 [0.031] MAXIMUM LIMIT MINIMUM LIMIT 44SOP 44-pin, 600-mil SOP ORDERING INFORMATION LH5324P00A Device Type N Package 44-pin, 600-mil SOP (SOP044-P-0600) CMOS 24M (3M x 8 or 1.5M x 16) Mask-Programmable ROM Example: LH5324P00AN (CMOS 24M (3M x 8 or 1.5M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) 5324P00A-5 5-312