LH5324C00 FEATURES CMOS 24M (1.5M × 16) MROM PIN CONNECTIONS • 1,572,864 × 16 bit organization • Access time: 120 ns (MAX.) • Supply current: – Operating: 80 mA (MAX.) – Standby: 100 µA (MAX.) • TTL compatible I/O • Three-state output • Single +5 V Power supply • Static operation • When the address input at both A19 and A20 is high level, outputs become high impedance irrespective of CE or OE. • Package: 42-pin, 600-mil DIP • Others: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate) 42-PIN DIP TOP VIEW A18 1 42 A19 A17 2 41 A8 A7 3 40 A9 A6 4 39 A10 A5 5 38 A11 A4 6 37 A12 A3 7 36 A13 A2 8 35 A14 A1 9 34 A15 A0 10 33 A16 CE 11 32 A20 GND 12 31 GND OE 13 30 D15 D0 14 29 D7 D8 15 28 D14 D1 16 27 D6 D9 17 26 D13 D2 18 25 D5 D10 19 24 D12 D3 20 23 D4 D11 21 22 VCC 5324C00-1 Figure 1. Pin Connections DESCRIPTION The LH5324C00 is a 24M-bit mask-programmable ROM organized as 1,572,864 × 16 bits. It is fabricated using silicon-gate CMOS process technology. 1 LH5324C00 CMOS 24M (1.5M x 16) MROM A20 32 A19 42 A18 1 A17 2 A16 33 A15 34 A14 35 MEMORY MATRIX (1,572,864 x 16) A9 40 A8 41 A7 3 A6 4 DATA SELECTOR/OUTPUT BUFFER A10 39 28 D14 ADDRESS DECODER ADDRESS BUFFER A13 36 A12 37 A11 38 30 D15 A5 5 A4 A3 A2 6 7 8 COLUMN SELECTOR A1 9 A0 10 CE 11 CE BUFFER OE 13 OE BUFFER TIMING GENERATOR 26 D13 24 D12 21 D11 19 17 15 29 D10 D9 D8 D7 27 D6 25 D5 23 D4 20 D3 18 D2 16 D1 14 D0 SENSE AMPLIFIER 22 VCC 12 31 GND 5324C00-2 Figure 2. LH5324C00 Block Diagram PIN DESCRIPTION SIGNAL SIGNAL PIN NAME A0 - A20 Address input OE Output enable input D0 - D15 Data output VCC Power supply (+5 V) Chip enable input GND Ground CE 2 PIN NAME CMOS 24M (1.5M x 16) MROM LH5324C00 TRUTH TABLE CE OE A0 - A18 A19 DATA OUTPUT A20 SUPPLY CURRENT D0 - D15 H X X X X High-Z Standby (ISB ) L H X X X High-Z Operating (ICC) L L X L L Output Operating (ICC) L L X L H Output Operating (ICC) L L X H L Output Operating (ICC) L L X H H High-Z Operating (ICC) NOTES: 1. X = Don’t care; High-Z = High-impedance 2. When the address inputs become HIGH to both A19 and A20, the data does not exist in this address area, the data outputs become "High Impedance". ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC -0.3 to +7.0 V Input voltage VIN -0.3 to VCC + 0.3 V Output voltage VOUT -0.3 to VCC + 0.3 V Operating temperature TOPR 0 to +70 °C Storage temperature TSTG -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ± 10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Input ‘Low’ voltage VIL -0.3 0.8 V Output ‘High’ voltage VOH I OH = -400 µA 2.4 V Output ‘Low’ voltage VOL I OL = 2.0 mA 0.4 V Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 120 ns 80 t RC = 1 µs mA 2 ICC2 70 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V 100 µA 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance CIN COUT f = 1 MHz, t A = 25°C NOTES: 1. CE = VIH, OE = VIH 2. VIN = VIH or VIL, CE = VIL, output is open 3 LH5324C00 CMOS 24M (1.5M x 16) MROM AC ELECTRICAL CHARACTERISTICS (VCC = +5 V ± 10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time tRC 120 ns Address access time tAA 120 ns Chip enable access time tACE 120 ns Output enable delay time tOE 60 ns Output hold time tOH 0 ns tCHZ 50 ns tOHZ 50 ns tAHZ 60 ns Output floating time NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.6 V to 2.4 V Input signal rise time 10 ns Input signal fall time 10 ns Input reference level 1.5 V Output reference level 1.5 V Output load condition 1TTL + 100 pF NOTE: It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. 4 1 CMOS 24M (1.5M x 16) MROM LH5324C00 tRC A0 - A20 tAA (NOTE) CE tACE (NOTE) tCHZ OE tOHZ tOE (NOTE) D0 - D15 HI-Z tOH HI-Z DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. HI-Z = High Impedance. 5324C00-3 Figure 3. Byte Mode A0 - A18 A19, A20 CE tCHZ OE tOHZ tAHZ D0 - D15 HI-Z DATA VALID HI-Z NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. HI-Z = High impedance. 5324C00-4 Figure 4. Word Mode 5 LH5324C00 CMOS 24M (1.5M x 16) MROM PACKAGE DIAGRAM 42DIP (DIP042-P-0600) 42 DETAIL 22 13.45 [0.530] 12.95 [0.510] 0° TO 15° 1 0.30 [0.012] 0.20 [0.008] 21 54.10 [2.130] 53.50 [2.106] 4.55 [0.179] 3.95 [0.156] 15.24 [0.600] TYP. 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.90 [0.035] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 42DIP ORDERING INFORMATION LH5324C00 Device Type D Package 42-pin, 600-mil DIP (DIP42-P-600) CMOS 24M (1.5M x 16) Mask-Programmable ROM Example: LH5324C00D (CMOS (24M 1.5M x 16) Mask-Programmable ROM, 42-pin, 600-mil DIP) 5324C00-5 6