CXA1396D
8-bit 125 MSPS Flash A/D Converter
Description
The CXA1396D are 8-bit ultrahigh-speed flash A/D
converter ICs capable of digitizing analog signals at
the maximum rate of 125 MSPS. The digital I/O
levels of these A/D converters are compatible with
the ECL 100K/10KH/10K.
The CXA1396D is pin-compatible with the earlier
model CX20116. They can replace the earlier models
respectively, without any design changes, in most
cases. Compared with the earlier models, these new
models have been greatly improved in performance,
by incorporating advanced process, new circuit
design and carefully considered layout.
Features
• Ultrahigh-speed operation with maximum
conversion rate of 125 MSPS (Min.)
• Wide analog input bandwidth: 200MHz (Min. for
full-scale input)
• Low power consumption: 870mW (Typ.)
• Single power supply: –5.2V
• Low input capacitance
• Built-in integral linearity compensation circuit
• Low error rate
• Operable at 50% clock duty cycle
• Good temperature charactcristics
• Capable of driving 50Ω loads
42 pin DIP (Ceramic)
Structure
Bipolar silicon monolithic IC
Applications
• Digital oscilloscopes
• HDTV (high-definition TVs)
• Other apparatus requiring ultrahigh-speed A/D
conversion
Pin Configuration
Pins without name are NC pins (not connected).
AVEE
1
42
2
41 VRT
LINV
3
40
DVEE
4
39 AVEE
DGND1
5
38 AVEE
DGND2
6
37
(LSB) D0
7
36
D1
8
35 AGND
D2
9
34 VIN
D3 10
33 AGND
D4 11
32 VRM
D5 12
31 AGND
D6 13
30 VIN
29 AGND
(MSB) D7 14
DGND2 15
28
DGND1 16
27
DVEE 17
26 AVEE
MINV 18
25 AVEE
19
24
CLK 20
23 VRB
CLK 21
22
(Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94521A79-PS
CXA1396D
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVEE, DVEE
• Analog input voltage
VIN
• Reference input voltage
VRT, VRB, VRM
VRT – VRB
• Digital input voltage
• VRM pin input curent
• Digital output current
• Storage temperature
CLK, CLK, MINV, LINV
CLK – CLK
IVRM
ID0 to ID7
Tstg
Recommended Operating Conditions
• Supply voltage
AVEE, DVEE
AVEE – DVEE
AGND – DGND
• Reference input voltage
VRT
VRB
• Analog input voltage
VIN
• Pulse width of clock
TPW1
TPW0
• Operating temperature
Ta
–7 to +0.5
–2.7 to +0.5
–2.7 to +0.5
2.5
–4 to +0.5
2.7
–3 to +3
–30 to 0
–65 to +150
Min.
–5.5
–0.05
–0.05
–0.1
–2.2
VRB
4.0
4.0
–20
–2–
Typ.
–5.2
0
0
0
–2.0
V
V
V
V
V
V
mA
mA
°C
Max.
–4.95
+0.05
+0.05
+0.1
–1.8
VRT
+75
unit
V
V
V
V
V
ns
ns
°C
CXA1396D
Block Diagram
MINV
r1
VRT
Comparator
r/2
r
r
r
1
2
D7 (MSB)
•
•
•
r
63
D6
64
VIN
r
D5
65
r2
r
VRM
r
OUTPUT
r
126
127
128
ENCODE LOGIC
r
•
•
•
r
D1
•
•
•
191
D0 (LSB)
192
VIN
r
193
r
r
r3
r/2
•
•
•
254
255
VRB
CLK
CLK
D3
D2
129
r
D4
CLOCK
DRIVER
LINV
–3–
CXA1396D
Pin Description and I/O Pin Equivalent Circuit
Pin No. Symbol
29, 31,
33, 35
1, 25,
26, 38,
39
AGND
AVEE
I/O
—
—
Standard
voltage
level
Equivalent circuit
Description
0V
Analog GND.
Used as GND for input buffers
and latches of comparators.
Isolated from DGND1, DGND2.
–5.2V
Analog VEE.
–5.2V (Typ.).
Internally connected with DVEE
(resistance: 4 to 6Ω).
A ceramic chip capacitor of at
least 0.1µF should be used to
connect to AGND and be
placed near the pins.
DGND1
r
21
CLK
CLK input
r
CLK
I
20
r
ECL
r
CLK
CLK
DVEE
r
r
Complementary input to CLK.
With open connection, kept at
threshold voltage (–1.3V).
Device is operable without CLK
input, but use of omplementary
inputs of CLK and CLK is
recommended to obtain the
stable high-speed operation.
5, 16
DGND1
—
0V
Digital GND for internal
circuits.
6, 15
DGND2
—
0V
Digital GND for output
transistors.
4, 17
DVEE
—
Digital VEE.
Internally connected with AVEE
(resistance: 4 to 6Ω).
A ceramic chip capacitor of at
least 0.1µF should be used to
connect to DGND near the
pins.
–5.2V
–4–
CXA1396D
Pin No. Symbol
I/O
Standard
voltage
level
Equivalent circuit
Description
DGND2
7
D0
8
D1
9
D2
10
D3
11
D4
12
D5
13
D6
14
D7
Di
O
Data outputs.
External pull-down resistors
are required.
ECL
MSB of data outputs.
External pull-down resistor is
required.
DVEE
DGND1
3
LINV
I
Input pin for D0 (LSB) to D6
output polarity inversion (see
output code table).
With open connection, kept at
"L" level.
ECL
r
LINV
or
MINV
18
MINV
LSB of data outputs.
External pull-down resistor is
required.
I
r
r
–1.3V
Input pin for D7(MSB) output
polarity inversion (see output
code table).
With open connection, kept at
"L" level.
ECL
DVEE
r
AGND
Analog input pins.
These two pins must be
connected externally, since
they are not internally
connected.
See Application Note for
precautions.
VIN
30, 34
VIN
I
VRT
to
VRB
VIN
AVEE
–5–
CXA1396D
Pin No. Symbol
I/O
Standard
voltage
level
Equivalent circuit
VRT
23
VRB
I
Description
Reference voltage (bottom).
Typically –2V.
A ceramic capacitor of at least
0.1µF and a tantalum capacitor
of at least 10µF should be
used to connect to AGND near
the pins.
r1
–2V
r/2
r
Comparator
1
Comparator
Comparator
2
.
.
.
127
Comparator
128
Comparator
129
Comparator
130
.
.
.
.
.
.
.
Comparator
255
r
32
VRM
I
VRB/2
r
VRM
r2
Reference voltage mid point.
Can be used as a pin for
integral linearity compensation.
r
r
r
41
VRT
I
0V
r
VRB
2, 19,
22, 24,
27, 28,
36, 37,
40, 42
NC
—
r3
r/2
Reference voltage (top).
Typically 0V.
When a voltage except for
AGND is applied to this pin, a
ceramic capacitor of at least
0.1µF and a tantalum capacitor
of at least 10µF should be used
to connect to AGND near the
pins.
Unused pins.
No internal connections have
been made to these pins.
Connecting them to AGND or
DGND on PC board is
recommended.
—
–6–
CXA1396D
Electrical Characteristics
(Ta = 25°C, AVEE = DVEE = –5.2V, VRT = 0V, VRB = –2V)
Symbol
Item
Condition
n
Resolution
DC characteristics
EIL
Integral linearity error
Differential linearity error EDL
Analog input
Analog input capacitance
Analog input resistance
Input bias current
CIN
RIN
IIN
Reference inputs
Reference resistance
Offset voltage VRT
VRB
RREF
EOT
EOB
Digital inputs
Logic H level
Logic L level
Logic H current
Logic L current
Input capacitance
VIH
VIL
IIH
IIL
Typ.
Fc = 125MSPS
Fc = 125MSPS
±0.3
±0.3
VIN = –1V + 0.07Vrms
VIN = –1V
75
8
0
Input connected to –0.8V
Input connected to –1.6V
±0.5
±0.5
LSB
LSB
17
190
130
320
pF
kΩ
µA
110
19
15
155
32
24
Ω
mV
mV
–1.50
50
50
V
V
µA
µA
pF
0
–50
7
Digital outputs
Logic H level
Logic L level
Output rising time
Output falling time
VOH
VOL
Tr
Tf
RL = 50Ω to –2V
RL = 50Ω to –2V
RL = 50Ω to –2V, 20% to 80%
RL = 50Ω to –2V, 80% to 20%
DG
DP
VIN = 2Vp-p, 3dB down
Input = 1MHz, FS
Clock = 125MHz
Input = 31.5MHz, FS
Clock = 125MHz
Input = 31.249MHz, FS
Error > 16LSB
Clock = 125MHz
NTSC 40IRE mod.ramp,
Fc = 125MSPS
Dynamic characteristics
Input bandwidth
S/N ratio
Error rate 10–9 TPS∗1
125
3.0
4.0
4.0
10
1.5
3.6
0.8
1.0
46
MHz
dB
40
dB
200
Power supply
Supply current
Power consumption∗2
10–9
}
IEE
Pd
–230
∗1 TPS: times Per Sample
(VRT – VRB)2
RREF
–7–
MSPS
ps
ns
ns
ns
ns
V
V
ns
ns
–1.62
{
Error rate
4.2
–1.10
{
{
Unit
bits
–1.13
Fc
Taj
Tds
Tdo
TPW1
TPW0
Differential gain error
Differential phase error
Max.
8
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Output delay
H pulse width of clock
L pulse width of clock
∗2 Pd = IEE • VEE +
Min.
TPS∗1
1.0
0.5
%
deg
–160
870
mA
mW
CXA1396D
Output Code Table
VIN∗
MINV
LINV
Step
1
1
D7
0V
0
1
–1V
127
128
254
255
–2V
0
1
1
0
D0 D7
0 0 0 …… 0 0
0 0 0 …… 0 0
0 0 0 …… 0 1
:
:
0 1 1 …… 1 1
1 0 0 …… 0 0
:
:
1 1 1 …… 1 0
1 1 1 …… 1 1
1 1 1 …… 1 1
D0
D7
1 0 0 …… 0 0
1 0 0 …… 0 0
1 0 0 …… 0 1
:
:
1 1 1 …… 1 1
0 0 0 …… 0 0
:
:
0 1 1 …… 1 0
0 1 1 …… 1 1
0 1 1 …… 1 1
0
0
D0
0 1 1 …… 1 1
0 1 1 …… 1 1
0 1 1 …… 1 0
:
:
0 0 0 …… 0 0
1 1 1 …… 1 1
:
:
1 0 0 …… 0 1
1 0 0 …… 0 0
1 0 0 …… 0 0
D7
D0
1 1 1 …… 1 1
1 1 1 …… 1 1
1 1 1 …… 1 0
:
:
1 0 0 …… 0 0
0 1 1 …… 1 1
:
:
0 0 0 …… 0 1
0 0 0 …… 0 0
0 0 0 …… 0 0
∗ VRT = 0V, VRB = –2V
Timing diagram
Tds
N
N+1
Analog in
Tpw1
N+2
Tpw0
CLK
CLK
N–1
Digital out
80%
20%
Tdo
Tr
–8–
N
80%
N+1
20%
Tf
CXA1396D
Electrical Characteristics Test Circuit
Maximum conversion rate test circuit
Signal
Source
Vin
fCLK
– 1kHz
4
2Vp-p Sine Wave
8
CLK
A
ECL
Latch
CXA1396D
B
CLK
Comparator
A>B
Pulse
Counter
ECL
Latch
+
DATA 16
Signal
Source
1/4
fCLK
Differential gain error test circuit
Differential phase error test circuit
(CX20202A-1)
VIN
Amp
10Ω
8
DUT
CXA1396D
CLK
ECL
Latch
8
10bit
D/A
CLK
NTSC
Signal
Source
Delay
VBB
Vector
Scope
SG (CW)
50
DG.DP
Integral linearity error test circuit
Differential linearity error test circuit
+V
S2
S1
S1: A < B: ON
S2: A > B: ON
–V
A<BA>B
Comparator
VIN
8
DUT
CXA1396D
A8
to
A1
A0
B8
to
B1
B0
"0"
8
Buffer
"1"
DVM
8
CLK (125MHz)
Controller
–9–
00000000
to
11111110
CXA1396D
Power Supply Current Test Circuit
Analog input bias current test circuit
–1V
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
CXA1396D
A
IIN
32
12
31
13
30
14
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
–2V
A IEE
–5.2V
Sampling delay test circuit
Aperture jitter test circuit
Aperture jitter test method
0V
67.5MHz
VIN
–1V
–2V
Amp
OSC1
φ: Variable
CLK
VIN
8
CXA1396D
fr
VIN
129
128
127
126
125
CLK
Aperture jitter
Logic
Analizer
∆v
∆t
CLK
t
1024
samples
OSC2
σ (LSB)
ECL
Buffer
67.5MHz
Apeature jitter is defined as follows:
Taj = σ/
∆v
∆t
= σ/(
256
2
× 2πf ),
Where σ (unit : LSB) is the deviation of the output codes when the input
frequency is exactly the same as the clock and is sampled at the
largest slew rate point.
– 10 –
CXA1396D
8-bit, 125MSPS ADC Evaluation board
Description
The CXA1396D EVALUATION BOARD WITH DAC is a tool for customers to evaluate the performance of the
CXA1396D (8-bit, 125MSPS, high-speed A/D converter). In addition to indispensable features such as the
reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier
input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed
DAC, and the 20-pin cable connector for digital outputs.
This evaluation board provides full performance of the CXA1396D and it is designed to facilitate evaluation.
Features
• Resolution: 8bits
• Maximum conversion rate: 125MSPS
• Supply voltage: +5.0V, –5.2V, –2.0V
• Two analog inputs (Direct input, buffer amplifier input)
• Clock level converter: Sine wave to ECL level signal
• Reference voltage adjustment circuit for the A/D converter
• Built-in clock frequency decimation circuit: (1/1 to 1/16)
Fig. 1. Block Diagram
–5.2V (A)
H
L
VRB
–2V
VR2
(2k)
–5.2V (A)
SW1
VR3
(1k)
DIGITAL OUT
(CONNECTOR)
LINV MINV
Vin
OFFSET
VR1
(2k)
SW2
VRB
J1
A
1k
(D7 to D0)
8
VRM
DATA
LATCH
8
8
BUFFER
CXA1396D
B
CLK
C
AMP.IN
240
CLK
X (–2)
51
Vin
(D7 to D0)
2 (CLK.CLK)
8
D
51
DIR.IN
D/A
CONVERTER
0.1µ
DECIMATOR
CLK
CLK
SW3
1/1 to 1/16
+5V
–5.2V (A)
AGND
–5.2V (D)
– 11 –
DGND
–2V (D)
D/A OUT
CXA1396D
Supply Current
Item
Min.
–5.2V
+5.0V
–2.0V
Typ.
Max.
Unit
0.85
15
0.45
1.0
30
0.6
A
mA
A
(Note: Supply current –2.0V is the value when Rn10, Rn11 and Rn12 are not mounted.)
Analog Input (DIR. IN, AMP. IN)
Item
Min.
Input voltage (DIR. IN)
(AMP. IN) ∗1
Input impedance
Typ.
–2.0
–0.5
Max.
Unit
0
+0.5
V
V
Ω
Max.
Unit
50
(∗1: Adjustable by VR1)
Clock Input (CLK)
Item
Min.
Input voltage
(Peak to Peak)
Input impedance
Typ.
1.0
Vp-p
50
Ω
0
1
1 0 0 …… 0 0
1 0 0 …… 0 1
:
:
1 1 1 …… 1 1
0 0 0 …… 0 0
:
:
0 1 1 …… 1 0
0 1 1 …… 1 1
1
0
0 1 1 …… 1 1
0 1 1 …… 1 0
:
:
0 0 0 …… 0 0
1 1 1 …… 1 1
:
:
1 0 0 …… 0 1
1 0 0 …… 0 0
Digital Output (D0 to D7)
ECL 10KH level
Clock Output
ECL 10KH level, complementary output
Output Code Table
MINV
LINV
VIN
0V
:
:
:
:
:
:
:
:
–2V
0
0
1 1 1 …… 1 1
1 1 1 …… 1 0
:
:
1 0 0 …… 0 0
0 1 1 …… 1 1
:
:
0 0 0 …… 0 1
0 0 0 …… 0 0
– 12 –
1
1
0 0 0 …… 0 0
0 0 0 …… 0 1
:
:
0 1 1 …… 1 1
1 0 0 …… 0 0
:
:
1 1 1 …… 1 0
1 1 1 …… 1 1
CXA1396D
Fig. 2. Timing Chart
N
A/D input pin
Vin
(DIR. IN, AMP. IN)
N+1
PCB input pin
CLK
CLK
A/D clock
CLK
D7 to D0
N–1
N
PCB output pin
D7 to D0
(For 1/1 frequency division)
N–2
N–1
A/D output
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
CLK
(For 1/1 frequency division)
PCB output pin DATA OUT
(For 1/2 frequency division)
N–4
N–2
N
Tdh
1.8ns
(Typ)
CLKN
PCB output pin
CLK
(For 1/2 frequency division)
– 13 –
CXA1396D
Adjustment Methods and Notes on Operation
1) Vin Offset (VR1)
The volume to adjust the signal range (0V center assumed) with the A/D converter input range when a
waveform is input through AMP. IN.
2)
A/D Full Scale (VR2)
The volume to adjust A/D converter VRB voltage.
3)
Linearity (VR3)
The volume to adjust VRM (linearity) voltage. When DIR. IN input selected and it is supplied through the
capacitor, VR3 can be used to adjust the input offset voltage.
4)
D/A Full Scale (VR4)
The volume to adjust D/A output full scale (–1V).
5)
J1 (Input selection)
A: Shorts to adjust VRM voltage.
B: Shorts to supply DC voltage to Vin.
C: Shorts to select AMP.IN input.
D: Shorts to select DIR.IN input.
[Jumper Position at Shipment]
J1
A
Input through the
B
buffer amplifier
C
D
J1
A
B
C
D
J1
Input through the A
B
buffer amplifier
(When the linearity C
D
is adjusted)
0.1µF
6)
SW1
The switch for LINV High/Low.
7)
SW2
The switch for MINV High/Low.
8)
SW3 (Decimation)
The switch to select clock frequency decimation.
Switch position: decimation ratio
0: 1/1
1: 1/2
2: 1/4
3: 1/8
4: 1/16
9)
SW4 (D/A INV)
The switch for D/A converter output inversion.
– 14 –
Input through the capacitor
(When the offset is adjusted using the
DIR IN. at the evaluation board)
CXA1396D
10) Rn10, Rn11 and Rn12 are not mounted at shipment. They are not required during evaluation.
11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce
the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300
mil, and there is φ1.2mm through hole at each. The signal and GND locations are suit for a Tektronix GND
tip (part number 013-1185-00).
φ1.2mm
GND
Probe point
300mil
Fig. 3
12) D/A converter (IC13) input data (waveform probe pins P21 through P28) are the complementary signals of
the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction
of reproduced waveform can agree with the A/D input signal converter.
13) The part unmber of the digital output connector is KEL 8830E-020-170S. A corresponding connector and
cable assembly is JUNKOSMA KBO020MCG50BI.
– 15 –
CXA1396D
PCB Circuit Schematic
+5V (A)
FERRITE
BEAD
VRB
P2
AGND
R9
AGND
1.3k
A/D Full Scale VR2
2k
–5.2V (A)
R5/11k
R6
240
Vin Offset
Q1
2SA970
VR3
1k
8 7
6
5
IC3
TL431CP
4
C19
0.1µ
AGND
C20
10
AGND
IC1-2
TL4558
R8
510
VR1
2K
Linearity
AGND
C18
0.1µ
VRM P1
C8
0.1µ
–5.2V (A)
R4
2 6 22k
1
3
4
IC1-1 C3
TL4558 0.1µ
–5.2V (A) AGND
R7
1k AGND
+5V (A)
C4
3.3µ
C12
C7
0.1µ
1µ
AGND
AGND AGND
AGND AGND R13
R2
R10 R11 1k
240
510 43
2 7 6
AMP.IN
3
R1
4
IC4
51
CLC404AJP R12
C6
51
AGND AGND
1µ
AGND
AGND
C11
0.1µ
–5.2V (A)
AGND
CLKN 20
23 VRB
NC 19
24 NC
25 AVEE
MINV 18
26 AVEE
DVEE 17
D
J1
VIN P5
AGND P4
AVEE P3
–5.2V (A)
DIR.IN
C15
1µ
C16
0.1µ
D7 14
30 VIN
D6 13
AGND
D7
#2
–5.2V (D)
#3
DGND
#4
D5 12
P14
P15
D4
D5
D4 11
D3 10
34 VIN
D2 9
35 AGND
D1 8
D0
7
38 AVEE
DGND1 5
39 AVEE
DVEE
40 NC
LINV 3
4
DGND
C25
0.1µ
AVEE
C26
1µ
–5.2V (D)
C24
0.1µ
NC 2
42 NC
DGND
P6
DGND2 6
37 NC
DGND
P17
#1
DVEE
41 VRT
AGND
C27
0.1µ
DGND2 15
29 AGND
C22
0.1µ
–2V (D)
P16
D6
28 NC
36 NC
AGND
AGND AGND
R16
51
P17
33 AGND
AGND
C25
0.1µ
DGND1 16
32 VRM
C17
0.1µ
B
C
R17
51
27 NC
31 AGND
A
P9
P8
CLK
CLKN
CLK 21
22 NC
IC6: CXA1396D
C9
0.1µ
D2
D3
P12
P13
1
#5
#6
FERRITE BEAD
#7
–5.2V (A)
#8
SW1
LINV
D1
P10
P11
D0
D1
SW2
MINV
D2
H
D3
L
DGND
R15
330
–5.2V (D)
#9
#10
–2V (D)
DGND
C2
0.1µ
Cout 15
3 Aout
Cout_ 14
4 Ain_
5 Ain
Cin 13
VBB 11
7 Bout
Bin 10
8 VEE
DGND
Rn1
51
Bin_ 9
Rn1
–5.2V (D)
DGND
C5
0.1µ
Q1 15
3 Q3
Q0 14
5 D3
Rn1
51
Rn1
51
2 Q2
4 Cout_
Rn1
51
Cin_ 12
6 Bout_
VCC2 16
1 VCC1
DGND
C10
0.1µ
C13
0.1µ
C14
0.1µ
DGND DGND
–2V
(D) DGND
DGND
CLK 13
D0 12
R14
51
–2V (D)
6 D2
D1 11
7 S2
Cin_ 10
8 VEE
S1 9
VCC1 16
1 VCC2
DGND
DGND 2 Enable_
DGND Rn2
3 X3
Rn2
51
4 X2
Rn2
51
5 X1
Rn2
51
6 X0
Rn2
IC7: 10H164
R3
51
VCC2 16
2 Aout_
IC5: 10H136
C1
0.1µ
CLK
1 VCC1
IC8: 10H116
DGND
C23
0.1µ
#11
Z 15
X7 14
X6 13
X5 12
R18 C31
51 0.1µ
X4 11
51
C37
0.1µ
C22
C21 0.1µ
0.1µ
–5.2V (D)
DGND
DGND DGND
7 A
C 10
8
B 9
VEE
–5.2V (D)
–2V (D) DGND
C29
0.1µ
DGND
C30
0.1µ
DGND
SW3
Decimation
DGND
#12
#13
#14
– 16 –
CXA1396D
Rn6
Rn6
75
–2V (D)
Rn6
75
Rn6
75
Rn6
75
2
Q0
3
4
Rn4
#1
5
Rn4
75
#2
Rn4
75
Rn4
75
#3
#4
Q1
Q2
D0
DGND
2 Aout_ Dout_ 15
3
Q3 13
4 Ain
D5 12
6
D1
D4 11
D2
D3 10
8
VEE
6
CLK
P18
C41
0.1µ
DGND
R19
51
KEL: 8830E-020-170S
(TOP VIEW)
Rn12
Rn12
51
Rn11
Cout 11
Bout
Cin 10
8 VEE
Dout 9
4
DGND
6
DGND
8
7
DGND
D3
10
9
DGND
D4
12
11
D5
DGND
13
14
D6
DGND
15
16
DGND
D7
17
18
CLK DGND
19
20
DGND
CLKN
5
D2
51
Rn12
Din 13
7 Bin
3
D1
51
Rn12
COM
IN 12
51
Rn11
51
Rn11
51
Rn11
C52
0.1µ
–5.2V (D)
DGND
–2V (D)
51
Rn11
Rn10
–5.2V (D)
–2V (D)
DGND
–2V (D)
DGND
75
Rn10
Rn5
75
Rn10
Rn5
75
Rn5
75
C51
0.1µ
–2V (D)
DGND
2
VCC2 16
VCC1
–2V (D)
Q5 15 DGND
Q0
DGND
75
Rn10
Rn5
75
1
DIGITAL OUT
75
Rn10
Rn5
75
2
DGND
1
D0
51
Rn12
DGND
Cout_ 14
Bout_
5 Aout
CLK 9
C36 C26
0.1µ 0.1µ
VCC2 16
1 VCC1
Q4 14
7
Rn4
75
–2V (D)
DGND
Q5 15
DGND
C42
0.1µ
DGND
VCC2 16
IC12: 10H101
VCC1
IC10: 10H176
DGND
1
CONNECTOR
C53
0.1µ
C40
0.1µ
DGND
DGND
DGND
P34 +5V (A)
VCC2 16
1 VCC1
+5V (A)
2 Aout_ Dout_ 15 DGND
C57
33µ
Q1
Q2
5
D0
6
D1
Rn3
#5
Rn3
75
#6
Rn3
75
#7
7
Rn3
75
#8
C24
0.1µ
8
Rn3
75
Q4 14
3
Q3 13
4 Ain
D5 12
5 Aout
D4 11
6
D3 10
D2
C39
0.1µ
CLK 9
VEE
–5.2V (D)
DGND
DGND
Bout_
Cout_ 14
IC11: 10H101
3
4
IC9: 10H176
AGND
P33 AGND
AGND
Din 13
AGND
COM 12
IN
P32
Cout 11
Bout
7 Bin
Cin 10
8 VEE
Dout 9
–5.2V (A)
–5.2V (A)
C56
33µ
AGND
P31 –5.2V (D)
–5.2V (D)
–5.2V (D)
C55
33µ
C35
0.1µ
DGND
–2V (D)
P30 DGND
DGND
DGND
DGND
P29 –2V (D)
–2V (D)
#9
–2V (D)
#10
DGND
C45
0.1µ
VCC2 16
2
Aout_
Cout 15
Aout
Cout_ 14
3
4 Ain_
5
6
Ain
Bout_
7 Bout
C34
0.1µ
IC8: 10H116
DGND
#11
1 VCC1
Rn9
8 VEE
DGND –5.2V (D)
DGND
D5 P26
D4 P25
Cin 13
Cin_ 12
VBB 11
Bin 10
Bin_ 9
75
Rn9
D6 P27
D1 P22
DGND
R20
51
D0 P21
C38
0.1µ
VREF 27
75
Rn9
3 D3
AVEE 26
75
Rn9
4 D4
NC 25
5 D5
NC 24
Rn8
D2 P23
C37
0.1µ
75
Rn8
6 D6
75
Rn8
7 D7
75
Rn8
8 D8
75
Rn8
9 D9
OUT 20
10 LSB
NC 19
C44
0.1µ
–2V (D) DGND
DGND –2V (D)
Rn7
#12
51
Rn7
CLKN P20
51
Rn7
#13
CLK P19
51
Rn7
C43
0.1µ
DGND
1 MSB AGND2 28
2 D2
75
D3 P24
R22 C49
240 0.1µ
Rn9
IC13: CX20202A-1
DGND
D7 P28
#14
C54
33µ
51
Rn7
–2V (D)
C48
R21
0.1µ VR4 1k
2k
D/A Full Scale
IC14
TL431CP
–5.2V (A)
NC 23
NC 22
NC 21
D/A OUT
AGND
11 NC AGND1 18
AGND
12 NC
DGND 17
DGND
DGND
AGND
C50
33µ
13 CLKN
14 CLK
SW4
D4
D/A INV L
DGND
INV 16
DVEE 15
C46
0.1µ
D5
C47
0.1µ
–5.2V (D)
DGND
DGND
D6
H
R23
3.2k
–5.2V (D)
– 17 –
CXA1396D
Characteristic Graph
Fig. 5. Gain vs. Input frequency
(CLK = 125MHz)
2
0
Gain [dB]
–2
–4
–6
–8
–10
10
100
Input frequency [MHz]
Fig. 6. SNR vs. Input frequency
(CLK = 125MHz)
50
DIR. IN
AMP. IN
45
SNR [dB]
40
35
30
25
20
10
Input frequency [MHz]
1
100
Fig. 7. 2nd, 3rd harmonic distortion vs. Input frequency
(CLK = 125MHz)
2nd, 3rd harmonic distortion [dB]
–20
2nd DIR. IN
2nd AMP. IN
3rd DIR. IN
3rd AMP. IN
–30
–40
–50
–60
–70
–80
1
10
Input frequency [MHz]
100
Measurement data
Figs. 5, 6 and 7 show the characteristic graphs.
DIR. IN is the characteristic where the signal is directry input to the ADC and AMP. IN is the characteristic
where the signal is input to ADC through the amplifier.
– 18 –
CXA1396D
Parts Layout
– 19 –
CXA1396D
Printed Pattern
1st layer
4th layer
Component plane (Top View)
Solder plane (Top View)
– 20 –
CXA1396D
2nd layer
3rd layer
GND plane (Top View)
Power supply plane (Top View)
– 21 –
CXA1396D
Package Outline
Unit: mm
42PIN DIP (CERAMIC) 600mil
+ 0.05
0.25 – 0.02
53.4 ± 0.5
13.2 ± 0.2
22
15.24 ± 0.25
42
1
0° to 15°
21
0.46 ± 0.1
1.0 ± 0.1
6.91 MIN
6.6 MIN
3.3 MIN
1.0 MIN
2.54
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
PACKAGE MATERIAL
CERAMIC
DIP-42C-01
LEAD TREATMENT
GOLD PLATING
∗DIP042-C-0600-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
6.7g
JEDEC CODE
– 22 –