LH53B16R00 CMOS 16M (1M × 16/512K × 32) MROM FEATURES PIN CONNECTIONS • 1,048,576 × 16 bit organization (Word mode: W = VIL) 524,288 × 32 bit organization (Double Word mode: W = VIH) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: – Operating: 180 mA (MAX.) – Standby: 300 µA (MAX.) • TTL compatible I/O TOP VIEW 70-PIN SSOP A0 1 70 A1 2 69 NC NC A2 3 68 NC A3 4 67 W A4 5 66 OE A5 6 65 CE VCC 7 64 GND D0 8 63 D31/A-1 (NOTE) D16 9 62 D15 D1 10 61 D30 D17 11 60 D14 GND 12 59 GND • Single +5 V power supply VCC 13 58 VCC D2 14 57 • Static operation D29 D18 15 56 D13 D3 16 55 D28 D19 17 54 D12 D4 18 53 D27 D20 19 52 D11 • Three-state outputs • Package: 70-pin, 500-mil SSOP • Others: – Non programmable – Not designed or rated as radiation – hardened – CMOS process (P type silicon substrate) DESCRIPTION The LH53B16R00 is a 16M-bit CMOS mask ROM (mask-programmable-read-only memory) organized as 1,048,576 × 16 bits (Word mode) or 524,288 × 32 bits (Double Word mode). It is fabricated using silicon-gate CMOS process technology. D5 20 51 D26 D21 21 50 D10 GND 22 49 GND VCC 23 48 VCC D6 24 47 D25 D22 25 46 D9 D7 26 45 D24 D23 27 44 D8 GND 28 43 VCC A6 29 42 NC A7 30 41 A18 A8 31 40 A17 A9 32 39 A16 A10 33 38 A15 A11 34 37 A14 A12 35 36 A13 NOTE: D31/A-1 pin becomes LSB address input (A-1) when the W pin is set to be LOW in word mode, and data output (D31) when set to be HIGH in double word mode. 53B16R00-1 Figure 1. Pin Connections 1 LH53B16R00 CMOS 16M (1M x 16/512K x 32) MROM 63 D31 61 D30 57 D29 55 D28 53 D27 51 D26 A18 41 A17 40 32 31 30 ADDRESS DECODER A9 A8 A7 A6 ADDRESS BUFFER A13 36 A12 35 A11 34 A10 33 DATA SELECTOR/OUTPUT BUFFER MEMORY MATRIX (1,048,576 x 16) (524,288 x 32) A16 39 A15 38 A14 37 29 COLUMN SELECTOR A5 6 A4 5 A3 4 A2 3 CE 65 CE BUFFER OE 66 OE BUFFER TIMING GENERATOR SENSE AMPLIFIER 47 45 27 25 21 19 D25 D24 D23 D22 D21 D20 17 15 11 9 D19 62 60 56 54 52 50 D15 D14 D13 D12 D11 D10 46 44 26 24 D9 D8 D7 20 18 16 14 10 8 D5 D4 D3 D2 D1 D0 D18 D17 D16 D6 12 22 W 67 WORD/DOUBLE WORD SWITCHOVER CIRCUIT ADDRESS BUFFER 28 ADDRESS BUFFER 49 GND 59 64 63 A-1 1 A0 2 A1 7 13 23 43 48 58 VCC 53B16R00-2 Figure 2. LH53B16R00 Block Diagram 2 CMOS 16M (1M x 16/512K x 32) MROM LH53B16R00 PIN DESCRIPTION SIGNAL A-1 - A1 PIN NAME SIGNAL Address input (page mode operation) A2 - A18 Address input D0 - D31 Data output ×16 bit / ×32 bit (word/double word) mode select input W PIN NAME CE Chip enable input OE Output enable input VCC Power pin (+5 V) GND Ground NC No connection TRUTH TABLE CE OE W DATA OUTPUT ADDRESS INPUT A-1 (D31) D0 - D15 D16 - D31 LSB MSB H L X H X X X X High-Z High-Z High-Z High-Z L L L L H L L D0 - D15 D0 - D15 D16 - D31 A0 A18 L L L H D16 - D31 High-Z High-Z A-1 A-1 A18 A18 SUPPLY CURRENT Standby (ISB) Operating Operating Operating Operating NOTE: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature VCC VIN VOUT TOPR -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 V V V °C Storage temperature TSTG -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V 3 LH53B16R00 CMOS 16M (1M x 16/512K x 32) MROM DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage V IH 2.2 VCC +0.3 V Input ‘Low’ voltage VIL -0.3 0.8 V Output ‘High’ voltage VOH 0.4 V VOL I OH = -400 µA I OL = 2.0 mA 2.4 Output ‘Low’ voltage V V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 120 ns 10 180 µA µA mA 1 2 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance | ILI | | ILO | ICC1 CIN f = 1 MHz, t A = 25°C COUT 10 300 10 µA pF 10 pF NOTES: 1. CE = VIH, OE = VIH, output is open 2. VIN = VIH, VIL, CE = VIL, output is open AC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER Read cycle time SYMBOL MIN. MAX. UNIT NOTE tRC 120 120 ns 120 50 ns ns 50 ns ns tAA Page address access time tACE tAPA Output enable delay time tOE Output hold time tOH 5 tCHZ 40 ns tOHZ 40 ns Address access time Chip enable access time Output floating time ns NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER Input voltage amplitude Input signal rise time Input signal fall time Input/output reference level Output load condition 4 RATING 0.4 V to 2.6 V 10 ns 10 ns 1.5 V 1TTL + 100 pF 1 CMOS 16M (1M x 16/512K x 32) MROM LH53B16R00 tRC A-1 - A18 (A0 - A18) tAA (NOTE) CE tCHZ tACE (NOTE) OE tOE (NOTE) tOHZ tOH D0 - D15 (D0 - D31) DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, tAPA, or tOE, have concluded. 53B16R00-3 Figure 3. Read Cycle A2 - A18 A-1 - A1 (A0 - A1) tAA tAPA tAPA (NOTE) (NOTE) (NOTE) tCHZ CE tOHZ tACE (NOTE) OE tOE tOH tOH tOH tOH (NOTE) D0 - D15 (D0 - D31) DATA VALID DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, tAPA, or tOE, have concluded. DATA VALID DATA VALID 53B16R00-4 Figure 4. Page Mode Read Cycle 5 LH53B16R00 CMOS 16M (1M x 16/512K x 32) MROM PACKAGE DIAGRAM 70SSOP (SSOP70-P-500) 0.40 [0.015] 0.20 [0.008] .08 [0.003] TYP. 0.15 [0.006] M 36 70 12.90 [0.508] 12.50 [0.492] 1 16.20 [0.638] 15.60 [0.614] 14.60 [0.575] 14.00 [0.551] SEE DETAIL 35 28.8 [1.134] 28.4 [1.118] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.10 [0.004] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] DETAIL 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 0 - 10° DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 70SSOP ORDERING INFORMATION LH53B16R00 Device Type N Package 70-pin, 500-mil SSOP (SSOP70-P-500) CMOS 16M (1M x 16 or 500K x 32) Mask-Programmable ROM with page mode operation Example: LH53B16R00N (CMOS 16M (1M x 16 or 500K x 32) Mask-Programmable ROM, 70-pin, 500-mil SSOP) 53B16R00-5 6